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BJ125.
Processor May Livelock During On Demand Clock Modulation
Problem:
The processor may livelock when (1) a processor thread has enabled on demand clock
modulation via bit 4 of the IA32_CLOCK_MODULATION MSR (19AH) and the clock
modulation duty cycle is set to 12.5% (02H in bits 3:0 of the same MSR), and (2) the
other processor thread does not have on demand clock modulation enabled and that
thread is executing a stream of instructions with the lock prefix that either split a
cacheline or access UC memory.
Implication:
Program execution may stall on both threads of the core subject to this erratum.
Workaround:
This erratum will not occur if clock modulation is enabled on all threads when using on
demand
IA32_CLOCK_MODULATION MSR is 18.75% or higher.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ126.
The Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging
Problem:
When 32-bit paging is in use, the processor should use a page directory located at the
32-bit physical address specified in bits 31:12 of CR3; the upper 32 bits of CR3 should
be ignored. Due to this erratum, the processor will use a page directory located at the
64-bit physical address specified in bits 63:12 of CR3.
Implication:
The processor may use an unexpected page directory or, if EPT (Extended Page Tables)
is in use, cause an unexpected EPT violation. This erratum applies only if software
enters 64-bit mode, loads CR3 with a 64-bit value, and then returns to 32-bit paging
without changing CR3. Intel has not observed this erratum with any commercially
available software.
Workaround:
Software that has executed in 64-bit mode should reload CR3 with a 32-bit value
before returning to 32-bit paging.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ127.
EPT Violations May Report Bits 11:0 of Guest Linear Address
Incorrectly
Problem:
If a memory access to a linear address requires the processor to update an accessed or
dirty flag in a paging-structure entry and if that update causes an EPT violation, the
processor should store the linear address into the "guest linear address" field in the
VMCS. Due to this erratum, the processor may store an incorrect value into bits 11:0 of
this field. (The processor correctly stores the guest-physical address of the paging-
structure entry into the "guest-physical address" field in the VMCS.)
Implication:
Software may not be easily able to determine the page offset of the original memory
access that caused the EPT violation. Intel has not observed this erratum to impact the
operation of any commercially available software.
Workaround:
Software requiring the page offset of the original memory access address can derive it
by simulating the effective address computation of the instruction that caused the EPT
violation.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ128.
IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report The
Highest Index Value Used For VMCS Encoding
Problem:
IA32_VMX_VMCS_ENUM MSR (48AH) bits 9:1 report the highest index value used for
any VMCS encoding. Due to this erratum, the value 21 is returned in bits 9:1 although
there is a VMCS field whose encoding uses the index value 23.
58
clock
modulation
or
if
the
duty
cycle
programmed
in
the
Specification Update
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