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Related Manuals for Quatech MPA-200
Summary of Contents for Quatech MPA-200
- Page 1 MPA-200/300 RS-422/485 SYNCHRONOUS ADAPTER CARD for ISA compatible machines INTERFACE CARDS FOR IBM PC/AT AND PS/2 User's Manual QUATECH, INC. TEL: (330) 655-9000 5675 Hudson Industrial Parkway FAX: (330) 655-9010 Hudson, Ohio 44236 http://www.quatech.com...
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Page 3: Warranty Information
Quatech Inc. warrants the to be free of defects for one (1) year from the date of purchase. Quatech Inc. will repair or replace any adapter that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from improper installation, operation, or general misuse voids all warranty rights. - Page 4 In no event will Quatech, Inc. be liable for damages of any kind, incidental or consequential, in regard to or arising out of the performance or form of the materials presented in this document or any software programs that might accompany this document.
- Page 5 TV reception. The user is cautioned that changes and modifications made to the equipment without the approval of the manufacturer could void the user's authority to operate this equipment. Quatech Inc., MPA-200/300 Manual...
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Page 6: Table Of Contents
......11.1 MPA-200 and EIA-530 Compatibility .... - Page 7 Quatech Inc., MPA-200/300 Manual...
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Page 8: Introduction
MPA-200 and MPA-300 will be collectively referred to as the MPA-200 except where noted. The ports of the MPA-200 occupy an 8 byte block of I/O address space. The base address of this block may be located anywhere within the available I/O address space of the system. - Page 9 Figure 1 MPA-200 board drawing Quatech, Inc. MPA-200 Quatech Inc., MPA-200/300 Manual...
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Page 10: Hardware Installation
DIRECT MEMORY ACCESS on page 18 for detailed information on how to set the address, IRQ, and DMA levels. 2. Turn off the power of the computer system in which the MPA-200 is to be installed. 3. Remove the system cover according to the instructions provided by the computer manufacturer. -
Page 11: Scc General Information
3 SCC GENERAL INFORMATION The Serial Communications Controller (SCC) is a dual channel, multi-protocol data communications peripheral. The MPA-200 provides a single channel for communications, however, to provide full DMA capabilities, both channels of the SCC can be utilized. The SCC can be software configured to satisfy a wide variety of serial communications applications. -
Page 12: Accessing The Registers
Table 3 SCC write register descrip- tion describes the write registers for each channel. The MPA-200 has been designed to assure that all back to back access timing requirements of the SCC are met without the need for any software timing control. - Page 13 These clocks can be programmed in WR11 to come from the RTXC pin, the TRXC pin, the output of the BRG, or the transmit output of the DPLL. The MPA-200 uses the TRXC pin for its transmit Quatech Inc., MPA-200/300 Manual...
- Page 14 Clock mode and source control WR12 Lower byte of baud rate time constant WR13 Lower byte of baud rate time constant WR14 Miscellaneous control bits: baud rate generator, DPLL control, auto echo WR15 External/Status interrupt control Quatech Inc., MPA-200/300 Manual...
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Page 15: Baud Rate Generator Programming
WR13 (most significant byte). The equation relating the baud rate to the time constant is given below while Table 4 shows the time constants associated with a number of popular baud rates when using the standard MPA-200 9.8304 MHz clock. -
Page 16: Scc Data Encoding Methods
WR14. They are local loopback and auto echo. For further information on these subjects or any others involving the SCC, contact the manufacturer of the SCC being used for a complete technical manual. Quatech Inc., MPA-200/300 Manual... -
Page 17: Jumper Block Configurations
IRQ2 - IRQ7 reside on J5, while interrupt levels IRQ10 - IRQ12 and IRQ14 - IRQ15 reside on J6. Table 6, and Table 7 summarize the jumper block selections for J5 and J6. The IRQ levels are also marked on the MPA-200 silk- screen for easy identification. -
Page 18: J10 - Transmit Dma Channel Selection
J10 selects the DMA channel to be used for transmit DMA. Three channels (1 - 3) are available on the MPA-200 for DMA. When selecting a DMA channel, both the DMA acknowledge (DACK) and the DMA request (DRQ) for the appropriate channel need to be selected. -
Page 19: J11 - Receive Dma Channel Selection
Similarly, by selecting pins 4 & 5, the receivers on the MPA-200 will always be enabled. If pins 5 & 6 are selected, the receivers are controlled by bit D1 of the communications register. Table 10 summarizes the jumper block selections for J7. -
Page 20: J8 - Synca To Rlen Control
SYNCA pin when the SCC is in external SYNC mode. Note: the RLEN output is still effected when used to control the SYNCA pin. Table 11 Jumper J8 Selections Function Jumper J8 SYNCA RLEN Quatech Inc., MPA-200/300 Manual... -
Page 21: Addressing
300H, then the MPA-200 will occupy address locations 300H-307H. The base address of the MPA-200 may be set to any of the first 64 Kbytes (0 - FFFFH) of available I/O address space through the settings of dip switches SW1 and SW2. - Page 22 The first four bytes, Base+0 through Base+3, of address space on the MPA-200 contain the internal registers of the SCC. The next two locations Base+4 and Base+5 contain the communications register and the configuration register. The last two address port locations are reserved for future use. The entire address range of the MPA-200 is shown in Table 12.
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Page 23: Interrupts
- 15. The interrupt level is selected through jumper blocks J5 and J6 ( see JUMPER BLOCK CONFIGURATIONS on page 11). The interrupt source is selected by bits D4 and D5 of the configuration register. The MPA-200 has three interrupt sources: interrupt on terminal count, interrupt on test mode, and interrupt from the SCC. -
Page 24: Direct Memory Access
D1 on the configuration register. After programming the SCC for DMA, one should enable the DMA on the MPA-200 by setting bit D3 of the configuration register. Then, the DMA on the SCC should be enabled, and finally the DMA controller should be enabled. - Page 25 W/REQB pin of channel B for DMA request on receive. This is done by clearing bit D0 and setting bit D1 of the configuration register. Figure 3 shows a block diagram of the DMA circuitry on the MPA-200. When using the channel A DTR/REQ pin for transmit DMA the SCC must be programmed so that the request release timing of this pin is identical to the WAIT/REQ timing.
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Page 26: Using Terminal Count To Generate An Interrupt
W/REQB Using Terminal Count to Generate an Interrupt The MPA-200 allows the option of generating an interrupt whenever the Terminal Count (TC) signal is asserted. Terminal Count is an indicator generated by the system’s DMA controller, which signals that the number of transfers programed into the DMA controller’s transfer register have occurred. -
Page 27: Configuration Register
8 CONFIGURATION REGISTER The MPA-200 is equipped with an onboard register used for configuring informa- tion such as DMA enables, DMA sources, interrupt enables, and interrupt sources. Below is a detailed description of the configuration register. The address of this register is Base+5. - Page 28 If both D0 and D1 are cleared (logic 0), then the transmit and receive DMA requests both come from the W/REQA pin of channel A on the SCC. Proper board function is not guaranteed under this condition. Quatech Inc., MPA-200/300 Manual...
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Page 29: Communications Register
Test mode bits pertain only to the DTE versions and can be ignored if using a MPA-200 configured DCE. The address of this register is Base+4. Table 14 and the descriptions that follow detail the communications register. - Page 30 D1 -RECEIVER ENABLE: If J7 is configured to allow the Communications Register to control the MPA-200’s receivers (see Table 10 on page 14) then when D1 is set (logic 1) the receivers are enabled and when D1 is cleared (logic 0) the receivers are disabled.
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Page 31: Dte / Dce Configuration
Both the DTE and DCE configurations allow the user to enable and disable the driver circuitry on the MPA-200 through the settings of jumper block J7. See the chapter JUMPER BLOCK CONFIGURATIONS on page 11 for further informa- tion on the configuration of this jumper block. They both also have the ability to receive data and receive clock (RCLK) on channel B of the SCC. -
Page 32: Dte Configuration
RRCLK or can be generated on the TRxCB pin of the SCC, depend- ing on RCKEN ( D3 of the communications register). The DTE can not transmit its RCLK. Figure 4 illustrates the clock circuitry of the MPA-200 for it's DTE configuration. -
Page 33: Dce Configuration
10.2 DCE Configuration On the MPA-200, the difference between the DTE and DCE signals is that, with the exception of a few control signals, the pins used for signal transmission on the DTE are used for signal reception on the DCE and vice versa. For example, pin 2 of the DCE connector is received data, yet the corresponding DTE signal is the transmitted data. - Page 34 The Test Mode (TM) signal is always in the OFF condition and cannot be changed by the user. The Local Loopback (LL) and Remote Loopback (RL) test signals are not implemented on the DCE. Table 16 summarizes the signals on the DCE. Quatech Inc., MPA-200/300 Manual...
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Page 35: External Connections
11 EXTERNAL CONNECTIONS When configured as a DTE, the MPA-200 uses a D-25 short body male connector (labeled CN2). When configured as a DCE, the MPA-200 uses a D-25 long body female connector (labeled CN1). Table 15 and Table 16 describe the pin out definitions for both connectors and Figure 6 and Figure 7 illustrate the pin-outs for each of the connectors.. - Page 36 DTR/REQB -TTCLK TRXCA DTR/REQB -RRCLK RTXC -RTCLK TRXCB -RTS RTSA -RXD RXDA +RTCLK TRXCB -TXD TXDA +TTCLK TRXCA No Connect -CTS CTSA +DSR DCDA No Connect -DTR DTR/REQA -DSR DCDA +RRCLK TRXC TEST MODE Always Zero Quatech Inc., MPA-200/300 Manual...
- Page 37 Figure 4 MPA-200 DTE Output Connector -CTS 13 25 TEST MODE -RTCLK 12 24 +TTCLK -TTCLK 11 23 -DTR -CD 10 22 -DSR -RRCLK 9 21 RLBK +CD 8 20 +DTR DGND 7 19 -RTS +DSR 6 18 LLBK +CTS 5...
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Page 38: Mpa-200 And Eia-530 Compatibility
11.1 MPA-200 and EIA-530 Compatibility If the MPA-200 is to be connected with an EIA-530 device, it may be necessary to swap the +/- conductors on the TXD and RXD signals. 11.2 Null-Modem Cables The MPA-200 does not use a standard asynchronous PC serial port connector pin out. -
Page 39: Definition Of Interface Signals
Ÿ CONNECTOR NOTATION: +TTCLK,-TTCLK Ÿ DIRECTION: To DCE This signal, generated by the DTE, provides the DCE with element timing information pertaining to the data transmitted by the DTE. The DCE can use this information for its received data. Quatech Inc., MPA-200/300 Manual... - Page 40 Ÿ CONNECTOR NOTATION: +CD,-CD Ÿ DIRECTION: From DCE This signal indicates to the DTE whether the DCE is conditioned to receive data from the communication channel, but does not indicate the relative quality of the data signals being received. Quatech Inc., MPA-200/300 Manual...
- Page 41 Note: The local loopback and remote loopback signals are optional and are omitted from the DCE configuration of the MPA-200. Since testing will never occur for this configuration, the test mode signal will always be in the OFF condition for the DCE. These three test signals follow the EIA-423-A standard while the remaining signals follow the EIA-422-A standard.
- Page 42 Ÿ DIRECTION: From DCE This signal indicates to the DTE that the DCE is in a test condition. The DCE generates this signal when it has received a local loopback or remote loopback signal from the DTE. Quatech Inc., MPA-200/300 Manual...
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Page 43: Specifications
75176 or compatible EIA485: 75175 or compatible Transceivers: EIA-422: 75176 or compatible EIA-485: 75176 or compatible I/O Address range: 0000H - FFFFH Interrupt levels: IRQ 2-7, 10-12, 14-15 Power requirements: (mA) (mA) Supply Voltage (Volts) 1248 1402 Quatech Inc., MPA-200/300 Manual... - Page 44 MPA-200/300 User's Manual Version 5.31 March 2004 Part No. 940-0038-531...