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Qua Tech Inc. warrants the
be free of defects for
purchase.
Qua Tech Inc. will repair or replace any board
t h a t f a i l s t o p e r f o r m u n d e r n o r m a l o p e r a t i n g c o n d i t i o n s
a n d i n a c c o r d a n c e w i t h t h e p r o c e d u r e s o u t l i n e d i n t h i s
d o c u m e n t d u r i n g t h e w a r r a n t y p e r i o d .
results from improper installation, operation, or general
misuse voids all warranty rights.
A l t h o u g h e v e r y a t t e m p t h a s b e e n m a d e t o g u a r a n t e e
t h e a c c u r a c y o f t h i s m a n u a l , Q u a T e c h I n c . a s s u m e s n o
l i a b i l i t y
f o r
d o c u m e n t .
Q u a T e c h I n c . r e s e r v e s t h e r i g h t t o e d i t o r
append to this document at any time without notice.
Please complete the following information and retain
f o r y o u r r e c o r d s .
requesting warranty service.
DATE OF PURCHASE:
MODEL NUMBER:
PRODUCT DESCRIPTION:
SERIAL NUMBER:
IBM PC T M , P C / X T T M , a n d P C / A T T M a r e t r a d e m a r k s o f
International Business Machines.
W A R R A N T Y I N F O R M A T I O N
o n e ( 1 ) y e a r
d a m a g e s
r e s u l t i n g
H a v e t h i s i n f o r m a t i o n a v a i l a b l e w h e n
Q S - 2 0 0 M / Q S - 3 0 0 M
F O U R
C H A N N E L
A S Y N C .
i
Q S - 2 0 0 M / Q S - 3 0 0 M
from the date of
A n y d a m a g e t h a t
f r o m
e r r o r s
R S - 4 2 2 / R S - 4 8 5
C O M M U N I C A T I O N S
to
i n
t h i s
A D A P T E R
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Table of Contents
Related Manuals for Quatech QS-300M
Summary of Contents for Quatech QS-300M
- Page 1 W A R R A N T Y I N F O R M A T I O N Qua Tech Inc. warrants the Q S - 2 0 0 M / Q S - 3 0 0 M be free of defects for o n e ( 1 ) y e a r from the date of purchase.
-
Page 2: Table Of Contents
TABLE OF CONTENTS WARRANTY INFORMATION ... . LIST OF FIGURES ... . . INTRODUCTION ....BOARD DESCRIPTION . - Page 3 INTRODUCTION LIST OF FIGURES Figure QS-200M/QS-300M board layout ..Figure 16450/16550 internal registers ..Figure Interrupt enable register ..Figure Interrupt identification register Figure Interrupt source identification . . .
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Page 4: Introduction
B O A R D D E S C R I P T I O N A component diagram of the QS-200M/QS-300M is shown f i g u r e T h e b a s e... -
Page 5: Figure
BOARD DESCRIPTION Figure 1. QS-200M/QS-300M board layout. -
Page 6: Internal Registers
FUNCTIONAL DESCRIPTION D e s i g n e d t o b e c o m p a t i b l e w i t h t h e 1 6 4 5 0 , t h e 1 6 5 5 0 A C E e n t e r s c h a r a c t e r m o d e o n r e s e t a n d i n t h i s m o d e a p p e a r s... -
Page 7: Interrupt Enable Register
FUNCTIONAL DESCRIPTION I I I A . I N T E R R U P T E N A B L E R E G I S T E R +-------+ +-------+ +-------+ +-------+ +-------+ | EDSSI |----- MODEM status +-------+ | ELSI |----- Receiver line status... -
Page 8: Interrupt Identification Register
FUNCTIONAL DESCRIPTION I I I B . I N T E R R U P T I D E N T I F I C A T I O N R E G I S T E R +------+ | FFE |----- FIFO enable (FIFO only) +------+ +------+... -
Page 9: Figure
FUNCTIONAL DESCRIPTION +---------------------+----------+---------------------+ | IID2 IID1 IID0 | Priority | Interrupt Type +---------------------+----------+---------------------+ | None | Highest | Receiver Line Status| | Second | Received Data Ready | | Second | Character Timeout (FIFO only) | Third | Transmitter Holding | Register Empty | Fourth | MODEM Status... -
Page 10: Fifo Control Register
0 t o m o d e 1 f o r D M A t r a n s f e r s . ( D M A m o d e not supported on QS-200M/QS-300M.) -
Page 11: Line Control Register
FUNCTIONAL DESCRIPTION RRST - Receive FIFO Reset: W h e n s e t ( l o g i c 1 ) , a l l b y t e s i n t h e r e c e i v e r FIFO are cleared and the counter is reset. -
Page 12: Figure
UNCTIONAL DESCRIPTION STKP - Stick Parity: Forces parity to logic 1 or logic 0 if parity is enabled. See EPS, PEN, and figure 9. - Even Parity Select: Selects even or odd parity if parity is enabled. See STKP, PEN, and figure 9. - Parity Enable: E n a b l e s p a r i t y o n t r a n s m i s s i o n a n d v e r i f i c a t i o n on reception. -
Page 13: Modem Control Register
FUNCTIONAL DESCRIPTION I I I E . M O D E M C O N T R O L R E G I S T E R +------+ +------+ +------+ +------+ | LOOP |----- Loopback enable +------+ | OUT2 |----- Output 2 +------+ | OUT1 |----- Output 1 +------+... -
Page 14: Line Status Register
FUNCTIONAL DESCRIPTION I I I F . L I N E S T A T U S R E G I S T E R +------+ | FFRX |----- Error in FIFO RCVR (FIFO only) +------+ | TEMT |----- Transmitter empty +------+ | THRE |----- Transmitter holding register empty +------+... -
Page 15: Fifo Mode
FUNCTIONAL DESCRIPTION Bits BI, FE, PE, and OE are the sources of receiver l i n e s t a t u s i n t e r r u p t s . T h e b i t s a r e r e s e t I n F I F O m o d e * ,... -
Page 16: Modem Status Register
FUNCTIONAL DESCRIPTION I I I G . M O D E M S T A T U S R E G I S T E R +------+ | DCD |----- Data carrier detect +------+ |----- Ring indicator +------+ | DSR |----- Data set ready +------+ | CTS... -
Page 17: Scratchpad Register
FUNCTIONAL DESCRIPTION I I I H . S C R A T C H P A D R E G I S T E R This register is not used by the 16450/16550. may be used by the programmer for data storage. O P E R A T I O N * F I F O I N T E R R U P T... -
Page 18: Figure
BAUD RATE SELECTION +-----------+ +-----------+ _+ _ _--_ _+ _ _--_ +-----------+ +-----------+ (a) ÷1 input clock (b) ÷2 input clock +-----------+ +-----------+ _--_ _+ _--_ _--_ _+ _--_ +-----------+ +-----------+ (c) ÷5 input clock (d) ÷10 input clock F i g u r e 1 4 . I n p u t C l o c k F r e q u e n c y O p t i o n s . -
Page 19: Addressing
A s w i t c h i n t h e " O F F " p o s i t i o n f o r c e s t h e c o r r e s p o n d i n g address be a logic selection. Some example switch settings for the QS-200M/QS-300M are shown in figures 16 and 17. The base address of each channel is incremented by a f a c t o r f r o m... -
Page 20: Figure
ADDRESSING BASE ADDRESS = 0300H On +-++-++-++-+ +-++-++-++-+ +-++-++-+ |_||_||_||_| |_||_|| || | |_||_||_| | || || || | | || ||_||_| | || || | Off +-++-++-++-+ +-++-++-++-+ +-++-++-+ = 0300H BASE ADDRESS = 06A0H On +-++-++-++-+ +-++-++-++-+ +-++-++-+ |_||_||_||_| |_|| || ||_| | ||_|| |... -
Page 21: Interrupts
INTERRUPTS VII. I N T E R R U P T S T h e Q S - 2 0 0 M / Q S - 3 0 0 M i s c a p a b l e o f s u p p o r t i n g s i x i n t e r r u p t l e v e l s , I R Q 2 - 7 . -
Page 22: Interrupt Status Register
Scratchpad/Interrupt Status select. +------+ +------+ +------+ +------+ +------+ | IP4 +------+ | IP3 +------+ | IP2 +------+ | IP1 +------+ Figure 20. Interrupt Status register for the QS-200M/QS-300M. IPx set (logic 1), indicates an interrupt is pending on the associated channel. -
Page 23: Output Configurations
Q S - 200M/QS-300M, the computer and the peripheral equipment. -
Page 24: External Connections
EXTERNAL CONNECTIONS E X T E R N A L C O N N E C T I O N S Figure 22. Output Connectors. -
Page 25: Installation
INSTALLATION I N S T A L L A T I O N Set base address switches and interrupt and output configuration jumpers on the card. Turn unit off. Remove system cover as instructed in the computer reference guide. Insert card into a vacant slot following the guidelines for installation.