1. Manuals
  2. Brands
  3. Quatech Manuals
  4. Computer Hardware
  5. MPA-100
  6. User manual

Quatech MPA-100 User Manual

Rs-232 synchronous adapter card
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
INTERFACE CARDS FOR IBM PC/AT AND PS/2
QUATECH, INC.
5675 Hudson Industrial Parkway
Hudson, Ohio 44236
MPA-100
RS-232 SYNCHRONOUS
ADAPTER CARD
User's Manual
TEL: (330) 665-9000
FAX: (330) 665-9010
http://www.quatech.com

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the MPA-100 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Quatech MPA-100

Summary of Contents for Quatech MPA-100

  • Page 1 MPA-100 RS-232 SYNCHRONOUS ADAPTER CARD User's Manual INTERFACE CARDS FOR IBM PC/AT AND PS/2 QUATECH, INC. TEL: (330) 665-9000 5675 Hudson Industrial Parkway FAX: (330) 665-9010 Hudson, Ohio 44236 http://www.quatech.com...

  • Page 3: Warranty Information

    No representation is made regarding the suitability of this product for any particular purpose. Quatech Inc. reserves the right to edit or append to this document or the product(s) to which it refers at any time and without notice.
  • Page 4 Quatech, Inc. Likewise, any software programs that might accompany this document can be used only in accordance with any license agreement(s) between the purchaser and Quatech, Inc. Quatech, Inc. reserves the right to change this documentation or the product to which it refers at any time and without notice.

  • Page 5: Table Of Contents

    ..........13-1 MPA-100 User's Manual...
  • Page 6 MPA-100 User's Manual...

  • Page 7: Introduction

    Figure 1 MPA-100 Board Layout Quatech, Inc. MPA-100 The MPA-100 occupies an 8 byte block of I/O address space which may be located anywhere within the available I/O address space in the system. Communication on the MPA-100 is controlled by a serial communications controller, hereafter referred to as the SCC (U17).
  • Page 8 MPA-100 User's Manual...

  • Page 9: Hardware Installation

    7 for detailed information on how to set the address, IRQ, and DMA levels. 2. Turn off the power of the computer system in which the MPA-100 is to be installed. 3. Remove the system cover according to the instructions provided by the computer manufacturer.
  • Page 10 MPA-100 User's Manual...

  • Page 11: Addressing

    300H, then the MPA-100 will occupy address locations 300H-307H. The base address of the MPA-100 may be set to any of the first 64 Kbytes (0 - FFFFH) of available I/O address space through the settings of dip switches SW1 and SW2. SW1 allows the user to select the higher address signals A15 - A8.

  • Page 12: Configuration Register

    SCC. The next two locations Base+4 and Base+5 contain the Communications Register and the Configuration Register. The last two address port locations are reserved for future use. The entire address range of the MPA-100 is shown in Table 2. Table 2 MPA-100 Address Assignments...

  • Page 13: Interrupts

    The MPA-100 supports eleven interrupt levels: IRQ2 -7, IRQ10 - 12, and IRQ14 - 15, and selects which interrupt level is in use through jumper packs J5 and J6. The MPA-100 has three interrupt sources: interrupt on terminal count, interrupt on test mode, and interrupt from the SCC.

  • Page 14: Using Terminal Count To Generate Interrupts

    Using Terminal Count to Generate Interrupts The MPA-100 allows the option of generating an interrupt whenever the Terminal Count (TC) signal is asserted. Terminal Count is an indicator generated by the system’s DMA controller, which signals that the number of transfers programed into the DMA controller’s transfer register have occurred.

  • Page 15: Jumper Configurations

    J4 is a three pin jumper which determines the configuration for the interrupts. By selecting pins 1 & 2, the user has the ability to share interrupts with other Quatech adapter cards. The MPA-100 will drive the interrupt onto the bus only when an interrupt occurs. Otherwise, the output is high impedance.

  • Page 16: Interrupt Level Selection - J5 & J6

    Interrupt Level Selection - J5 & J6 Jumper blocks J5 and J6 select the interrupt level that the MPA-100 utilizes. Interrupt levels IRQ2 - IRQ7 reside on J5, while interrupt levels IRQ10 - IRQ12 and IRQ14 - IRQ15 reside on J6. Table 5 and Table 6 summarize the jumper block selections for J5 and J6. The IRQ levels are also marked on the MPA-100 silkscreen for easy identification.

  • Page 17: Transmit Dma Selection - J8

    J8 Selects the DMA channel to be used for Transmit DMA. Three channels (1 - 3) are available on the MPA-100 for DMA. When selecting a DMA channel, both the DMA acknowledge (DACK) and the DMA request (DRQ) for the appropriate channel need to be selected.
  • Page 18 SYNCA input to the SCC. If J7 is installed and the SCC is in external SYNC mode, setting the RLEN bit high will assert the SYNCA pin. Note: the RLEN output is still affected when used to control the SYNCA pin. Table 9 Jumper J7 Selections Function Jumper J1 SYNCA RLEN (Default) no connections MPA-100 User's Manual...

  • Page 19: Scc General Information

    6. SCC GENERAL INFORMATION The Serial Communications Controller (SCC) is a dual channel, multi-protocol data communications peripheral. The MPA-100 provides a single channel for communications, however, to provide full DMA capabilities with complete modem control line support, both channels of the SCC can be utilized. The SCC can be software configured to satisfy a wide variety of serial communications applications.

  • Page 20: Accessing The Registers

    The register set of the SCC includes 16 write registers and 9 read registers. These registers only occupy four address locations, which start at the MPA-100's physical base address that is configured via the on board switches. This and all other addresses are referenced from this base address in the form Base + Offset.
  • Page 21 The SCC incorporates additional circuitry supporting serial communications. This circuitry includes clocking options, baud rate generator (BRG), data encoding, and internal loopback. The SCC may be programmed to select one of several sources to provide the transmit MPA-100 User's Manual...
  • Page 22 Lower byte of baud rate time constant WR14 Miscellaneous control bits: baud rate generator, DPLL control, auto echo WR15 External/Status interrupt control For more information regarding the SCC registers please refer to the manufacturer's technical manual for the specific part being used. MPA-100 User's Manual...

  • Page 23: Baud Rate Generator Programming

    The equation relating the baud rate to the time constant is given below while Table 12 shows the time constants associated with a number of popular baud rates when using the standard MPA-100 9.8304 MHz clock. Clock_Frequency Baud_Const = 2&Baud_Rate&Clock_Mode...

  • Page 24: Scc Data Encoding Methods

    SCC contains two features for diagnostic purposes, controlled by bits in WR14. They are local loopback and auto echo. For further information on these subjects or any others involving the SCC contact the manufacturer of the SCC being used for a complete technical manual. MPA-100 User's Manual...

  • Page 25: Direct Memory Access

    B. The source is then determined by bit D1 on the Configuration Register. After programming the SCC for DMA, one should enable the DMA on the MPA-100 by setting bit D3 of the Configuration Register. Then, the DMA on the SCC should be enabled, and finally the DMA controller should be enabled.
  • Page 26 Therefore, bits D0 and D1 of the Configuration Register should never be cleared at the same time while bits D2 and D3 are both set. This situation may result in damage to the system. Figure 3 Block Diagram of DMA on MPA-100 W/REQA DMATRQ...

  • Page 27: Configuration Register

    8. CONFIGURATION REGISTER The MPA-100 is equipped with an onboard register used for configuring information such as DMA enables, DMA sources, interrupt enables, and interrupt sources. Below is a detailed description of the Configuration Register. The address of this register is Base+5. Table 13 details the bit definitions of the Configuration Register.
  • Page 28 DMA receive, obviously it cannot be used for both simultaneously. Therefore, bits D0 and D1 of the Configuration Register should never be cleared at the same time while bits D2 and D3 are both set. This situation may result in damage to the system. MPA-100 User's Manual...

  • Page 29: Communications Register

    Test mode bits pertain only to the DTE versions and can be ignored if using a DCE configured MPA-100. The address of this register is Base+4. Table 15 and the descriptions that follow detail the Communications Register.
  • Page 30 (logic 0), the DTE receives TCLK. Since a DCE can only transmit its TCLK, writing to this bit has no effect on a DCE. D1 RESERVED: This bit should always be programmed to 0. D0 RESERVED: This bit should always be programmed to 0. MPA-100 User's Manual...

  • Page 31: Dte/Dce Configuration

    10. DTE/DCE CONFIGURATION As indicated earlier in this manual, the MPA-100 can be configured as either a Data Terminal Equipment (DTE) or a Data Communications Equipment (DCE) device. The differences between these configurations include signal definitions, connector pin out, and clocking options.

  • Page 32: Dte Configuration

    TCLK on the same pin. RCKEN (bit D3 of the Communications Register) is always deasserted on a DTE configured MPA-100; therefore the DTE can receive its Receive Clock (RCLK) on the RTXC pins (pin 12 & 28) of the SCC but, as per the EIA-232D specification, the DTE cannot transmit its receive clock.

  • Page 33: Dce Configuration

    DCE configuration is the same one used for the DTE configuration the MPA-100 does not have a true DCE implementation. However, the pin out is correct for a one to one wired connection with a DTE.
  • Page 34 Receive Clock on the RTXC pins (pins 12 and 28) of the SCC. TCKEN (bit D2 of the Communications Register) is always asserted on a DTE configured MPA-100; therefore the DCE can transmit its Transmit Clock (TCLK) from the TRXCA pin (pin 14) but, as per the EIA-232D specification, the DCE cannot receive its Transmit Clock.
  • Page 35 DCDA of SCC DTR/REQA pin of SCC DTR/REQB pin of SCC TxCLK TRXCA pin of SCC RxCLK RTXC/TRXCB pin of SCC Bit D5 of Comm. Reg Bit D4 of Comm Reg INTM or Bit D7 of Comm Reg MPA-100 User's Manual 10-5...
  • Page 36 MPA-100 User's Manual 10-6...

  • Page 37: External Connections

    The MPA-100 is designed to meet the RS-232 standard through a D-25 connector. The MPA-100 uses a D-25 short body male connector (labeled CN1) for both the DTE and DCE configurations. Jumper blocks J2, J11, and J12 configure the connector pin out. Table 18 and Table 19 display the pin out definitions for both configurations while Figure 6 and Figure 7 illustrate the pin-outs for each of the configurations.
  • Page 38 RXCLK (DTE) TXCLK (DCE) TRXCA on SCC RXCLK (DCE) RTXC pins on SCC D5 of COMM REG DCDB on SCC D4 of COMM REG TXCLK (DTE) RTXC pins on SCC TEST MODE D7 of COMM REG MPA-100 User's Manual 11-2...
  • Page 39 Figure 6 MPA-100 DTE Output Connector Configuration N/C 13 25 Test Mode (Output) N/C 12 24 TxCLK (DTE) RxCLK (DTE) 11 23 N/C N/C 10 22 N/C N/C 9 21 RLBK (Output) CD 8 20 DTR DGND 7 19 N/C...
  • Page 40 MPA-100 User's Manual 11-4...

  • Page 41: Definition Of Interface Signals

    Ÿ CONNECTOR NOTATION:TXCLK (DCE) Ÿ DIRECTION: From DCE This signal, generated by the DCE, provides the DTE with element timing information pertaining to the data transmitted to the DCE. The DCE can use this information for its received data. MPA-100 User's Manual 12-1...
  • Page 42 CIRCUIT LL - Local Loopback Ÿ CONNECTOR NOTATION: LLBK Ÿ DIRECTION: To DCE This signal provides a means whereby a DTE may check the functioning of the DTE/DCE interface and the transmit and receive sections of the local DCE. MPA-100 User's Manual 12-2...
  • Page 43 Ÿ DIRECTION: From DCE This signal indicates to the DTE that the DCE is in a test condition. The DCE generates this signal when it has received a local loopback or remote loopback signal from the DTE. MPA-100 User's Manual 12-3...
  • Page 44 MPA-100 User's Manual 12-4...

  • Page 45: Specifications

    I/O Address range: 0000H - FFFFH Interrupt levels: IRQ 2-7, 10-12, 14-15 DMA levels: DMA Channel 1, 2, and 3 on transmit and receive. Physical Dimensions: 4.2” x 7.65” Power requirements: (mA) (mA) Supply Voltage (Volts) 1248 1402 MPA-100 User's Manual 13-1...
  • Page 46 MPA-100 User's Manual Version 4.12 March 2004 Part No. 940-0037-412 MPA-100 User's Manual 13-2...

Table of Contents