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WARRANTY INFORMATION Q u a T e c h I n c . w a r r a n t s t h e D S - 1 0 0 0 t o f r e e defects for o n e ( 1 ) y e a r from the date of purchase.
C O M M I S S I O N S T A T E M E N T +-----------------------------------------------+ The Qua Tech DS-1000 is certified to comply with Class B limits, Part 15 of FCC Rules. FCC ID: F4A4LUDS1000...
I I I A . I N T E R R U P T E N A B L E R E G I S T E R +-------+ +-------+ +-------+ +-------+ +-------+ | EDSSI |----- MODEM status +-------+ | ELSI |----- Receiver line status +-------+ | ETBEI |----- Transmitter holding register empty...
I I I B . I N T E R R U P T I D E N T I F I C A T I O N R E G I S T E R +------+ | FFE |----- FIFO enable (FIFO only) +------+ +------+ +------+...
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I I I B . I N T E R R U P T I D E N T I F I C A T I O N R E G I S T E R (continued) +---------------------+----------+----------------------+ | IID2 IID1 IID0 | Priority | Interrupt Type +---------------------+----------+----------------------+...
DMAM - DMA Mode Select: When set (logic 1), RxRDY and TxRDY change from mode 0 to mode 1. (DMA mode not supported on DS-1000) XRST - Transmit FIFO Reset: When set (logic 1), all bytes in the transmitter FIFO...
I I I D . L I N E C O N T R O L R E G I S T E R +------+ | DLAB |----- Divisor latch access bit +------+ | BKCN |----- Break control +------+ | STKP |----- Stick parity +------+ | EPS |----- Even parity select...
I I I D . L I N E C O N T R O L R E G I S T E R (continued) - Number of Stop Bits: S e t s t h e n u m b e r o f s t o p b i t s t r a n s m i t t e d . S e e W L S x and Figure 10.
Used for interrupt enable. See section VII. OUT1 - Output 1: Controls the OUT1 output, pin 34, as described above. Unused on DS-1000. - Request To Send: Controls the RTS output, pin 32, as described above. - Data Terminal Ready:...
I I I F . L I N E S T A T U S R E G I S T E R +------+ | FFRX |----- Error in FIFO RCVR (FIFO only) +------+ | TEMT |----- Transmitter empty +------+ | THRE |----- Transmitter holding register empty +------+ |----- Break interrupt...
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I I I F . L I N E S T A T U S R E G I S T E R (continued) Bits BI, FE, PE, and OE are the sources of receiver line status interrupts. The bits a r e r e s e t r e a d i n g...
I I I G . M O D E M S T A T U S R E G I S T E R +------+ | DCD |----- Data carrier detect +------+ |----- Ring indicator +------+ | DSR |----- Data set ready +------+ | CTS |----- Clear to send...
I I I H . S C R A T C H P A D R E G I S T E R This register is not used by the 16550. It may be used by the programmer for data storage. F I F O I N T E R R U P T M O D E...
O U T P U T C O N F I G U R A T I O N S R S - 2 3 2 - C d e v i c e s a r e c l a s s i f i e d b y t h e i r f u n c t i o n a s e i t h e r D a t a T e r m i n a l E q u i p m e n t ( D T E ) o r D a t a C o m m u n i c a t i o n E q u i p m e n t ( D C E ) .
(b) Jumper connections (c) Jumper connections for DTE configuration. for DCE configuration. Figure 22. DS-1000 output configuration jumpers. Shown are jumpers for port 1. NOTE: Connections are referenced by port and pin number. e.g. P1.3 _ port 1 pin 3, P1.6 _...
S P E C I F I C A T I O N S Bus interface: IBM MicroChannel 16-bit bus Controllers: 2 - 16550 Asynchronous Communication Elements (ACEs) RS-232 interface: 2 - D-9 connectors (male) optional: 2 - D-25 connectors (male) available using adapter cables provided Transmit drivers: MC1488 or compatible...