Quatech DS-3000 User Manual

Dual channel rs-422 async communications adapter

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Q u a T e c h I n c . w a r r a n t s t h e
f r e e o f d e f e c t s f o r
purchase.
Qua Tech Inc. will repair or replace any board
t h a t f a i l s t o p e r f o r m u n d e r n o r m a l o p e r a t i n g c o n d i t i o n s
a n d i n a c c o r d a n c e w i t h t h e p r o c e d u r e s o u t l i n e d i n t h i s
d o c u m e n t d u r i n g t h e w a r r a n t y p e r i o d .
results from improper installation, operation, or general
misuse voids all warranty rights.
A l t h o u g h e v e r y a t t e m p t h a s b e e n m a d e t o g u a r a n t e e
t h e a c c u r a c y o f t h i s m a n u a l , Q u a T e c h I n c . a s s u m e s n o
l i a b i l i t y
f o r
d o c u m e n t .
Q u a T e c h I n c . r e s e r v e s t h e r i g h t t o e d i t o r
append to this document at any time without notice.
Please complete the following information and retain
f o r y o u r r e c o r d s .
requesting warranty service.
DATE OF PURCHASE:
MODEL NUMBER:
PRODUCT DESCRIPTION:
SERIAL NUMBER:
I B M P C / X T / A T T M , P S / 2 T M , a n d M i c r o C h a n n e l T M a r e t r a d e m a r k s
of International Business Machines.
WARRANTY INFORMATION
o n e ( 1 ) y e a r
d a m a g e s
r e s u l t i n g
H a v e t h i s i n f o r m a t i o n a v a i l a b l e w h e n
D S - 2 0 0 0
D U A L
C H A N N E L
C O M M U N I C A T I O N S
i
D S - 2 0 0 0
f r o m
t h e
A n y d a m a g e t h a t
f r o m
e r r o r s
R S - 4 2 2
A S Y N C .
A D A P T E R
t o
b e
d a t e
o f
i n
t h i s

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Summary of Contents for Quatech DS-3000

  • Page 1 WARRANTY INFORMATION Q u a T e c h I n c . w a r r a n t s t h e D S - 2 0 0 0 f r e e o f d e f e c t s f o r o n e ( 1 ) y e a r f r o m t h e...
  • Page 2: Table Of Contents

    TABLE OF CONTENTS WARRANTY INFORMATION ... . LIST OF FIGURES ... . . INTRODUCTION ....BOARD DESCRIPTION .
  • Page 3 LIST OF FIGURES Figure DS-2000 board layout ..Figure 16550 internal registers ..Figure Interrupt enable register ..Figure Interrupt identification register Figure Interrupt source identification .
  • Page 4: Introduction

    I N T R O D U C T I O N T h e D S - 2 0 0 0 i s a d u a l c h a n n e l a s y n c h r o n o u s s e r i a l c o m m u n i c a t i o n a d a p t e r w h i c h...
  • Page 5: Figure

    F U N C T I O N A L D E S C R I P T I O N F i g u r e D S - 2 0 0 0 b o a r d l a y o u t .
  • Page 6: 16550 Functional Description

    F U N C T I O N A L D E S C R I P T I O N III. 1 6 5 5 0 F U N C T I O N A L D E S C R I P T I O N T h e 1 6 5 5 0 u p g r a d e...
  • Page 7: Interrupt Enable Register

    F U N C T I O N A L D E S C R I P T I O N A . I N T E R R U P T E N A B L E R E G I S T E R +-------+ +-------+ +-------+...
  • Page 8: Interrupt Identification Register

    F U N C T I O N A L D E S C R I P T I O N B . I N T E R R U P T I D E N T I F I C A T I O N R E G I S T E R +------+ | FFE...
  • Page 9: Figure

    F U N C T I O N A L D E S C R I P T I O N +-------------------+----------+----------------------+ | IID2 IID1 IID0 IP | Priority | Interrupt Type +-------------------+----------+----------------------+ | None 0 | Highest | Receiver Line Status | 0 | Second | Received Data Ready 0 | Second...
  • Page 10: Fifo Control Register

    F U N C T I O N A L D E S C R I P T I O N C . F I F O C O N T R O L R E G I S T E R +------+ | RXT1 |--+ +------+...
  • Page 11: Line Control Register

    F U N C T I O N A L D E S C R I P T I O N RRST - Receive FIFO Reset: W h e n s e t ( l o g i c 1 ) , a l l b y t e s i n t h e r e c e i v e r F I F O a r e c l e a r e d a n d t h e c o u n t e r i s r e s e t .
  • Page 12: Figure 10. Word Length And Stop Bit Options

    F U N C T I O N A L D E S C R I P T I O N STKP - Stick Parity: Forces parity to logic 1 or logic 0 if parity is enabled. See EPS, PEN, and figure 9. - Even Parity Select: S e l e c t s e v e n o r o d d p a r i t y i f p a r i t y i s e n a b l e d .
  • Page 13: Modem Control Register

    F U N C T I O N A L D E S C R I P T I O N E . M O D E M C O N T R O L R E G I S T E R +------+ +------+ +------+...
  • Page 14: Line Status Register

    F U N C T I O N A L D E S C R I P T I O N F . L I N E S T A T U S R E G I S T E R +------+ | FFRX |----- Error in FIFO RCVR (FIFO only) +------+...
  • Page 15 F U N C T I O N A L D E S C R I P T I O N B i t s B I , F E , P E , a n d O E a r e t h e s o u r c e s o f r e c e i v e r line status interrupts.
  • Page 16: Modem Status Register

    F U N C T I O N A L D E S C R I P T I O N G . M O D E M S T A T U S R E G I S T E R +------+ | DCD |----- Data carrier detect...
  • Page 17: Scratchpad Register

    F U N C T I O N A L D E S C R I P T I O N H . S C R A T C H P A D R E G I S T E R This register is not used by the 16550.
  • Page 18: Figure 14. Input Clock Frequency Options

    A U D R A T E S E L E C T I O N +-----------+ +-----------+ o+ o o--o o+ o o--o +-----------+ +-----------+ (a) ÷1 input clock (b) ÷2 input clock +-----------+ +-----------+ o--o o+ o--o o--o o+ o--o +-----------+ +-----------+...
  • Page 19: Addressing

    A D D R E S S I N G A D D R E S S I N G Each channel of the DS-2000 uses 8 consecutive I/O a d d r e s s l o c a t i o n s . T h e b a s e a d d r e s s e s a r e i n d e p e n d e n t but must begin on an even 8-byte boundary (xxx0H - xxx7H...
  • Page 20: Figure 16. Pos Implementation

    P R O G R A M M A B L E O P T I O N S E L E C T The remaining POS registers are used for address and interrupt selections. These registers are programmed by t h e u s e r t h r o u g h t h e I B M i n s t a l l a t i o n u t i l i t y s u p p l i e d with the PS/2.
  • Page 21: Figure 17. Base Address Locations

    P R O G R A M M A B L E O P T I O N S E L E C T +-------------------------+-------------------+ | ADSx3 ADSx2 ADSx1 ADSx0 | Base address +-------------------------+-------------------+ 3F8H (Serial 1) | 2F8H (Serial 2) | | 3220H (Serial 3) | | 3228H...
  • Page 22: Output Configurations

    O U T P U T C O N F I G U R A T I O N S O U T P U T C O N F I G U R A T I O N S Two sets of jumpers are implemented on the DS-2000 to control the auxiliary driver/receiver set.
  • Page 23 O U T P U T C O N F I G U R A T I O N S The other function of J2 and J3 is to configure the communication channel in half or full duplex mode. Half d u p l e x o p e r a t i o n i s a c h i e v e d b y c o n n e c t i n g p i n s 4 a n d 8 t h e j u m p e r...
  • Page 24: Figure 19. Output Control Block Diagram

    O U T P U T C O N F I G U R A T I O N S +-----------+ RI +-+ +------+ DCD +-+ +-+ inv. +-+ DSR +-+ | +------+ | (4,5,6 for channel 1, DTR +-+----+----o 1,2,3 for channel 2) +----------+ RCLK +-----------+...
  • Page 25: Figure 21. Auxiliary Channel Configuration (Handshake Mode)

    O U T P U T C O N F I G U R A T I O N S AUXIN ------+ +------ RCLK CTS --+ +-- DTR +-------------------+ o---o o---o +-------------------+ RTS --+ +-- driver enable AUXOUT ------+ +------ XCLK J2 _ Channel 1 J3 _ Channel 2 Figure 21.
  • Page 26: External Connections

    T E R N A L C O N N E C T I O N S E X T E R N A L C O N N E C T I O N S Connections to peripheral equipment are made via a f e m a l e D - 9 c o n n e c t o r .
  • Page 27: Installation

    I N S T A L L A T I O N I N S T A L L A T I O N M a k e s u r e t h e r e c o p y t h e original reference diskette available.

This manual is also suitable for:

Ds-2000

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