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Summary of Contents for Texas Instruments TMS320DM36x
- Page 1 TMS320DM36x DMSoC Analog to Digital Converter (ADC) Interface User's Guide Literature Number: SPRUFI7 March 2009...
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Page 2: Sprufi7 – March
SPRUFI7 – March 2009 Submit Documentation Feedback... -
Page 3: Table Of Contents
Contents ............................Preface ..........................Features ......................Block Diagram ..................Industry Compliance Statement ......................Peripheral Architecture ......................Clock Control ....................... Signal Descriptions ..................... Functional Operation ....................Reset Considerations ......................Interrupt Support ....................EDMA Event Support ..................... Power Management ....................Emulation Considerations ........................... - Page 4 www.ti.com List of Figures ...................... ADC IF Block Diagram ..................ADC Control (ADCTL) Register ..............Comparator Target Channel (CMPTGT) Register ..............Comparison A/D Lower Data (CMPLDAT) Register ..............Comparison A/D Upper Data (CMPUDAT) Register ..............Setup Divide Value for Start A/D (SETDIV) Register ...............
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Page 5: Preface
SPRUFH0— TMS320DM36x Digital Media System-on-Chip (DMSoC) 64-bit Timer Users Guide This document describes the operation of the software-programmable 64-bit timers in the TMS320DM36x Digital Media System-on-Chip (DMSoC). Timer 0, Timer 1, and Timer 3 are used as general-purpose (GP) timers and can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode;... - Page 6 TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFH7— TMS320DM36x Digital Media System-on-Chip (DMSoC) Real-Time Out (RTO) Controller Users Guide This document describes the Real Time Out (RTO) controller in the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFH8— TMS320DM36x Digital Media System-on-Chip (DMSoC) General-Purpose Input/Output (GPIO) Users Guide This document describes the general-purpose input/output (GPIO) peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC).
- Page 7 Interface (McBSP) User's Guide This document describes the operation of the multibuffered serial host port interface in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The primary audio modes that are supported by the McBSP are the AC97 and IIS modes. In addition to the primary audio modes, the McBSP supports general serial port receive and transmit operation.
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Page 8: Features
User's Guide SPRUFI7 – March 2009 Analog to Digital Converter (ADC) Interface DM36x has a 6-channel, 10-bit analog-to-digital converter (ADC) interface. The CPU communicates to the ADC interface using 32-bit-wide control registers accessible via the internal peripheral bus. Features The DM36x ADC interface has following features: Supports six configurable analog Input Supports for successive approximation type 10-bit, A-D converter Programmable sampling / conversion time (base clock is AUXCLK) -
Page 9: Industry Compliance Statement
Peripheral Architecture www.ti.com Industry Compliance Statement The ADC interface does not conform to any recognized industry standards. Peripheral Architecture Clock Control The ADC interface is driven by the auxiliary clock of the PLL controller. The frequency of the auxiliary clock is equal to the input reference clock of the PLL controller, and therefore is not affected by the multiplier and divider values of the PLL controller. -
Page 10: Reset Considerations
Peripheral Architecture www.ti.com 2.3.2 Free-Run Mode Operation In free-run mode operation, the ADC interface performs A/D conversion continuously without stopping. For free-run mode operation, the ADC interface should first be configured for scan mode(SCNMD), and comparator mode (CMPMD) in ADC interface control register (ADCTL), along with other configuration options. -
Page 11: Edma Event Support
Registers www.ti.com EDMA Event Support The ADC interface module does not generate an EDMA event. Power Management The ADC interface can be placed in reduced-power modes to conserve power during periods of low activity. Power management of the ADC Interface is controlled by the power and sleep controller (PSC) processor. -
Page 12: Adctl
Registers www.ti.com ADCTL The ADC control register (ADCTL) is shown in Figure 2 and described in Table Figure 2. ADC Control (ADCTL) Register Reserved Reserved Reserved BUSY CMPFLG CMPIEN CMPMD SCNFLG SCNIEN SCNMD START R/C-0 R/W-0 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write;... -
Page 13: Cmptgt
Registers www.ti.com CMPTGT The comparator target channel (CMPTGT) register is shown in Figure 3 and described in Table Figure 3. Comparator Target Channel (CMPTGT) Register Reserved CMPTGT R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3. -
Page 14: Cmpudat
Registers www.ti.com CMPUDAT The comparison A/D Upper data (CMPUDAT) register is shown in Figure 5 and described in Table Figure 5. Comparison A/D Upper Data (CMPUDAT) Register Reserved CMPUDAT R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5. -
Page 15: Ad0Dat
Registers www.ti.com Table 7. CHSEL setting for Channel selection CHSEL Selected Channel 000001b Channel 0 000010b Channel 1 000100b Channel 2 001000b Channel 3 010000b Channel 4 100000b Channel 5 Figure 7. Analog Input Channel Select (CHSEL) Register Reserved CHSEL R/W-0x3F LEGEND: R/W = Read/Write;... -
Page 16: Ad2Dat
Registers www.ti.com Table 10. A/D Conversion Data 1 (AD1DAT) Field Descriptions Field Value Description 31-10 Reserved Any writes to these bit(s) must always have a value of 0. AD1DAT A/D conversion data for channel 1 AD2DAT The A/D conversion data 2 (AD2DAT) register is shown in Figure 10 and described in Table... -
Page 17: Ad5Dat
Registers www.ti.com Table 13. A/D Conversion Data 4 (AD4DAT) Field Descriptions Field Value Description 31-10 Reserved Any writes to these bit(s) must always have a value of 0. AD4DAT A/D conversion data for channel 4 3.12 AD5DAT The A/D conversion data 5 (AD5DAT) register is shown in and described in . Figure 13. - Page 18 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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