Timing Logic - Fluke 5220A Instruction Manual

input is present. Under normal operating condition the reset command is high at U9-10
and low at U3-10.
When the 5220A is switched from remote to local operation the local/remote logic
triggers monostable U11-10 in the reset logic circuit. The result is a momentary positive-
going pulse at the Q output of U11-10. This in turn drives the complementary reset lines
of U9-10 and U3-10.
The overall result of a reset command, regardless of how it is initiated, is to set the output
commands of the A10 Logic to the states shown in Table 3-1. Essentially the unit is
commanded to standby operation with front panel inputs selected. Remote and Local
Lockout (LLO) commands are not affected by the reset command.
Table 3-1. Effect of Reset Command on A10 Logic and A9 Front Panel
Signal Name
Interface Operate Status
Operate LED
Standby LED
T1, T2, and T4
Relay 1
Relay 2
Front Panel Input LED
Rear Panel Input LED
Overcompliance LED
Overcurrent LED
Thermal Cutout LED
Interface Overload Status

3-15. Timing Logic

The timing logic controls the timing sequence used to switch the transconductance
amplifier between the standby and operate modes. It consists of a bi-directional shift
register U22, D-type flip-flops U17-1, and free running multivibrator U23. The
multivibrator runs at a frequency of 100 Hz (10 ms period) and serves as the clock for
both the flip-flop and the shift register. Flip-flop U17-1 responds to the Reset command
(reset input) and the standby/operate commands (D-input) to select the shift register's
control mode; i.e., shift left or shift right. The shift register's four outputs are sequenced
low in the shift-left mode and high in the shift-right mode. With all outputs low the
transconductance amplifier is set to standby. The amplifier is operational when all output
are high.
The shift-left mode is selected when flip-flop U17-1 drives the register's S0 input low and
its S1 input high. (This occurs as the result of a standby or reset command.) In this mode
the register sequentially propagates the low input at U22-7 through the register causing
its four outputs (QA, QB, QC, and QD) to be sequentially driven low. Since the register
shifts at the rate of the 100 Hz clock, the outputs are sequenced at intervals of 10 ms. At
the end of four clock pulses all four outputs are low (standby), and will remain low until
the register is commanded to shift right.
Logic State
Low
High
Low
Low
High
High
Low
High
High
High
High
Low
Theory of Operation
Circuit Analysis
Front Panel LED Status
None
OPER LED off
STDBY LED on
None
None
None
FRONT LED on
FRONT LED OFF
OVERCOMPLIANCE LED off
OVERCURRENT LED off
THERMAL CUTOFF LED off
None
3
3-13