Reset Circuit - Panasonic KX-F900 Service Manual

KX-F900
3-2, RESET CIRCUIT
The output from pin 3 of the Reset IC (IC9) resets the gate array (IC1), the modem (IC11), the gate array on the operating
board (10301), the Port IC (10151) on the analog board through the IC1.
(1) During to momentary power interruption, a positive reset pulse of 175 msec or more is generated and the system is reset
completely.
This is done to prevent partial resetting and system runaway during power fluctuation.
Timing Chart
+5
__ ,,_.8,_4. 3 It
i
i
: :about 175 ms jj
i
I
4.2 _ 4.3
: about 17._s_j}
(2) When pin 3 of the IO9 becomes low level, it will prohibit the RAM (IO3) from changing data.
The RAM (IC3) go into the backup mode, when it is backed up by the lithium battery.
Circuit Diagram
+5V
064
c00
IC9
101
R78
IC1
WDERR
lo__L
102
103
RESET (TO ANALOG BOARD,
OPERATION BOARD)
RESET (TO MODEM)
(3) The watch dog timer, built-in the gate array (IO1), is initialized about every 1.5 ms.
When the watch dog error occurs, pin 104 of the gate array (IC1) becomes low level.
The terminal of WDERR signal is connected to the reset line so, WDERR signal works as the reset signal.
(')
C
-I
O
"1o
rn
_>
--I
i
O
Z
-133-