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PCI Bridge/CPU
Cache Memory
ADAC Ultra2 S466 BIOS
Chapter 4 Features
ADAC Ultra2 S466 uses the Intel i960RP PCI bridge with
an embedded 80960JF RISC processor running at 33 MHz.
The RP bridge handles data transfers between the primary
(host) PCI bus, the secondary PCI bus, cache memory, and
the SCSI bus. The DMA controller supports chaining and
unaligned data transfers. The embedded 80960JF CPU
directs all controller functions, including command
processing, SCSI bus transfers, RAID processing, drive
rebuilding, cache management, and error recovery.
ADAC Ultra2 S466 cache memory resides in a memory
bank that uses 1 MB x 36, 4 MB x 36, 16 MB x 36, or 32
MB x 36 72-pin 60 or 70 ns Fast Page Mode or EDO
SIMMs. Possible configurations are 4, 8, 16, 32, 64, or 128
MB.
ADAC Ultra2 S466 supports write-through or write-back
caching, selectable for each logical drive. To improve
performance in sequential disk accesses, the ADAC Ultra2
S466 controller uses read-ahead caching by default. You
can disable read-ahead caching.
The BIOS resides on a 1 MB × 8 flash ROM for easy
upgrade. The ADAC Ultra2 S466 BIOS supports INT 13h
calls to boot DOS without special software or device
drivers. The ADAC Ultra2 S466 BIOS provides an
extensive setup utility that can be accessed by pressing
<Ctrl> <M> at BIOS initialization. ADAC BIOS Setup is
described in the ADAC Ultra2 S466 Configuration
Software Guide.
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