Fujitsu MB15E07SL User Manual page 9

Single serial input pll frequency synthesizer on-chip 2.5 ghz prescaler
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Programmable Counter
LSB
1
2
3
4
C
A
A
A
N
1
2
3
T
CNT
: Control bit
N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7
: Divide ratio setting bits for the swallow counter (0 to 127)
Note: Data input with MSB first.
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio (R)
R14
3
0
4
0
16383
1
Note : Divide ratio less than 3 is prohibited.
Table 3. Binary 11-bit Programmable Counter Data Setting
Divide ratio (N)
N11
3
0
4
0
2047
1
Note : Divide ratio less than 3 is prohibited.
Table 4. Binary 7-bit Swallow Counter Data Setting
Divide ratio (A)
0
1
127
Data Flow
5
6
7
8
9
A
A
A
A
N
4
5
6
7
1
R13
R12
R11
R10
0
0
0
0
0
0
0
0
1
1
1
1
N10
N9
N8
0
0
0
0
0
0
1
1
1
A7
A6
0
0
0
0
1
1
10
11
12
13
14
N
N
N
N
N
2
3
4
5
6
R9
R8
R7
R6
0
0
0
0
0
0
0
0
1
1
1
1
N7
N6
N5
0
0
0
0
0
0
1
1
1
A5
A4
0
0
0
0
1
1
MB15E07SL
MSB
15
16
17
18
19
N
N
N
N
N
7
8
9
10
11
[Table 1]
[Table 3]
[Table 4]
R5
R4
R3
R2
0
0
0
1
0
0
1
0
1
1
1
1
N4
N3
N2
N1
0
0
1
0
1
0
1
1
1
A3
A2
A1
0
0
0
0
0
1
1
1
1
R1
1
0
1
1
0
1
9

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