Fujitsu MB15E07SL User Manual page 8

Single serial input pll frequency synthesizer on-chip 2.5 ghz prescaler
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MB15E07SL
FUNCTIONAL DESCRIPTION
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
f
= [(M
N) + A]
VCO
f
: Output frequency of external voltage controlled oscillator (VCO)
VCO
N
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0
f
: Output frequency of the reference frequency oscillator
OSC
R
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
M : Preset divide ratio of modulus prescaler (32 or 64)
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken
high, stored data is latched according to the control bit data as follows:
Table 1. Control Bit
Control bit (CNT)
H
L
(1) Shift Register Configuration
Programmable Reference Counter
LSB
1
2
3
4
C
R
R
R
N
1
2
3
T
CNT
: Control bit
R1 to R14 : Divide ratio setting bit for the programmable reference counter (3 to 16,383)
SW
: Divide ratio setting bit for the prescaler (32/33 or 64/65)
FC
: Phase control bit for the phase comparator
LDS
: LD/f
OUT
CS
: Charge pump current select bit
Note: Start data input with MSB first.
8
f
R (A < N)
OSC
For the programmable reference divider
For the programmable divider
Data Flow
5
6
7
8
9
R
R
R
R
R
4
5
6
7
8
signal select bit
A
127)
Destination of serial data
10
11
12
13
14
R
R
R
R
R
9
10
11
12
13
MSB
15
16
17
18
19
R
14
SW FC LDS CS
[Table 1]
[Table 2]
[Table 5]
[Table 8]
[Table 7]
[Table 6]

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