Fujitsu MB15E07SL User Manual page 14

Single serial input pll frequency synthesizer on-chip 2.5 ghz prescaler
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MB15E07SL
PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
LD
[FC = "H"]
D
O
[FC = "L"]
D
O
Notes :
Phase error detection range: –2 to +2
Pulses on Do signal during locked state are output to prevent dead zone.
LD output becomes low when phase is t
is t
WL
t
and t
WU
t
> 2/fosc (s) (e. g. t
WU
t
< 4/fosc (s) (e. g. t
WU
LD becomes high during the power saving mode (PS = "L").
14
t
WU
or less and continues to be so for three cycles or more.
depend on OSC
input frequency.
WL
IN
> 156.3 ns, fosc = 12.8 MHz)
WU
< 312.5 ns, fosc = 12.8 MHz)
WL
t
WL
or more. LD output becomes high when phase error
WU

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