Intel Piix4 - Acer TM7100 Series Service Manual

2.2

Intel PIIX4

PIIX4 is a multi-function PCI device that integrates many system-level functions.
PCI to ISA/EIO Bridge
PIIX4 is compatible with the PCI Rev 2.1 specification, as well as the IEEE 996 specification for the
ISA (AT) bus. On PCI, PIIX4 operates as a master for various internal modules, such as the USB
controller, DMA controller, IDE bus master controller, distributed DMA masters, and on behalf of
ISA masters. PIIX4 operates as a slave for its internal registers or for cycles that are passed to the
ISA or EIO buses. All internal registers are positively decoded.
PIIX4 can be configured for a full ISA bus or a subset of the ISA bus called the Extended IO (EIO)
bus. The use of the EIO bus allows unused signals to be configured as general purpose inputs and
outputs. PIIX4 can directly drive up to five ISA slots without external data or address buffering. It
also provides byte-swap logic, I/O recovery support, wait-state generation, and SYSCLK
generation. X-Bus chip selects are provided for Keyboard Controller, BIOS, Real Time Clock, a
second microcontroller, as well as two programmable chip selects.
PIIX4 can be configured as either a subtractive decode PCI to ISA bridge or as a positive decode
bridge. This gives a system designer the option of placing another subtractive decode bridge in the
system (e.g., an Intel 380FB Dock Set).
IDE Interface (Bus Master capability and synchronous DMA Mode)
The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks
and CD ROMs.
Each IDE device can have independent timings. The IDE interface supports PIO IDE transfers up
to 14 Mbytes/sec and Bus Master IDE transfers up to 33 Mbytes/sec. It does not consume any ISA
DMA resources. The IDE interface integrates 16x32-bit buffers for optimal transfers.
PIIX4's IDE system contains two independent IDE signal channels. They can be electrically isolated
independently, allowing for the implementation of a "glueless" Swap Bay. They can be configured
to the standard primary and secondary channels (four devices) or primary drive 0 and primary drive
1 channels (two devices). This allows flexibility in system design and device power management.
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently
programmable channels. Channels [0:3] are hardwired to 8-bit, count-by-byte transfers, and
channels [5:7] are hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA
channels can be programmed to support fast Type-F transfers. The DMA controller also generates
the ISA refresh cycles.
The DMA controller supports two separate methods for handling legacy DMA via the PCI bus. The
PC/PCI protocol allows PCI-based peripherals to initiate DMA cycles by encoding requests and
grants via three PC/PCI REQ#/GNT# pairs. The second method, Distributed DMA, allows reads
and writes to 82C37 registers to be distributed to other PCI devices. The two methods can be
enabled concurrently. The serial interrupt scheme typically associated with Distributed DMA is also
supported.