Acer TM7100 Series Service Manual page 70

Table 2-2 82371AB Pin Descriptions
Name Type
IOW# I/O
LA[23:17]/ I/O
GPO[7:1]
MEMCS16# I/O
MEMR# I/O
MEMW# I/O
REFRESH# I/O
RSTDRV O
I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave may
latch data from the ISA data bus (SD[15:0]). IOW# is an output when PIIX4
owns the ISA Bus. IOW# is an input when an external ISA master owns the ISA
Bus.
During Reset: High-Z After Reset: High During POS: High
ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory on
the ISA Bus up to 16 Mbytes. LA[23:17] are outputs when PIIX4 owns the ISA
Bus. The LA[23:17] lines become inputs whenever an ISA master owns the ISA
Bus. If the EIO bus is used, these signals become a general purpose output.
During Reset: High-Z After Reset: Undefined During POS: Last LA/GPO
MEMORY CHIP SELECT 16. MEMCS16# is a decode of LA[23:17] without any
qualification of the command signal lines. ISA slaves that are 16-bit memory
devices drive this signal low. PIIX4 ignores MEMCS16# during I/O access cycles
and refresh cycles. MEMCS16# is an input when PIIX4 owns the ISA Bus. PIIX4
drives this signal low during ISA master to PCI memory cycles.
During Reset: High-Z After Reset: High-Z During POS: High-Z
MEMORY READ. MEMR# is the command to a memory slave that it may drive
data onto the ISA data bus. MEMR# is an output when PIIX4 is a master on the
ISA Bus. MEMR# is an input when an ISA master, other than PIIX4, owns the
ISA Bus. This signal is also driven by PIIX4 during refresh cycles. For DMA
cycles, PIIX4, as a master, asserts MEMR#.
During Reset: High-Z After Reset: High During POS: High
MEMORY WRITE. MEMW# is the command to a memory slave that it may latch
data from the ISA data bus. MEMW# is an output when PIIX4 owns the ISA Bus.
MEMW# is an input when an ISA master, other than PIIX4, owns the ISA Bus.
For DMA cycles, PIIX4, as a master, asserts MEMW#.
During Reset: High-Z After Reset: High During POS: High
REFRESH. As an output, REFRESH# is used by PIIX4 to indicate when a
refresh cycle is in progress. It should be used to enable the SA[7:0] address to
the row address inputs of all banks of dynamic memory on the ISA Bus. Thus,
when MEMR# is asserted, the entire expansion bus dynamic memory is
refreshed. Memory slaves must not drive any data onto the bus during refresh.
As an output, this signal is driven directly onto the ISA Bus. This signal is an
output only when PIIX4 DMA refresh controller is a master on the bus
responding to an internally generated request for refresh. As an input,
REFRESH# is driven by 16-bit ISA Bus masters to initiate refresh cycles.
During Reset: High-Z After Reset: High During POS: High
RESET DRIVE. PIIX4 asserts RSTDRV to reset devices that reside on the
ISA/EIO Bus. PIIX4 asserts this signal during a hard reset and during power-up.
RSTDRV is asserted during power-up and negated after PWROK is driven
active. RSTDRV is also driven active for a minimum of 1 ms if a hard reset has
been programmed in the RC register.
During Reset: High After Reset: Low During POS: Low
Description