Acer TM7100 Series Service Manual page 75

Table 2-2 82371AB Pin Descriptions
Name Type
IRQ 12/M I
PIRQ[A:D]# I/OD
PCI
SERIRQ/ I/O
GPI7
CPU INTERFACE SIGNALS
A20M# OD
CPURST OD
FERR# I
IGNNE# OD
INTERRUPT REQUEST 12. In addition to providing the standard interrupt
function as described in the pin description for IRQ[3:7,9:11,14:15], this pin can
also be programmed to provide the mouse interrupt function. When the mouse
interrupt function is selected, a low to high transition on this signal is latched by
PIIX4 and an INTR is generated to the CPU as IRQ12. An internal IRQ12
interrupt continues to be generated until a Reset or an I/O read access to
address 60h (falling edge of IOR#) is detected.
PROGRAMMABLE INTERRUPT REQUEST. The PIRQx# signals are active
low, level sensitive, shareable interrupt inputs. They can be individually steered
to ISA interrupts IRQ [3:7,9:12,14:15]. The USB controller uses PIRQD# as its
output signal.
SERIAL INTERRUPT REQUEST. Serial interrupt input decoder, typically used in
conjunction with the Distributed DMA protocol. If not using serial interrupts, this
pin can be used as a general-purpose input.
ADDRESS 20 MASK. PIIX4 asserts A20M# to the CPU based on combination of
Port 92 Register, bit 1 (FAST_A20), and A20GATE input signal.
During Reset: High-Z After Reset: High-Z During POS: High-Z
CPU RESET. PIIX4 asserts CPURST to reset the CPU. PIIX4 asserts CPURST
during power-up and when a hard reset sequence is initiated through the RC
register. CPURST is driven inactive a minimum of 2 ms after PWROK is driven
active. CPURST is driven active for a minimum of 2 ms when initiated through
the RC register. The inactive edge of CPURST is driven synchronously to the
rising edge of PCICLK. If a hard reset is initiated through the RC register, PIIX4
resets its internal registers (in both core and suspend wells) to their default state.
This signal is active high for Pentium processor and active-low for Pentium II
processor as determined by CONFIG1 signal. For values During Reset, After
Reset, and During POS, see the Suspend/Resume and Resume Control
Signaling section.
NUMERIC COPROCESSOR ERROR. This pin functions as a FERR# signal
supporting coprocessor errors. This signal is tied to the coprocessor error signal
on the CPU. If FERR# is asserted, PIIX4 generates an internal IRQ13 to its
interrupt controller unit. PIIX4 then asserts the INT output to the CPU. FERR# is
also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to
the CPU unless FERR# is active.
IGNORE NUMERIC EXCEPTION. This signal is connected to the ignore
numeric exception pin on the CPU. IGNNE# is only used if the PIIX4
coprocessor error reporting function is enabled. If FERR# is active, indicating a
coprocessor error, a write to the Coprocessor Error Register (F0h) causes the
IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If
FERR# is not asserted when the Coprocessor Error Register is written, the
IGNNE# signal is not asserted.
During Reset: High-Z After Reset: High-Z During POS: High-Z
Description