Acer TM7100 Series Service Manual page 112

Table 2-6 NS87338VJG Pin Descriptions
Pin No.
/DR1 83
(PPM Mode)
/DR23 47
/DRATE0 50, 49
/DRATE1
(Normal Mode)
/DRATE0 85
(PPM Mode)
DRQ0 54
DRQ1 31
DRQ2 2
DRQ3 58
/DRV2 47
/DSKCHG 30
(Normal Mode)
/DSKCHG 87
(PPM Mode)
/DSR1 74,
/DSR2 66
/DSTRB 76
/DTR1 69,
/DTR2 61
/ERR 77
I/O Description
O
FDC Drive Select 1. This pin offers an additional Drive Select signal
in PPM Mode when PNF = 0. It is drive select 1 when bit 4 of FCR is
0. It is drive select 0 when bit 4 of FCR is 1. This signal is active low.
O
FDC Drive 2 or 3. /DR23 is asserted when either Drive 2 or Drive 3 is
assessed(except during logical drive exchange).
O
FDC Data Rate 0, 1. These outputs reflect the currently selected FDC
data rate (bits 0 and 1 in the Configuration Control Register (CCR) or
the Data Rate Select Register (DSR), whichever was written to last).
The pins are totem-pole buffered outputs (6 mA sink, 6 mA source).
O
FDC Data Rate 0. This pin provides an additional Data Rate signal, in
PPM mode, When PNF=0.
O
DMA Request 0, 1, 2.
controller that a data transfer is required. This DMA request can be
sourced by one of the following: FDC or Parallel Port.
When it is not sourced by and of them, it is in TRI-STATE. When the
sourced device is disabled or when the sourced device is configured
with no DMA, it is also in TRI-STATE. Upon reset, DRQ2 is used by
the FDC; DRQ0, 1, 3 are in TRI-STATE. DRQ3 is multiplexed with
IRQ15 and SIRQI1.
I
FDD Drive2. This input indicates whether a second disk drive has
been installed. The state of this pin is available from Status Register
A in PS/2 mode. (See PNF for further information).
I
Disk Change. The input indicates if the drive door has been opened.
The state of this pin is available from the Digital Input Register. This
pin can also be configured as the RGATE data separator diagnostic
input via the Mode command.
I
Disk Change. This pin offers an additional Disk Change signal in
PPM Mode when PNF = 0.
I
UARTs Data Set Ready. When low, this indicates that the data set or
modem is ready to establish a communications link. The DSR signal
is a modem status input. The CPU tests the /DSR signal by reading
bit 5 (DSR) of the Modem Status Register (MSR) for the appropriate
channel. Bit 5 is the complement of the DSR signal. Bit 1 (DDSR) of
the MSR indicates whether the DSR input has changed state since the
previous reading of the MSR.
NOTE: Whenever the DDSR bit of the NSR is set, an interrupt is
generated if Modem Status interrupts are enabled.
O
EPP Data Strobe. This signal is used in EPP mode as data strobe. It
is an active low signal.
O
UARTs Data Terminal Ready. When low, this output indicates to the
modem or data set that the UART is ready to establish a
communications link. The DTR signal can be set to an active low by
programming bit 0 (DTR) of the Modem Control Register to a high
level. A Master Reset operation sets this signal to its inactive (high)
state. Loop mode operation holds this signal to its inactive state.
I
Parallel Port Error. This input is set low by the printer when an error
is detected.
attached to it.
\An active high output that signals the DMA
This pin has a nominal 25 KOHM pull-up resistor