HP XM600 - Kayak - 128 MB RAM Technical Reference Manual page 49

• Multi-function PCI Bus Interface:
PCI at 32-bit 33 MHz.
PCI Rev 2.2 Specification.
133 Mbyte/sec data transfer rate.
Master PCI Device Support for up to six devices.
• USB:
USB revision 1.1 compliant.
UHCI Implementation with Two USB Ports for serial trans-
fers at 12 or 1.5 Mbit/sec.
Wake-up from sleeping states (S1).
Legacy keyboard/mouse software.
• Power Management Logic:
ACPI 1.0 compliant.
Support for APM-based legacy power management for non-
ACPI implementations.
ACPI defined power states (S1, S3, S4, S5).
ACPI power management timer.
SMI generation.
All registers readable/restorable for proper resume from 0 V
suspend states.
PCI PME#.
• Real-Time Clock:
256-byte battery-backed CMOS RAM.
Hardware implementation to indicate Century Rollover.
• Timers Based on 82C54:
System Timer, Refresh Request, Speaker Tone Output.
• System Timer, Refresh Request, Speaker Tone Output.
• FirmWare Hub (FWH) interface.
• 241 BGA Package.
The following table shows the available ICH features.
Feature
The Input/Output Controller Hub (82801AA)
• Enhanced DMA Controller:
Two 82C37 DMA controllers.
PCI DMA with 2 PC/PCI Channels in pairs.
LPC DMA.
DMA Collection Buffer to provide Type-F DMA performance
for all DMA channels.
• Interrupt Controller:
Two cascaded 82C59 controllers.
Integrated I/O APIC capability.
15 Interrupt support in 8259 Mode, 24 supported in I/O APIC
mode.
Serial Interrupt Protocol.
• Integrated IDE Controller:
Independent Timing of up to four drives.
Ultra ATA/66 Mode (66 Mbytes/sec).
Ultra ATA/33 Mode (33 Mbytes/sec).
PIO Mode 4 transfers up to 14 Mbytes/sec.
Separate IDE connections for Primary and Secondary cables.
Integrated 16 x 32-bit buffer for IDE PCI Burst transfers.
Write Ping-Pong Buffer for faster write performances.
• System TCO Reduction Circuits:
Timers to Generate SMI# and Reset Upon.
Timers to Detect Improper Processor Reset.
Integrated Processor Frequency Strap Logic.
• SMBus:
Host Interface allows processor to communicate via SMBus.
Compatible with 2-wire I
• GPIO:
TTL, Open-Drain, Inversion.
• 3.3 V operation with 5 V Tolerant Buffers for IDE and PCI signals.
• Alert-On-LAN (AOL) support.
2 System Board
Feature
2
C bus.
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