HP XM600 - Kayak - 128 MB RAM Technical Reference Manual page 43

• Processor/Host Bus:
Supports Pentium III processor configuration at both 100
MHz and133 MHz bus speeds
Supports Symmetric Multiprocessing Protocol (SMP) for up
to two processors
APIC related buffer management support
Supports 32-bit host bus addressing
Supports 6-deep In-Order Queue
AGTL+ bus driver technology (gated)
AGTL+ receivers for reduced power
Supports single-ended AGTL+ termination in uniprocessor
configuration
• Direct Rambus Memory Controller, supporting:
Single Direct Rambus Channel
Supports PC700, and PC800 Direct Rambus DRAM modules
(HP supports PC800 modules only)
Maximum memory array size up to 256 MB using
64Mb/72Mb, 512 MB using 128Mb/144Mb, 1 GB using
256Mb/288Mb DRAM technology
Supports up to 32 Direct Rambus devices per channel
Supports a maximum DRAM address decode space of 4 GB
Configurable optional ECC operation:
- ECC with single bit Error Correction and multiple bit Error
Detection
- Single bit errors corrected and written back to memory
(auto-scrubbing)
- Parity mode not supported
• Hub Link 8-bit Interface to ICH:
Private interconnect between the MCH and ICH.
• 324-pin BGA MCH package.
Feature
• Accelerated Graphics Port (AGP) Interface:
Supports a single AGP device (either via a connector or on
the system board)
Supports AGP 2.0, including 1x/2x/4x AGP data transfers,
1.5V and 3.3V signaling, and 2x/4x Fast Write protocol
AGP Universal Connector support via dual mode buffers
AGP PIPE# or SB accesses to DRAM not snooped
AGP FRAME# accesses to DRAM are snooped
High priority access support
Hierarchical PCI configuration mechanism
Delayed transaction support for AGP-to-DRAM reads using
AGP FRAME# protocol
• Power Management:
SMRAM space re-mapping to A0000h (128 KB)
Supports HSEG and TSEG cacheable extended SMRAM
space
- 128 KB HSEG at 0FEEA0000h remapped to A0000h
- TSEG is 128 KB/256 KB/512 KB/1 MB at the top of memory
- No maximum DRAM limit to use extended SMM
SMRAM accesses from AGP or the hub interface are not al-
lowed
Suspend to DRAM (STR) support
ACPI Rev 1.0 compliant power management
APM Rev 1.2 compliant power management
• Arbitration:
Distributed Arbitration Model for Optimum Concurrency
Support.
Concurrent operations of host, hub interface, AGP and
memory buses supported via a dedicated arbitration and
data buffering logic.
• Input/Output Device Support:
Input/Output Controller Hub (ICH).
2 System Board
Memory Controller Hub (MCH) 82820
Feature
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