Elan EM78P458 User Manual
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Elan EM78P458 User Manual

8-bit micro-controller
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EM78P458/459
OTP ROM
EM78P458/459
8-BIT MICRO-CONTROLLER
Version 1.3
ELAN MICROELECTRONICS CORP.
st
No. 12, Innovation 1
RD., Science-Based Industrial Park
Hsin Chu City, Taiwan, R.O.C.
TEL: (03) 5639977
FAX: (03)5782037(SL) 5630118 (FAE)

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Summary of Contents for Elan EM78P458

  • Page 1 EM78P458/459 OTP ROM EM78P458/459 8-BIT MICRO-CONTROLLER Version 1.3 ELAN MICROELECTRONICS CORP. No. 12, Innovation 1 RD., Science-Based Industrial Park Hsin Chu City, Taiwan, R.O.C. TEL: (03) 5639977 FAX: (03)5782037(SL) 5630118 (FAE)

  • Page 2: Application Note

    Application Note AN-001 A/D Pre-amplifier AN-002 Calibration Offset on A/D AN-003 Example of Microcomputer Digital Thermometer AN-004 Tips on how to apply EM78P458 AN-005 Tips on how to apply A/D Converter AN-006 AD & R4 AN-007 Enhancing Noise Immunity This specification is subject to change without prior notice.

  • Page 3: General Description

    1. GENERAL DESCRIPTION EM78P458 and EM78P459 are 8-bit microprocessors designed and developed with low-power and high-speed CMOS technology. It is equipped with a 4K*13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). With its OTP-ROM feature, it is able to offer a convenient way of developing and verifying user’s programs.
  • Page 4 • Programmable free running watchdog timer • 8 Programmable pull-down I/O pins • 7 programmable pull-high I/O pins • 8 programmable open-drain I/O pins • Two clocks per instruction cycle This specification is subject to change without prior notice. EM78P458/459 OTP ROM 07.01.2003 (V1.3)
  • Page 5 * 24 pin skinny DIP 300mil : EM78P459AK * 24 pin SOP 300mil • Power on voltage detector available (2.0V± 0.15V) This specification is subject to change without prior notice. : EM78P458AP : EM78P458AM : EM78P459AM EM78P458/459 OTP ROM 07.01.2003 (V1.3)

  • Page 6: Pin Assignment

    3. PIN ASSIGNMENT P56/CIN+ P57/CO P60/ADC1 P61/ADC2 P62/ADC3 P63/ADC4 P64/ADC5 P65/ADC6 P66/ADC7 Table 1 EM78P458 Pin Description Symbol Pin No. OSCI OSCO 13~15 P51 ~ P57 19, 20, 1, 2 3, 4, P60 ~ P67 6~11 3, 4, ADC1~ADC8 6 ~ 11...
  • Page 7 * Pull-high is on if /RESET is asserted. * Real time clock/counter with Schmitt trigger input pin; it must be tied to VDD or VSS if it is not in use. 1: Enable TCC; 0: Disable TCC. Ground. EM78P458/459 OTP ROM Function 07.01.2003 (V1.3)

  • Page 8: Function Description

    & Wake Up Control Comparators Fig. 2 The Functional Block Diagram of EM78P458/459 4.1 Operational Registers 1. R0 (Indirect Addressing Register) R0 is not a physically implemented register. Its major function is to perform as an indirect addressing pointer. Any instruction using R0 as a pointer, actually accesses data pointed by the RAM Select Register (R4).
  • Page 9 256 locations of a page. • In the case of EM78P458/459, the most two significant bits (A11 and A10) will be loaded with the content of PS1 and PS0 in the status register (R3) upon the execution of a "JMP", "CALL", or any other instructions set which write to R2.
  • Page 10 7. R7 ~ R8 • All of these are 8-bit general-purpose registers. This specification is subject to change without prior notice. Program memory page [Address] Page 0 [000-3FF] Page 1 [400-7FF] Page 2 [800-BFF] Page 3 [C00-FFF] EM78P458/459 OTP ROM 07.01.2003 (V1.3)
  • Page 11 IOCA0 (AD-CMPCON) IOCB0 IOCC0 IOCD0 IOCE0 IOCF0 32x8 Bank Register (Bank 0) Fig. 4 Data Memory Configuration EM78P458/459 OTP ROM IOC51 (PWMCON) IOC61 (DT1L) IOC71 (DT1H) IOC81 (PRD1) IOC91 (DT2L) IOCA1 (DT2H) IOCB1 (PRD2) IOCC1 (DL1L) IOCD1 (DL1H) IOCE1 (DL2L)
  • Page 12 ADIF is set. 10. RB An 8-bit general-purpose register. 11. RC A 2-bit, Bit 0and Bit 1 register. 12. RD This specification is subject to change without prior notice. IOCS ADRUN ADPD EM78P458/459 OTP ROM ADIS2 ADIS1 ADIS0 07.01.2003 (V1.3)

  • Page 13: Special Purpose Registers

    4.2 Special Purpose Registers 1. A (Accumulator) • Internal data transfer, or instruction operand holding • It can not be addressed. This specification is subject to change without prior notice. PWM2IF PWM1IF ADIF EM78P458/459 OTP ROM EXIF ICIF TCIF 07.01.2003 (V1.3)
  • Page 14 • IOC50 and IOC60 registers are both readable and writable. This specification is subject to change without prior notice. PSR0 TCC Rate WDT Rate 1:16 1:32 1:64 1:128 1:256 1:128 EM78P458/459 PSR2 PSR1 1:16 1:32 1:64 OTP ROM PSR0 07.01.2003 (V1.3)
  • Page 15 0 = The Vref of the ADC is connected to Vdd (default value), and the P53/VREF pin carries out the function of P53; This specification is subject to change without prior notice. IMS2 IMS1 EM78P458/459 OTP ROM IMS0 CKR1 CKR0...
  • Page 16 • Bit 2 (/PD2) Control bit is used to enable the pull-down of the P62 pin. • Bit 3 (/PD3) Control bit is used to enable the pull-down of the P63 pin. This specification is subject to change without prior notice. /PD5 /PD4 /PD3 EM78P458/459 /PD2 /PD1 07.01.2003 (V1.3) OTP ROM /PD0...
  • Page 17 • Bit 7 (/PH7) Control bit is used to enable the pull-high of the P56 pin. • IOCD0 register is both readable and writable. This specification is subject to change without prior notice. /OD5 /OD4 /OD3 /PH5 /PH3 EM78P458/459 OTP ROM /OD2 /OD1 /OD0 /PH2 /PH1 /PH0...
  • Page 18 1: enable ADIF interrupt • Bit 4 (PWM1IE) PWM1IF interrupt enable bit. 0: disable PWM1 interrupt 1: enable PWM1 interrupt This specification is subject to change without prior notice. PWM2IE PWM1IE ADIE EM78P458/459 OTP ROM EXIE ICIE TCIE 07.01.2003 (V1.3)
  • Page 19 1 = TMR1 is on. • Bit 3: Bit 2 ( T2P1:T2P0 ): TMR2 clock prescale option bits. T2P1 T2P0 This specification is subject to change without prior notice. T2EN T1EN T2P1 Prescale 1:2(Default) 1:32 1:64 EM78P458/459 OTP ROM T2P0 T1P1 T1P0 07.01.2003 (V1.3)
  • Page 20 16. IOCA1 ( DT2H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle of PWM2 ) CALI2 SIGN2 • Bit 7 (CALI2): Calibration enable bit This specification is subject to change without prior notice. Prescale 1:2(Default) 1:32 1:64 VOF1[2] VOF1[1] VOF1[0] VOF2[2] VOF2[1] VOF2[0] EM78P458/459 OTP ROM PWM1[9] PWM1[8] PWM2[9] PWM2[8] 07.01.2003 (V1.3)
  • Page 21 21. IOCF1 ( DL2H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle Latch of PWM2 ) The content of IOCF1 is read-only. This specification is subject to change without prior notice. EM78P458/459 OTP ROM 07.01.2003 (V1.3)

  • Page 22: Tcc/Wdt & Prescaler

    Refer to WDTE bit of IOCE0 register. Without presacler, the WDT time-out period is approximately 18 ms NOTE: VDD=5V,Setup time period = 16ms ± 5%. VDD=3V,Setup time period = 19ms ± 5%. This specification is subject to change without prior notice. EM78P458/459 OTP ROM 07.01.2003 (V1.3)
  • Page 23 Fig. 6, Fig. 7, and Fig. 8 respectively. This specification is subject to change without prior notice. WDTE (in IOCE) WDT timeout Fig. 5 Block Diagram of TCC and WDT EM78P458/459 DATA BUS SYNC TCC (R1) 2 cycles TCC overflow...
  • Page 24 Fig. 7 The Circuit of I/O Port and I/O Control Register for P50(/INT) This specification is subject to change without prior notice. PCRD PDRD NOTE: Pull-down is not shown in the figure. PCRD EM78P458/459 PCWR PDWR PCWR PDWR PDRD TI 0 OTP ROM 07.01.2003 (V1.3)
  • Page 25 Fig. 8 The Circuit of I/O Port and I/O Control Register for P60~P67 IOCE.1 /SLEP Fig. 9 Block Diagram of Port 6 with Input Changed Interrupt/Wake-up This specification is subject to change without prior notice. PCRD PCWR PDWR EM78P458/459 PDRD TI n Interrupt RE.1 ENI Instruction DISI Instruction Interrupt...

  • Page 26: Reset And Wake-Up

    WDT (if enabled) is cleared but keeps on running. The controller can be awakened by- This specification is subject to change without prior notice. Usage of Port 6 Input Status Changed Wake-up/Interrupt EM78P458/459 (II) Port 6 Input Status Change Interrupt 1. Read I/O Port 6 (MOV R6,R6) 2.
  • Page 27 (3) Port 6 input status change (if enabled). (4) Comparator high. The first two cases will cause the EM78P458/459 to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). Case 3 is considered the continuation of program execution and the global interrupt ("ENI"...
  • Page 28 IOW RF ENI (or DISI) SLEP Similarly, if the Comparator High Interrupt is used to wake up the EM78P458/459 (as in Case [c] above), the following instructions must be executed before SLEP: MOV A, @0Bxx000110 CONTW CLR R1 MOV A, @0Bxxxx1110...
  • Page 29 *P: Previous value before reset Oscillator Power-On Reset Voltage Detector /RESET This specification is subject to change without prior notice. Reset Type Event WDT Timeout Fig. 10 Block Diagram of Reset of Controller EM78P458/459 Reset Setup time 07.01.2003 (V1.3) OTP ROM...
  • Page 30 P50 pin configured as /INT, is excluded from this function. Port 6 Input Status Change Interrupt will wake up the EM78P458/459 from the sleep mode if it is enabled prior to going into the sleep mode by executing SLEP. When the controller is wake-up, it will continue to execute the succeeding program if the global interrupt is disabled, or branches out to the interrupt vector 008H if the global interrupt is enabled.

  • Page 31: Analog-To-Digital Converter (Adc)

    Fig. 12 The Functional Block Diagram of Analog-to-Digital Conversion This specification is subject to change without prior notice. Fig. 11 Interrupt Input Circuit ( successive approximation ) Fsco Internal ADCON AD-CMPCON GCON DATA BUS EM78P458/459 Vref Power-Down Start to Convert ADDATA ADCON OTP ROM 07.01.2003 (V1.3)
  • Page 32 SYMBOL *Init_Value *Init_Value: Initial value at power on reset • VREFS (Bit 7): The input source of the Vref of the ADC. This specification is subject to change without prior notice. IOCS VREFS EM78P458/459 ADRUN ADPD ADIS2 IMS2 IMS1 IMS0...
  • Page 33 2. ADC Data Register (ADDATA/RA) This specification is subject to change without prior notice. OP2E OP1E Gain Range of Operating Voltage 0 ~ Vref 0 ~ (1/2)Vref 0 ~ (1/4)Vref 0 ~ (1/8)Vref 0 ~ (1/16)Vref 0 ~ (1/32)Vref EM78P458/459 OTP ROM 07.01.2003 (V1.3)

  • Page 34: A/D Conversion Time

    CKR0 and CKR1 select the conversion time (Tct), in terms of instruction cycles. This allows the MCU to run at the maximum frequency without sacrificing the accuracy of A/D conversion. For the EM78P458/459, the conversion time per bit is about 4μs. Table 8 shows the relationship between Tct and the maximum operating frequencies.
  • Page 35 This specification is subject to change without prior notice. ; Indirect addressing register ; Status register ; Interrupt status register ; Control Register of Port 5 ; Control Register of Port 6 ; Interrupt Control Register EM78P458/459 OTP ROM 07.01.2003 (V1.3)
  • Page 36 ; Interrupt vector ; To clear the ADCIF bit ; To start to execute the next AD conversion if necessary ; Enable the interrupt function of ADC, “X” by application ; Interrupt disabled:<6> EM78P458/459 OTP ROM IMS0 CKR1 CKR0 07.01.2003 (V1.3)
  • Page 37 ; To disable the power-down mode of ADC ; Enable the interrupt function ; Start to run the ADC ; To check the ADRUN bit continuously; ; ADRUN bit will be reset as the AD conversion is completed EM78P458/459 OTP ROM 07.01.2003 (V1.3)
  • Page 38 Com parator TM R2H + TM R2L Com parator PRD2 PRD1 = TMR1 DT1 = TMR1 Fig. 14 The Output Timing of the PWM EM78P458/459 OTP ROM latch To PW M 1IF Duty Cycle M atch PW M 1 reset...
  • Page 39 (4) Set PWMX pin to be output by writing a desired value to IOC51. (5) Load a desired value to IOC51 with TMRX prescaler value and enable both PWMX and TMRX. This specification is subject to change without prior notice. EM78P458/459 OTP ROM 07.01.2003 (V1.3)
  • Page 40 This specification is subject to change without prior notice. reset TMR1X Comparator PRD1 PRD2 Comparator reset TMR2X *TMR1X = TMR1H + TMR1L; *TMR2X = TMR2H +TMR2L Fig. 15 TMRX Block Diagram EM78P458/459 OTP ROM To PWM1IF Period Match Data Bus Period Match To PWM2IF Timer register; TMRX...

  • Page 41: External Reference Signal

    PWMX. 4.10 Comparator EM78P458/459 has one comparator, which has two analog inputs and one output. The comparator can be employed to wake up from the sleep mode. Fig. 16 shows the circuit of the comparator. 1. External Reference Signal The analog signal that is presented at Cin- compares to the signal at Cin+, and the digital output (CO) of the comparator is adjusted accordingly.
  • Page 42 • CMPIF (RF.6), the comparator interrupt flag, can only be cleared by software. 5. Wake-up from SLEEP Mode This specification is subject to change without prior notice. RESET CMRD EM78P458/459 OTP ROM From OP I/O CMRD To CPIF From other comparator 07.01.2003 (V1.3)
  • Page 43 Bit Name OP2E OP1E Power-on Bit Name VREFS Power-on Bit Name PWM2E PWM2E Power-on Bit Name Bit7 Bit6 Power-on EM78P458/459 Bit 5 Bit 4 Bit 3 Bit 2 */PD5 */PD4 /PD3 /PD2 /PH5 /PH4 /PH3 /PH2 PMW2IE PWM1IE ADIE EXIE...
  • Page 44 Bit Name Power-on Bit Name Power-on Bit Name Power-on Jump to address 0x08 or continue to execute next instruction Bit Name Power-on Bit Name Power-on EM78P458/459 Bit 5 Bit 4 Bit 3 Bit 2 VOF1[2] VOF1[1] VOF1[0] Bit5 Bit4 Bit3...

  • Page 45: Oscillator Modes

    4.12 Oscillator 1. Oscillator Modes The EM78P458 and EM78P459 can be operated in four different oscillator modes, such as High XTAL oscillator mode (HXT), Low XTAL oscillator mode (LXT), External RC oscillator mode (ERC), and RC oscillator mode with Internal capacitor (IC). Users can select one of them by programming the This specification is subject to change without prior notice.
  • Page 46 Two clocks 2. Crystal Oscillator/Ceramic Resonators (XTAL) EM78P458/459 can be driven by an external clock signal through the OSCI pin as shown in Fig. 18 below. In the most applications, pin OSCI and pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation.
  • Page 47 Table 13 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators Oscillator Type Ceramic Resonators Crystal Oscillator OSCI EM78P458 EM78P459 Fig. 20 Circuit for Crystal/Resonator-Series Mode EM78P458 EM78P459 Fig. 21 Circuit for Crystal/Resonator-Parallel Mode This specification is subject to change without prior notice.

  • Page 48: External Rc Oscillator Mode

    Fig. 22 Circuit for External RC Oscillator Mode Table 14 RC Oscillator Frequencies Cext Rext 3.3k 5.1k 20 pF 100k This specification is subject to change without prior notice. OSCI EM78P458 EM78P459 Average Fosc 5V,25°C 3.57 MHz 2.63MHz 1.30 MHz 150 KHz EM78P458/459 OTP ROM Rext Cext Average Fosc 3V,25°C...

  • Page 49: Rc Oscillator Mode With Internal Capacitor

    1.43 MHz 980 KHz 520 KHz 57 KHz 510 KHz 340 KHz 175 KHz 19 KHz OSCI EM78P458 EM78P459 Fig. 23 Circuit for Internal C Oscillator Mode Average Fosc 3V,25°C 2.22 MHz 1.15 MHz 375 KHz EM78P458/459 1.35 MHz 877 KHz...

  • Page 50: Power-On Considerations

    Vdd must drop to below 1.2V and remains OFF for 10us before power can be switched ON again. This way, the EM78P458/459 will reset and work normally. The extra external reset circuit will work well if Vdd can rise at very fast speed (50 ms or less). However, under most cases where critical applications are involved, extra devices are required to assist in solving the power-up problems.

  • Page 51: Code Option

    EM78P459 /RESET Fig. 26 Circuit 2 for the Residue Voltage Protection 4.14 CODE OPTION EM78P458/459 has one CODE option word and one Customer ID word that are not a part of the normal program memory. Bit12~Bit0 Code option12~0 1. Code Option Register (Word 0)
  • Page 52 • Bit 7 ~ Bit 5 (VOF1[2]~VOF210)): Offset voltage bits • Bit 4 ~ Bit 0 : Not used. This specification is subject to change without prior notice. Bit10 Bit9 Bit8 VOF2[1] VOF2[0] SIGN1 EM78P458/459 OTP ROM Bit7 Bit6 Bit5 VOF1[2] VOF1[1] VOF1[0] 07.01.2003 (V1.3)

  • Page 53: Instruction Set

    "b" represents a bit field designator that selects the value for the bit located in the register "R" that is affected by the operation. The symbol "k" represents an 8 or 10-bit constant or literal value. Table 16 The list of the instruction set of EM78P458/459 INSTRUCTION BINARY...
  • Page 54 [Top of Stack] → PC k-A → A SUB A,k PC+1 → [SP], 001H → PC k+A → A ADD A,k R2+A → R2 Bits 8~9 of R2 unchanged EM78P458/459 OTP ROM STATUS AFFECTED Z,C,DC Z,C,DC None None None None...

  • Page 55: Timing Diagrams

    RESET Tim ing (CLK="0") /RESET TCC Input Tim ing (CLKS="0") T ins T CC This specification is subject to change without prior notice. TEST POIN TS NO P T drh T tcc EM78P458/459 OTP ROM Instruction 1 Executed 07.01.2003 (V1.3)

  • Page 56: Absolute Maximum Ratings

    5. ABSOLUTE MAXIMUM RATINGS Items Temperature under bias Storage temperature Input voltage Output voltage This specification is subject to change without prior notice. Rating 0°C -65°C -0.3V -0.3V EM78P458/459 OTP ROM 70°C 150°C +6.0V +6.0V 07.01.2003 (V1.3)

  • Page 57: Dc Electrical Characteristic

    /RESET=‘High',Fosc=32KHz (Crystal type, two clocks), output pin floating, WDT enabled /RESET='High', Fosc=2MHz (Crystal type, two clocks), output pin floating /RESET='High', Fosc=4MHz (Crystal type, two clocks), output pin floating EM78P458/459 OTP ROM Unit F±30% ±1 µA µA -100 -240 µA µA µA...

  • Page 58: Ac Electrical Characteristic

    AREF Vdd=V =5.0V, V =0.0V AREF Vdd=V =5.0V, V AREF =0.0V,RL=10KΩ Vdd=V =5.0V, V =0.0V AREF Vdd=5.0V±0.5V (Vdd = 5.0V,Vss=0V,Ta=0 to 70℃) Condition EM78P458/459 OTP ROM Unit Min. Typ. Max. Unit AREF 1000 Bits ±2 ±4 ±0.5 ±0.9 ±0 ±2 ±4...
  • Page 59 2.These parameters are for design guidance only and are not tested. 3.Specifications subject to change without notice. This specification is subject to change without prior notice. Vdd =5.0V, V =0.0V Vd =5.0V, V =0.0V,RL=10KΩ Vdd= 5.0V, V =0.0V Vdd= 5.0V, V =0.0V EM78P458/459 OTP ROM ±10 ±20 07.01.2003 (V1.3)

  • Page 60: Package Types

    Package Types: OTP MCU EM78P458AP EM78P458AM EM78P459AK EM78P459AM This specification is subject to change without prior notice. Package Type Pin Count Skinny DIP EM78P458/459 OTP ROM Package Size 20 pin 300mil 20 pin 300mil 24 pin 300mil 24 pin 300mil...

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