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C141-E104-03EN
MHL2300AT, MHM2200AT,
MHM2150AT, MHM2100AT
DISK DRIVES
PRODUCT MANUAL

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   Also See for Fujitsu MHM2100AT - Mobile 10 GB Hard Drive

   Summary of Contents for Fujitsu MHM2100AT - Mobile 10 GB Hard Drive

  • Page 1

    C141-E104-03EN MHL2300AT, MHM2200AT, MHM2150AT, MHM2100AT DISK DRIVES PRODUCT MANUAL...

  • Page 2

    “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully. FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.

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  • Page 4: Revision History

    Revision History (1/1) Edition Date Revised section (*1) Details (Added/Deleted/Altered) 2000-02-15 — — 2000-09-20 - Table 1.1 - Specification (Number of Sections for MHL2300AT) was altered. - Table 1.2 - Order No. was changed. - (16) SET MAX in Section - SET MAX commands are added.

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  • Page 6: Chapter 3 Installation Conditions

    Preface This manual describes the MHL Series and MHM Series, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the ATA interface. This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems.

  • Page 7: Operating Environment

    Preface Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the alert signals and their meanings: This indicates a hazardous situation could result in CAUTION...

  • Page 8

    “Disk drive defects” refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.

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  • Page 10: Important Alert Items

    Important Alert Items Important Alert Messages The important alert messages in this manual are as follows: A hazardous situation could result in minor or moderate personal CAUTION injury if the user does not perform the procedure correctly. Also, damage to the predate or other property, may occur if the user does not perform the procedure correctly.

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  • Page 12: Manual Organization

    Manual Organization MHL2300AT, MHM2200AT, • Device Overview MHM2150AT, MHM2100AT • Device Configuration • Installation Conditions DISK DRIVES • Theory of Device Operation PRODUCT MANUAL • Interface (C141-E104) • Operations <This manual> MHL2300AT, MHM2200AT, • Maintenance and Diagnosis MHM2150AT, MHM2100AT • Removal and Replacement Procedure DISK DRIVES MAINTENANCE MANUAL (C141-F043)

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  • Page 14: Table Of Contents

    Contents CHAPTER 1 Device Overview ............... 1-1 Features 1.1.1 Functions and performance 1.1.2 Adaptability 1.1.3 Interface Device Specifications 1.2.1 Specifications summary 1.2.2 Model and product number Power Requirements Environmental Specifications Acoustic Noise Shock and Vibration Reliability Error Rate 1-10 Media Defects 1-10 CHAPTER 2 Device Configuration..............

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    Contents CHAPTER 3 Installation Conditions.............. 3-1 Dimensions Mounting Cable Connections 3-10 3.3.1 Device connector 3-10 3.3.2 Cable connector specifications 3-11 3.3.3 Device connection 3-11 3.3.4 Power supply connector (CN1) 3-12 Jumper Settings 3-12 3.4.1 Location of setting jumpers 3-12 3.4.2 Factory default setting 3-13 3.4.3...

  • Page 16

    Contents 4.6.2 Write circuit 4-11 4.6.3 Read circuit 4-13 4.6.4 Digital PLL circuit 4-14 Servo Control 4-15 4.7.1 Servo control circuit 4-15 4.7.2 Data-surface servo format 4-18 4.7.3 Servo frame format 4-20 4.7.4 Actuator motor control 4-21 4.7.5 Spindle motor control 4-22 CHAPTER 5 Interface..................

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    Contents 5.5.2.1 Ultra DMA burst initiation phase 5-93 5.5.2.2 Data transfer phase 5-94 5.5.2.3 Ultra DMA burst termination phase 5-94 5.5.3 Ultra DMA data in commands 5-95 5.5.3.1 Initiating an Ultra DMA data in burst 5-95 5.5.3.2 The data in transfer 5-96 5.5.3.3 Pausing an Ultra DMA data in burst 5-96...

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    Contents 6.1.1 Response to power-on 6.1.2 Response to hardware reset 6.1.3 Response to software reset 6.1.4 Response to diagnostic command Address Translation 6.2.1 Default parameters 6.2.2 Logical address Power Save 6.3.1 Power save mode 6.3.2 Power commands 6-11 Defect Management 6-11 6.4.1 Spare area...

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    Contents Illustrations Figures Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on Figure 2.1 Disk drive outerview (the MHL Series and MHM Series) Figure 2.2 Configuration of disk media heads Figure 2.3 1 drive system configuration Figure 2.4 2 drives configuration Figure 3.1 Dimensions (MHL/MHM series) Figure 3.2 Orientation (Sample: MHL2300AT) Figure 3.3 Mounting frame structure...

  • Page 20

    Contents Figure 5.3 Read Sector(s) command protocol 5-86 Figure 5.4 Protocol for command abort 5-87 Figure 5.5 WRITE SECTOR(S) command protocol 5-88 Figure 5.6 Protocol for the command execution without data transfer 5-90 Figure 5.7 Normal DMA data transfer 5-91 Figure 5.8 An example of generation of parallel CRC 5-105 Figure 5.9 Ultra DMA termination with pull-up or pull-down...

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    Contents Table 4.1 Self-calibration execution timechart 4-10 Table 4.2 Write precompensation algorithm 4-11 Table 5.1 Signal assignment on the interface connector Table 5.2 I/O registers Table 5.3 Command code and parameters 5-14 Table 5.4 Information to be read by IDENTIFY DEVICE command 5-32 Table 5.5 Features register values and settable modes...

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    CHAPTER 1 Device Overview Features Device Specifications Power Requirements Environmental Specifications Acoustic Noise Shock and Vibration Reliability Error Rate Media Defects Overview and features are described in this chapter, and specifications and power requirement are described. The MHL Series and MHM Series are 2.5-inch hard disk drives with built-in disk controllers.

  • Page 23: Functions And Performance

    Device Overview 1.1 Features 1.1.1 Functions and performance The following features of the MHL Series and MHM Series are described. (1) Compact The MHL2300AT has 3 built-in disks (the diameter is 65mm[2.5inch]), and its height is 12.5 mm (0.492 inch). The MHM2200AT, MHM2150AT and MHM2100AT have 1 disk or 2 disks of 65 mm (2.5 inches) diameter, and its height is 9.5 mm (0.374 inch).

  • Page 24

    1.1 Features 1.1.3 Interface (1) Connection to interface With the built-in ATA interface controller, the disk drives (the MHL Series and MHM Series) can be connected to an ATA interface of a personal computer. (2) 2 MB data buffer The disk drives (the MHL Series and MHM Series) uses a 2 MB data buffer to transfer data between the host and the disk media.

  • Page 25: Device Specifications

    Device Overview 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drives (MHL Series and MHM Series). Table 1.1 Specifications (1/2) MHL2300AT MHM2200AT MHM2150AT MHM2100AT Format Capacity (*1) 30 GB 20 GB 15 GB 10 GB Number of Heads Number of Cylinders (User) 19,904...

  • Page 26: Power Requirements

    1.3 Power Requirements Under the CHS mode (normal BIOS specification), formatted capacity, number of cylinders, number of heads, and number of sectors are as follows. Table 1.1 Specifications (2/2) Model Capacity No. of Cylinder No. of Heads No. of Sectors MHL2300AT 8.45 GB 16,383...

  • Page 27

    Device Overview (3) Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation. Table 1.3 Current and power dissipation Typical RMS Current Typical Power (*3) MHL Series MHM Series MHL Series MHM Series Spin up (*1) 0.9 A 0.9 A 4.5 W 4.5 W...

  • Page 28: Figure 1.1 Current Fluctuation (typ.) At +5v When Power Is Turned On

    1.4 Environmental Specifications Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on (5) Power on/off sequence The voltage detector circuits (the MHL Series and MHM Series) monitor +5 V. The circuits do not allow a write signal if either voltage is abnormal. These prevent data from being destroyed and eliminates the need to be concerned with the power on/off sequence.

  • Page 29: Acoustic Noise

    Device Overview 1.5 Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Acoustic noise specification Item Specification Sound Pressure • Idle mode (DRIVE READY) 30 dBA typical at 1 m Note: Measure the noise from the cover top surface. 1.6 Shock and Vibration Table 1.6 lists the shock and vibration specification.

  • Page 30

    1.7 Reliability Reliability (1) Mean time between failures (MTBF) Conditions of 300,000 h Power-on time 250H/month or less 3000H/years or less Operating time 20% or less of power-on time CSS operations 50/day or less Total 50,000 or less Power on/off 1/day or more needed.

  • Page 31: Error Rate

    Device Overview 1.8 Error Rate Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media. (1) Unrecoverable read error Read errors that cannot be recovered by maximum read retries of drive without user’s retry and ECC corrections shall occur no more than 10 times when reading...

  • Page 32: Chapter 2 Device Configuration

    CHAPTER 2 Device Configuration Device Configuration System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate. C141-E104-03EN...

  • Page 33: Figure 2.1 Disk Drive Outerview (the Mhl Series And Mhm Series)

    Device Configuration 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors, actuators, and a circulating air filter. MHL Series MHM Series Figure 2.1 Disk drive outerview...

  • Page 34: Figure 2.2 Configuration Of Disk Media Heads

    2.1 Device Configuration Head Head Head Head MHL2300AT MHM2200AT MHM2150AT MHM2100AT (Either of head 0 or head 3 is mounted.) Figure 2.2 Configuration of disk media heads (3) Spindle motor The disks are rotated by a direct drive Hall-less DC motor. (4) Actuator The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and generates very little heat.

  • Page 35: Figure 2.3 1 Drive System Configuration

    Device Configuration 2.2 System Configuration 2.2.1 ATA interface Figures 2.3 and 2.4 show the ATA interface system configuration. The drive has a 44pin PC AT interface connector and supports PIO mode 4 transfer at 16.6 MB/s, Multiword DMA mode 2 transfer at 16.6 MB/s and also U-DMA mode 4 transfer at 66.6 MB/s.

  • Page 36

    2.2 System Configuration IMPORTANT HA (host adaptor) consists of address decoder, driver, and receiver. ATA is an abbreviation of “AT attachment”. The disk drive is conformed to the ATA-4 interface. At high speed data transfer (PIO mode 3, mode 4, or DMA mode 2 U-DMA mode 4), occurrence of ringing or crosstalk of the signal lines (AT bus) between the HA and the disk drive may be a great cause of the obstruction of system reliability.

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  • Page 38

    CHAPTER 3 Installation Conditions Dimensions Mounting Cable Connections Jumper Settings This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives. C141-E104-03EN...

  • Page 39

    Installation Conditions 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. Figure 3.1 Dimensions (MHL series) (1/2) C141-E104-03EN...

  • Page 40

    3.1 Dimensions Figure 3.1 Dimensions (MHM series) (2/2) C141-E104-03EN...

  • Page 41: Figure 3.2 Orientation (sample: Mhl2300at)

    Installation Conditions 3.2 Mounting (1) Orientation Figure 3.2 illustrates the allowable orientations for the disk drive. gravity (b) Horizontal –1 (a) Horizontal –1 gravity (c) Vertical –1 (d) Vertical –2 gravity (e) Vertical –3 (f) Vertical –4 Figure 3.2 Orientation (Sample: MHL2300AT) C141-E104-03EN...

  • Page 42: Figure 3.3 Mounting Frame Structure

    3.2 Mounting (2) Frame The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to SG. IMPORTANT Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3. The tightening torque must be 0.49N·m(5kgf·cm).

  • Page 43: Figure 3.4 Location Of Breather

    Installation Conditions IMPORTANT Because of breather hole mounted to the HDD, do not allow this to close during mounting. Locating of breather hole is shown as Figure 3.4 in both MHL series and MHM series. For breather hole of Figure 3.4, at least, do not allow its around φ3 to block.

  • Page 44: Figure 3.5 Surface Temperature Measurement Points

    3.2 Mounting (4) Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. The ambient temperature must satisfy the temperature conditions described in Section 1.4, and the airflow must be considered to prevent the DE surface temperature from exceeding 60°C.

  • Page 45: Figure 3.6 Service Area (sample: Mhl2300at)

    Installation Conditions (5) Service area Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. Mounting screw hole Cable connection Mounting screw hole Figure 3.6 Service area (Sample: MHL2300AT) CAUTION Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers.

  • Page 46: Figure 3.7 Handling Cautions

    3.2 Mounting - General notes ESD mat Wrist strap Shock absorbing mat Use the Wrist strap. Place the shock absorbing mat on the operation table, and place ESD mat on it. Do not hit HDD each other. Do not stack when carrying. Do not place HDD vertically Do not drop.

  • Page 47: Figure 3.8 Connector Locations (sample: Mhl2300at)

    Installation Conditions 3.3 Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.8 shows the locations of these connectors and terminals. Connector, setting pins Figure 3.8 Connector locations (Sample: MHL2300AT) 3-10 C141-E104-03EN...

  • Page 48: Figure 3.9 Cable Connections

    3.3 Cable Connections 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable connector specifications Name Model Manufacturer ATA interface and power Cable socket 89361-144 BERG supply cable (44-pin type) (44-pin type) IMPORTANT For the host interface cable, use a ribbon cable.

  • Page 49: Figure 3.10 Power Supply Connector Pins (cn1)

    Installation Conditions 3.3.4 Power supply connector (CN1) Figure 3.10 shows the pin assignment of the power supply connector (CN1). Figure 3.10 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.11 shows the location of the jumpers to select drive configuration and functions.

  • Page 50: Figure 3.12 Factory Default Setting

    3.4 Jumper Settings 3.4.2 Factory default setting Figure 3.12 shows the default setting position at the factory. Open Figure 3.12 Factory default setting 3.4.3 Master drive-slave drive setting Master drive (disk drive #0) or slave drive (disk drive #1) is selected. Open Short Open...

  • Page 51: Figure 3.14 Csel Setting

    Installation Conditions 3.4.4 CSEL setting Figure 3.14 shows the cable select (CSEL) setting. Open Short Note: The CSEL setting is not depended on setting between pins Band D. Figure 3.14 CSEL setting Figure 3.15 and 3.16 show examples of cable selection using unique interface cables.

  • Page 52: Figure 3.16 Example (2) Of Cable Select

    3.4 Jumper Settings drive drive Figure 3.16 Example (2) of Cable Select C141-E104-03EN 3-15...

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  • Page 54

    CHAPTER 4 Theory of Device Operation Outline Subassemblies Circuit Configuration Power-on Sequence Self-calibration Read/write Circuit Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.

  • Page 55

    Theory of Device Operation 4.1 Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method. 4.2 Subassemblies The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).

  • Page 56: Air Filter

    4.2 Subassemblies Head Head Head Head MHL2300AT MHM2200AT MHM2150AT MHK2100AT (Either of head 0 or head 3 is mounted.) Figure 4.1 Head structure 4.2.3 Spindle The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 4,200 rpm ±1%.

  • Page 57: Circuit Configuration

    Theory of Device Operation 4.3 Circuit Configuration Figure 4.2 shows the power supply configuration of the disk drive, and Figure 4.3 shows the disk drive circuit configuration. (1) Read/write circuit The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC).

  • Page 58: Figure 4.2 Power Supply Configuration

    4.3 Circuit Configuration HDIC FROM - 3V 3.3V SDRAM Figure 4.2 Power Supply Configuration C141-E104-03EN...

  • Page 59: Figure 4.3 Circuit Configuration

    Theory of Device Operation Printed Circuit Board FROM Program Memory 16 bit Local Bus Host Interface (Hard Disk (Micro Controller) Processor Unit) Control Control Signal Signal Read Write Data HDIC Data 16 bit Buffer Control Signal SDRAM Data Read Motor Servo Buffer Channel...

  • Page 60: Power-on Sequence

    4.3 Circuit Configuration 4.4 Power-on Sequence Figure 4.4 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.

  • Page 61: Figure 4.4 Power-on Operation Sequence

    Theory of Device Operation Power-on Start Self-diagnosis 1 - MPU bus test - Internal register write/read test - Work RAM write/read test The spindle motor starts. Self-diagnosis 2 - Data buffer write/read Initial on-track and read test out of system information Confirming spindle motor Execute self-calibration speed...

  • Page 62: Execution Timing Of Self-calibration

    4.5 Self-calibration The forces are compensated by adding the measured value to the specified current value to the power amplifier. This makes the stable servo control. To compensate torque varying by the cylinder, the disk is divided into 23 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration.

  • Page 63: Command Processing During Self-calibration

    Theory of Device Operation Table 4.1 Self-calibration execution timechart Time elapsed Time elapsed (accumulated) At power-on Initial calibration About 5 minutes About 5 minutes About 5 minutes About 10 minutes About 10 minutes About 20 minutes About 10 minutes About 30 minutes About 15 minutes About 45 minutes About 15 minutes...

  • Page 64: Write Circuit

    4.6 Read/write Circuit 4.6.2 Write circuit The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent to the encoder circuit in the RDC. The NRZ write data is converted from 16-bit data to 17-bit data by the encoder circuit then sent to the HDIC, and the data is written onto the media.

  • Page 65: Figure 4.5 Read/write Circuit Block Diagram

    Theory of Device Operation HDIC WDX/WDY RDX/RDY Serial I/O Write Amplifier PreCompen- sation Registers Digital Programmable Filter Flash Digitizer ServoPulse MEEPR Detector Viterbi Detect 16/17 ENDEC Position A/B/C/D (to reg) WTGATE REFCLK RDGATE DATA RWCLK SRV_CLK SRV_OUT[1:0] [7:0] Figure 4.5 Read/write circuit block diagram 4-12 C141-E104-03EN...

  • Page 66: Read Circuit

    4.6 Read/write Circuit 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This clock signal is converted into the NRZ data by the 16/17 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

  • Page 67: Digital Pll Circuit

    Theory of Device Operation (3) Flash digitizer circuit This circuit is 10-tap sampled analog transversal filter circuit that cosine-equalizes the head read signal to the Modified Extended Partial Response (MEEPR) waveform. (4) Viterbi detection circuit The sample hold waveform output from the flash digitizer circuit is sent to the Viterbi detection circuit.

  • Page 68: Servo Control

    4.6 Read/write Circuit 4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand.

  • Page 69

    Theory of Device Operation The major internal operations are listed below. Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied. b. Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area. The logical initial cylinder is at the outermost circumference (cylinder 0).

  • Page 70

    4.7 Servo Control (2) Servo burst capture circuit The servo burst capture circuit reproduces signals (position signals) that indicate the head position from the servo data on the data surface. SERVO A, SERVO B, SERVO C and SERVO D burst signals shown in Figure 4.9 followed the servo mark, cylinder gray and index information are output from the servo area on the data surface via the data head.

  • Page 71: Data-surface Servo Format

    Theory of Device Operation 4.7.2 Data-surface servo format Figure 4.8 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.8 are described below. (1) Inner guard band The head is in contact with the disk in this space when the spindle starts turning or stops, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.

  • Page 72: Figure 4.8 Physical Sector Servo Configuration On Disk Surface

    4.7 Servo Control Servo frame (66 servo frames per revolution) Data area expand CYLn CYLn – 1 (n: even number) CYLn + 1 Diameter direction W/R Recovery W/R Recovery W/R Recovery Servo Mark Servo Mark Servo Mark Gray Code Gray Code Gray Code Erase Servo A...

  • Page 73: Figure 4.9 Servo Frame Format

    Theory of Device Operation 4.7.3 Servo frame format As the servo information, the IDD uses the two-phase servo generated from the gray code and servo A to D. This servo information is used for positioning operation of radius direction and position detection of circumstance direction. The servo frame consists of 6 blocks;...

  • Page 74: Actuator Motor Control

    4.7 Servo Control (1) Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. (2) Servo mark This area generates a timing for demodulating the gray code and position- demodulating the servo A to D by detecting the servo mark. (3) Gray code (including index bit) This area is used as cylinder address.

  • Page 75: Spindle Motor Control

    (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control; start mode, acceleration mode, and stable rotation mode.

  • Page 76

    4.7 Servo Control d) During phase switching, the spindle motor starts rotating in low speed, and generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection. e) The MPU is waiting for a PHASE signal.

  • Page 77

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  • Page 78: Chapter 5 Interface

    CHAPTER 5 Interface Physical Interface Logical Interface Host Commands Command Protocol Ultra DMA Feature Set Timing This chapter gives details about the interface, and the interface commands and timings. C141-E104-03EN...

  • Page 79: Physical Interface

    Interface 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. Host DATA 0-15: DATA BUS DMACK-: DMA ACKNOWLEDGE DMARQ: DMA REQUEST INTRO: INTERRUPT REQUEST DIOW-: I/O WRITE STOP: STOP DURING ULTRA DMA DATA BURSTS DIOR-:I/O READ HDMARDY:DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE:DATA STROBE DURING ULTRA DMA DATA OUT BURST PDIAG-: PASSED DIAGNOSTICS CBLID-: CABLE TYPE IDENTIFIER...

  • Page 80: Signal Assignment On The Connector

    5.1 Physical Interface 5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal Pin No. Signal MSTR MSTR/ENCSEL unused ENCSEL (KEY) (KEY) RESET– DATA7 DATA8 DATA6...

  • Page 81

    Interface [signal] [I/O] [Description] ENCSEL This signal is used to set master/slave using the CSEL signal (pin 28). Pins B and D Open: Sets master/slave using the CSEL signal is disabled. Short: Sets master/slave using the CSEL signal is enabled. MSTR- MSTR, I, Master/slave setting Pin A, B, C, D open: Master setting...

  • Page 82

    5.1 Physical Interface [signal] [I/O] [Description] CS0- Chip select signal decoded from the host address bus. This signal is used by the host to select the command block registers. CS1- Chip select signal decoded from the host address bus. This signal is used by the host to select the control block registers.

  • Page 83: Logical Interface

    Interface [signal] [I/O] [Description] DMARQ This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system (at reading) or from the host system (at writing). The direction of data transfer is controlled by the DIOR and DIOW signals.

  • Page 84: I/o Registers

    5.2 Logical Interface 5.2.1 I/O registers Communication between the host system and the device is done through input- output (I/O) registers of the device. These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to DA2 from the host system. Table 5.2. shows the coding address and the function of I/O registers.

  • Page 85: Command Block Registers

    Interface 5.2.2 Command block registers (1) Data register (X’1F0’) The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or DMA mode. (2) Error register (X’1F1’) The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.

  • Page 86

    5.2 Logical Interface [Diagnostic code] X’01’: No Error Detected. X’02’: HDC Register Compare Error X’03’: Data Buffer Compare Error. X’05’: ROM Sum Check Error. X’80’: Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration.

  • Page 87

    Interface (6) Cylinder Low register (X’1F4’) The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indicates LBA bits 15 to 8.

  • Page 88

    5.2 Logical Interface (9) Status register (X’1F7’) The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid.

  • Page 89

    Interface - Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault (write fault) condition has been detected. If a write fault is detected during command execution, this bit is latched and retained until the device accepts the next command or reset.

  • Page 90: Control Block Registers

    5.3 Host Commands 5.2.3 Control block registers (1) Alternate Status register (X’3F6’) The Alternate Status register contains the same information as the Status register of the command block register. The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.

  • Page 91: Command Code And Parameters

    Interface When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the host system writes to the command register, the correct device operation is not guaranteed. 5.3.1 Command code and parameters Table 5.3 lists the supported commands, command code and the registers that needed parameters are written.

  • Page 92

    5.3 Host Commands Table 5.3 Command code and parameters (2 of 2) Command code (Bit) Parameters used Command name FR SC SN CY DH IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE SMART SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY SET PASSWORD...

  • Page 93: Command Descriptions

    Interface Necessary to set parameters under the LBA mode. Not necessary to set parameters (The parameter is ignored if it is set.) May set parameters The device parameter is valid, and the head parameter is ignored. The command is addressed to the master device, but both the master device and the slave device execute it.

  • Page 94

    5.3 Host Commands CM: Command register FR: Features register DH: Device/Head register ST: Status register CH: Cylinder High register ER: Error register CL: Cylinder Low register L: LBA (logical block address) setting bit SN: Sector Number register DV: Device address. bit SC: Sector Count register x, xx: Do not care (no necessary to set) Note:...

  • Page 95

    Interface Command block registers contain the cylinder, the head, and the sector addresses of the sector (in the CHS mode) or the logical block address (in the LBA mode) where the error occurred, and remaining number of sectors of which data was not transferred.

  • Page 96

    5.3 Host Commands The implementation of the READ MULTIPLE command is identical to that of the READ SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE MODE command are transferred without intervening interrupts. In the READ MULTIPLE command operation, the DRQ bit of the Status register is set only at the start of the data block, and is not set on each sector.

  • Page 97: Figure 5.2 Execution Example Of Read Multiple Command

    Interface Figure 5.2 Execution example of READ MULTIPLE command At command issuance (I/O registers setting contents) (CM) (DH) Start head No. /LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR)

  • Page 98

    5.3 Host Commands (3) READ DMA (X’C8’ or X’C9’) This command operates similarly to the READ SECTOR(S) command except for following events. The data transfer starts at the timing of DMARQ signal assertion. • The device controls the assertion or negation timing of the DMARQ signal. •...

  • Page 99

    Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. /LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)

  • Page 100

    5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) Start head No. /LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read) (ST)

  • Page 101

    Interface If an error occurs during multiple sector write operation, the write operation is terminated at the sector where the error occurred. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred. Then the host can read the command block registers to determine what error has occurred and on which sector the error has occurred.

  • Page 102

    5.3 Host Commands (6) WRITE MULTIPLE (X’C5’) This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command.

  • Page 103

    Interface At command issuance (I/O registers setting contents) (CM) (DH) Start head No. /LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read) (ST)

  • Page 104

    5.3 Host Commands A host system can select the following transfer mode using the SET FEATURES command. Multiword DMA transfer mode 0 to 2 • Ultra DMA transfer mode 0 to 4 • At command issuance (I/O registers setting contents) (CM) (DH) Start head No.

  • Page 105

    Interface At command issuance (I/O registers setting contents) (CM) (DH) Start head No. /LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read) (ST)

  • Page 106

    5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Note: Also executable in LBA mode. (10) SEEK (X’7x’, x : X’0’...

  • Page 107

    Interface At command issuance (I/O registers setting contents) (CM) (DH) Head No. /LBA [MSB] (CH) Cylinder No. [MSB] / LBA (CL) Cylinder No. [LSB] / LBA (SN) Sector No. / LBA [LSB] (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH)

  • Page 108

    5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) Max. head No. (CH) (CL) (SN) (SC) Number of sectors/track (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) Max. head No. (CH) (CL) (SN) (SC)

  • Page 109

    Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Table 5.4 Information to be read by IDENTIFY DEVICE command (1 of 8) Word Value Description...

  • Page 110

    5.3 Host Commands Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 8) Word Value Description 23-26 – Firmware revision (ASCII code, 8 characters, left) 27-46 Set by a device Model name (ASCII code, 40 characters, left) X’8010’...

  • Page 111

    Interface Table 5.4 Information to be read by IDENTIFY DEVICE command (3 of 8) Word Value Description Valid of command sets/function *12 Valid of command sets/function *13 X’4000’ Default of command sets/function X’xx1F’ Ultra DMA transfer mode *14 Set by a device Security Erase Unit execution time (Unit: 2 min.) X’0000’...

  • Page 112

    5.3 Host Commands Table 5.4 Information to be read by IDENTIFY DEVICE command (4 of 8) Bit 13: Standby timer value. Factory default is 0. Bit 12: Reserved Bit 11: IORDY support 1=Supported Bit 10: IORDY inhibition 0=Disable inhibition Bit 9-0: Undefined Bit 9, 8: Always 1...

  • Page 113

    Interface Table 5.4 Information to be read by IDENTIFY DEVICE command (5 of 8) Bit 1 = 1 Mode 4 Bit 0 = 1 Mode 3 *9 WORD 80 Bit 15-6: Reserved Bit 5: ATA/ATAPI-5 supported = 1 Bit 4: ATA/ATAPI-4 supported = 1 Bit 3: ATA-3 supported = 1...

  • Page 114

    5.3 Host Commands Table 5.4 Information to be read by IDENTIFY DEVICE command (6 of 8) Bit 5: '1' = Supports the Power-Up In Standby set. Bit 4: '1' = Supports the Removable Media Status Notification feature set. Bit 3: '1' = Supports the Advanced Power Management feature set.

  • Page 115

    Interface Table 5.4 Information to be read by IDENTIFY DEVICE command (7 of 8) Bits 2-0: Same definition as WORD 83. *14 WORD 88 Bit 15-8: Currently used Ultra DMA transfer mode Bit 7-0: Supportable Ultra DMA transfer mode Bit 4 = '1': Mode 4 Bit 3 = '1': Mode 3 Bit 2 = '1': Mode 2 Bit 1 = '1': Mode 1...

  • Page 116

    5.3 Host Commands Table 5.4 Information to be read by IDENTIFY DEVICE command (8 of 8) '00' = Reserved '01' = Using a jumper. '10' = Using the CSEL signal. '11' = Other method. Bit 0: Reserved *16 WORD 128 Bit 15-9: Reserved Bit 8:...

  • Page 117

    Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (14) SET FEATURES (X’EF’) The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed. For the transfer mode (Feature register = 03), detail setting can be done using the Sector Count register.

  • Page 118

    5.3 Host Commands Table 5.5 Features register values and settable modes Features Drive operation mode Register X’02’ Enables the write cache function. X’03’ Transfer mode depends on the contents of the Sector Count register. (Details are given later.) X’05’ Enables the advanced power management function. X’55’...

  • Page 119

    Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) xx or transfer mode (FR) [See Table 5.5] At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information The host sets X’03’...

  • Page 120

    5.3 Host Commands Multiword DMA transfer mode X 00100 000 (X’20’: Mode 0) 00100 001 (X’21’: Mode 1) 00100 010 (X’22’: Mode 2) Ultra DMA transfer mode X 01000 000 (X’40’: Mode 0) 01000 001 (X’41’: Mode 1) 01000 010 (X’42’: Mode 2) 01000 011 (X’43’: Mode 3) 01000 100 (X’44’: Mode 4) The host writes the Sector Count register with the desired power management...

  • Page 121

    Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) Sector count/block (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) Sector count/block (ER) Error information After power-on or after hardware reset, the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode.

  • Page 122

    5.3 Host Commands Word 47 Bit 7-0 = 10: Maximum number of sectors that can be transferred per interrupt by the READ MULTIPLE and WRITE MULTIPLE commands. The READ MULTIPLE and WRITE MULTIPLE commands are Word 59 = 0000: disabled. The READ MULTIPLE and WRITE MULTIPLE commands are = 01xx: enabled.

  • Page 123

    Interface After power on and the occurrence of a hard reset, the host can issue this command only once when VV bit = 1. If this command with VV bit = 1 is issued twice or more, any command following the first time will result in an Aborted Command error.

  • Page 124

    5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Password information Words Contents Reserved 1 to 16...

  • Page 125

    Interface If the device is in the Set Max Locked or Set Max Freeze Locked state: 51h, 04h: ABORTED command At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH)

  • Page 126

    5.3 Host Commands If this command is accepted in the Set Max Unlocked state, the device terminates normally. The READ NATIVE MAX ADDRESS command is not executed just before this command. The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed.

  • Page 127

    Interface The READ NATIVE MAX ADDRESS command is not executed just before this command. The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed. At command issuance (I/O registers setting contents) (CM) (DH) (CH)

  • Page 128

    5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) Max head/LBA [MSB] (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max.

  • Page 129

    Interface When device 1 is not present: The device 0 posts only the results of its own self-diagnosis. • The device 0 clears the BSY bit of the Status register, and generates an • interrupt. Table 5.6 lists the diagnostic code written in the Error register which is 8-bit code. If the device 1 fails the self-diagnosis, the device 0 “ORs”...

  • Page 130

    5.3 Host Commands At command completion (I/O registers contents to be read) (ST) Status information (DH) Head No. /LBA [MSB] (CH) (CL) (SN) (*1) (SC) (ER) Diagnostic code This register indicates X’00’ in the LBA mode. (19) READ LONG (X’22’ or X’23’) This command operates similarly to the READ SECTOR(S) command except that the device transfers the data in the requested sector and the ECC bytes to the host system.

  • Page 131

    Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) Head No. /LBA [MSB] (CH) Cylinder No. [MSB] / LBA (CL) Cylinder No. [LSB] / LBA (SN) Sector No. / LBA [LSB] (SC) 00 (*1) (ER) Error information If the command is terminated due to an error, this register indicates 01.

  • Page 132

    5.3 Host Commands At command completion (I/O registers contents to be read) (ST) Status information (DH) Head No. /LBA [MSB] (CH) Cylinder No. [MSB] / LBA (CL) Cylinder No. [LSB] / LBA (SN) Sector No. / LBA [LSB] (SC) 00 (*1) (ER) Error information If the command is terminated due to an error, this register indicates 01.

  • Page 133

    Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (22) WRITE BUFFER (X’E8’) The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command.

  • Page 134

    5.3 Host Commands At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (23) IDLE (X’97’ or X’E3’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode.

  • Page 135

    Interface attention: The automatic power-down is executed if no command is coming for 30 min. At command issuance (I/O registers setting contents) (CM) X’97’ or X’E3’ (DH) (CH) (CL) (SN) (SC) Period of timer (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH)

  • Page 136

    5.3 Host Commands At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (25) STANDBY (X’96’ or X’E2’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode.

  • Page 137

    Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (26) STANDBY IMMEDIATE (X’94’ or X’E0’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode.

  • Page 138

    5.3 Host Commands (27) SLEEP (X’99’ or X’E6’) This command is the only way to make the device enter the sleep mode. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device then clears the BSY bit and generates an interrupt.

  • Page 139

    Interface (28) CHECK POWER MODE (X’98’ or X’E5’) The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers. The device sets the BSY bit and sets the following register value.

  • Page 140

    5.3 Host Commands (29) SMART (X’B0) This command performs operations for device failure predictions according to a subcommand specified in the FR register. If the value specified in the FR register is supported, the Aborted Command error is posted. It is necessary for the host to set the keys (CL = 4Fh and CH = C2h) in the CL and CH registers prior to issuing this command.

  • Page 141

    Interface Table 5.7 Features Register values (subcommands) and functions (1 of 3) Features Resister Function X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host.

  • Page 142

    5.3 Host Commands Table 5.7 Features Register values (subcommands) and functions (2 of 3) Features Resister Function X’D5’ SMART Read Log Sector: A device which receives this sub-command asserts the BSY bit, then reads the log sector specified in the SN register. Next, it clears the BSY bit and transmits the log sector to the host computer.

  • Page 143

    Interface Table 5.7 Features Register values (subcommands) and functions (3 of 3) Features Resister Function X’DA’ SMART Return Status: When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values.

  • Page 144

    5.3 Host Commands At command completion (I-O registers setting contents) (ST) Status information (DH) (CH) Key-failure prediction status (C2h-2Ch) (CL) Key-failure prediction status (4Fh-F4h) (SN) (SC) (ER) Error information The attribute value information is 512-byte data; the format of this data is shown below.

  • Page 145

    Interface Table 5.8 Format of device attribute value data Byte Item Data format version number Attribute 1 Attribute ID Status flag Current attribute value Attribute value for worst case so far 07 to 0C Raw attribute value Reserved 0E to 169 Attribute 2 to (The format of each attribute value is the same attribute 30...

  • Page 146

    5.3 Host Commands Data format version number • The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds. The data format version numbers of the device attribute values and insurance failure thresholds are the same.

  • Page 147

    Interface Current attribute value • The current attribute value is the normalized raw attribute data. The value varies between 01h and 64h. The closer the value gets to 01h, the higher the possibility of a failure. The device compares the attribute values with thresholds.

  • Page 148

    5.3 Host Commands Self-test Meaning execution status Self-test has been completed normally or has not been executed. Self-test has been stopped by the host computer. Self-test has been suspended by hard or soft reset. Self-test has been aborted by a fatal error. Self-test has been completed abnormally by an unknown meaning.

  • Page 149

    Interface Check sum • Two’s complement of the lower byte, obtained by adding 511-byte data one byte at a time from the beginning. Insurance failure threshold • The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure.

  • Page 150

    5.3 Host Commands Table 5.10 SMART error log data format (2/2) Byte Item Error log 1 Error data Device/Head register Status register 46 to 58 Vendor unique Status 5A, 5B Total power on time [hour] 5C to 1C3 Error log 2 (The format of each error log is the same as Byte 02 to 5B.) Error log 5...

  • Page 151

    Interface Status Meaning Unclear status Sleep status Standby status Active status or idle status (BSY bit = 0) Off-line data collection being executed 5 to F Reserved The host computer can issue the SMART Execute Off-line Immediate sub- command (FR Register = D4h) and cause the device to execute a self test. When the self test is completed, the device saves the SMART self test log to the disk medium.

  • Page 152

    5.3 Host Commands (30) SECURITY DISABLE PASSWORD (F6h) This command invalidates the user password already set and releases the lock function. The host transfers the 512-byte data shown in Table 5.12 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same.

  • Page 153

    Interface Table 5.12 Contents of security password Word Contents Control word Bit 0: Identifier 0 = Compares the user passwords. 1 = Compares the master passwords. Bits 1 to 15: Reserved 1 to 16 Password (32 bytes) 17 to 255 Reserved At command issuance (I-O register contents)) (CM)

  • Page 154

    5.3 Host Commands At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (32) SECURITY ERASE UNIT (F4h) This command erases all user data. This command also invalidates the user password and releases the lock function.

  • Page 155

    Interface At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (33) SECURITY FREEZE LOCK (F5h) This command puts the device into FROZEN MODE. The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE.

  • Page 156

    5.3 Host Commands • READ DMA • WRITE DMA • SECURITY DISABLE PASSWORD • READ LONG • WRITE LONG • SECURITY FREEZE LOCK • READ MULTIPLE • WRITE MULTIPLE • SECURITY SET PASSWORD • READ SECTORS • WRITE SECTORS • WRITE VERIFY At command issuance (I-O register contents) (CM) (DH)

  • Page 157

    Interface (34) SECURITY SET PASSWORD (F1h) This command enables a user password or master password to be set. The host transfers the 512-byte data shown in Table 5.13 to the device. The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data.

  • Page 158

    5.3 Host Commands At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (35) SECURITY UNLOCK This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 5.12 to the device.

  • Page 159

    Interface LOCKED MODE canceled (in UNLOCK MODE) has no affect on the UNLOCK counter. Issuing this command in FROZEN MODE returns the Aborted Command error. At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH)

  • Page 160: Error Posting

    5.3 Host Commands At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information 5.3.3 Error posting Table 5.15 lists the defined errors that are valid for each command. Table 5.15 Command code and parameters (1 of 2) Command name Error register (X’1F1’)

  • Page 161

    Interface Table 5.15 Command code and parameters (2 of 2) Command name Error register (X’1F1’) Status register (X’1F7’) ICRC INDF ABRT TK0NF DRDY RECALIBRATE SEEK INITIALIZE DEVICE PARAMETERS IDENTIFY DEVICE IDENTIFY DEVICE DMA SET FEATURES SET MULTIPLE MODE SET MAX ADDRESS READ NATIVE MAX ADDRESS EXECUTE DEVICE DIAGNOSTIC READ LONG...

  • Page 162: Command Protocol

    5.4 Command Protocol 5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0.

  • Page 163: Figure 5.3 Read Sector(s) Command Protocol

    Interface words, the host should receive the relevant sector of data (512 bytes of uninsured dummy data) or release the DRQ status by resetting. Figure 5.3 shows an example of READ SECTOR(S) command protocol, and Figure 5.4 shows an example protocol for command abort. Figure 5.3 Read Sector(s) command protocol IMPORTANT For transfer of a sector of data, the host needs to read Status register...

  • Page 164: Data Transferring Commands From Host To Device

    5.4 Command Protocol Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading. If the timing to read the Status register does not meet above condition, normal data transfer operation is not guaranteed.

  • Page 165

    Interface a) The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head registers. b) The host writes a command code in the Command register. The drive sets the BSY bit of the Status register. c) When the device is ready to receive the data of the first sector, the device sets DRQ bit and clears BSY bit.

  • Page 166: Commands Without Data Transfer

    5.4 Command Protocol IMPORTANT For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 50 µs after the completion of the sector data transfer.

  • Page 167: Other Commands

    Interface Figure 5.6 Protocol for the command execution without data transfer 5.4.4 Other commands READ MULTIPLE • SLEEP • WRITE MULTIPLE • See the description of each command. 5.4.5 DMA data transfer commands READ DMA • WRITE DMA • Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance.

  • Page 168

    5.5 Ultra DMA Feature Set When the command execution is completed, the device clears both BSY and DRQ bits and asserts the INTRQ signal. Then, the host reads the Status register. g) The host resets the DMA channel. Figure 5.7 shows the correct DMA data transfer protocol. Figure 5.7 Normal DMA data transfer C141-E104-03EN 5-91...

  • Page 169: Ultra Dma Feature Set

    Interface 5.5 Ultra DMA Feature Set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only.

  • Page 170: Phases Of Operation

    5.5 Ultra DMA Feature Set Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the host sends the its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command.

  • Page 171: Data Transfer Phase

    Interface g) Ultra DMA data in burst The device should not invert the state of this signal in the period from the moment of STOP signal negation or HDMARDY-signal assertion to the moment of inversion of the first STROBE signal. 5.5.2.2 Data transfer phase a) The Data transfer phase is defined as the period from The Ultra DMA burst initiation phase to Ultra DMA burst termination phase.

  • Page 172: Ultra Dma Data In Commands

    5.5 Ultra DMA Feature Set Once the transmitting side has outputted the ending request, the output state of STROBE signal should not be changed unless the receiving side has confirmed it. Then, if the STROBE signal is not in asserted state, The transmitting side should assert the STROBE signal.

  • Page 173

    Interface host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device (i.e., after the first data word has been received). 10) The device shall drive DD (15:0) no sooner than t after the host has asserted DMACK-, negated STOP, and asserted HDMARDY-.

  • Page 174

    5.5 Ultra DMA Feature Set b) Host pausing an Ultra DMA data in burst 1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred. 2) The host shall pause an Ultra DMA burst by negating HDMARDY-. 3) The device shall stop generating DSTROBE edges within t of the host negating HDMARDY-.

  • Page 175

    Interface 7) If DSTROBE is negated, the device shall assert DSTROBE within t after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra DMA burst is terminated.

  • Page 176

    5.5 Ultra DMA Feature Set 5) The host shall assert STOP no sooner than t after negating HDMARDY-. The host shall not negate STOP again until after the Ultra DMA burst is terminated. 6) The device shall negate DMARQ within t after the host has asserted STOP.

  • Page 177: Ultra Dma Data Out Commands

    Interface 5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.7 and 5.6.4.2 for specific timing requirements): 1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.

  • Page 178

    5.5 Ultra DMA Feature Set HSTROBE edge no more frequently than t for the selected Ultra DMA Mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2 t for the selected Ultra DMA mode. 3) The host shall not change the state of DD (15:0) until at least t after generating an HSTROBE edge to latch the data.

  • Page 179

    Interface 5.5.4.4 Terminating an Ultra DMA data out burst a) Host terminating an Ultra DMA data out burst The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.10 and 5.6.4.2 for specific timing requirements): 1) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.

  • Page 180

    5.5 Ultra DMA Feature Set b) Device terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.11 and 5.6.4.2 for specific timing requirements): 1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.

  • Page 181

    Interface 13) The host shall neither negate STOP nor HSTROBE until at least t after negating DMACK-. 14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t after negating DMACK. 5.5.5 Ultra DMA CRC rules The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.

  • Page 182

    5.5 Ultra DMA Feature Set Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynomial where DD0 is shifted in first and DD15 is shifted in last.

  • Page 183: Series Termination Required For Ultra Dma

    Interface 5.5.6 Series termination required for Ultra DMA Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA Modes. The following table describes recommended values for series termination at the host and the device. Table 5.17 Recommended series termination for Ultra DMA Signal Host Termination...

  • Page 184: Pio Data Transfer

    5.6 Timing 5.6 Timing 5.6.1 PIO data transfer Figure 5.10 shows of the data transfer timing between the device and the host system. C141-E104-03EN 5-107...

  • Page 185

    Interface Figure 5.10 Data transfer timing 5-108 C141-E104-03EN...

  • Page 186: Multiword Dma Data Transfer

    5.6 Timing 5.6.2 Multiword DMA data transfer Figure 5.11 shows the multiword DMA data transfer timing between the device and the host system. Delay time from DIOR-/DIOW- assertion to DMARQ negation Figure 5.11 Multiword DMA data transfer timing (mode 2) C141-E104-03EN 5-109...

  • Page 187: Transfer Of Ultra Dma Data

    Interface 5.6.3 Transfer of Ultra DMA data Figures 5.12 to 5.21 define the timings concerning every phase for the Ultra DMA Burst. Table 5.18 includes the timing for each Ultra DMA mode. 5.6.3.1 Starting of Ultra DMA data In Burst The timing for each Ultra DMA mode is included in 5.6.3.2.

  • Page 188: Ultra Dma Data Burst Timing Requirements

    5.6 Timing 5.6.3.2 Ultra DMA data burst timing requirements Table 5.18 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 COMMENT (in ns) (in ns) (in ns) (in ns) (in ns) MAX (see Notes 1 and 2) Typical sustained average two cycle...

  • Page 189

    Interface Table 5.18 Ultra DMA data burst timing requirements (2 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 COMMENT (in ns) (in ns) (in ns) (in ns) (in ns) MAX (see Notes 1 and 2) Minimum time before driving ZIORDY IORDY...

  • Page 190: Sustained Ultra Dma Data In Burst

    5.6 Timing 5.6.3.3 Sustained Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. 2CYC 2CYC DSTROBE at device DD(15:0) at device DSTROBE at host DD(15:0) at host Note: DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.

  • Page 191

    Interface 5.6.3.4 Host pausing an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) DSTROBE (device) DD(15:0) (device) Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t after HDMARDY- is negated.

  • Page 192

    5.6 Timing 5.6.3.5 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) IORDYZ DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, HDMARDY- and DSTROBE signal...

  • Page 193

    Interface 5.6.3.6 Host terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) IORDYZ DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0, CS1 Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are...

  • Page 194

    5.6 Timing 5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) ZIORDY DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal...

  • Page 195

    Interface 5.6.3.8 Sustained Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. 2CYC HSTROBE 2CYC at host DD(15:0) at host HSTROBE at device DD(15:0) at device Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.

  • Page 196

    5.6 Timing 5.6.3.9 Device pausing an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t after DDMARDY- is negated.

  • Page 197

    Interface 5.6.3.10 Host terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) IORDYZ DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal...

  • Page 198

    5.6 Timing 5.6.3.11 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) IORDYZ DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal...

  • Page 199: Power-on And Reset

    Interface 5.6.4 Power-on and reset Figure 5.22 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present Power-on Reset RESET– (2) Master and slave devices are present (2-drives configuration) PDIAG- negation Figure 5.22 Power on Reset Timing 5-122 C141-E104-03EN...

  • Page 200

    CHAPTER 6 Operations 6.1 Device Response to the Reset 6.2 Address Translation 6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache 6.6 Write Cache C141-E104-03EN...

  • Page 201: Device Response To The Reset

    Operations 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. 6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1).

  • Page 202: Figure 6.1 Response To Power-on

    6.1 Device Response to the Reset Power on Master device Power On Reset- Status Reg. BSY bit Max. 31 sec. Checks DASP- for up to If presence of a slave device is 450 ms. confirmed, PDIAG- is checked for up to 31 seconds. Slave device Power On Reset- BSY bit...

  • Page 203: Response To Hardware Reset

    Operations 6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to the power-on reset. Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to confirm presence of a slave device. The master device recognizes the presence of the slave device when it confirms assertion of the DASP- signal.

  • Page 204: Response To Software Reset

    6.1 Device Response to the Reset 6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 15 seconds to see if the slave device has completed the self-diagnosis successfully.

  • Page 205: Response To Diagnostic Command

    Operations 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self- diagnosis successfully.

  • Page 206: Address Translation

    6.2 Address Translation 6.2 Address Translation When the IDD receives any command which involves access to the disk medium, the IDD always implements the address translation from the logical address (a host-specified address) to the physical address (logical to physical address translation).

  • Page 207: Logical Address

    Operations 6.2.2 Logical address (1) CHS mode Logical address assignment starts from physical cylinder (PC) 0, physical head (PH) 0, and physical sector (PS) 1 and is assigned by calculating the number of sectors per track that is specified by the INITIALIZE DEVICE PARAMETERS command.

  • Page 208: Power Save

    6.3 Power Save (2) LBA mode Logical address assignment in the LBA mode starts from physical cylinder 0, physical head 0, and physical sector 1. If the last sector of a physical track is used, the track is switched and the next LBA is assigned to the initial sector of the subsequent physical track.

  • Page 209

    Operations The drive moves from the Active mode to the idle mode by itself. Regardless of whether the power down is enabled, the device enters the idle mode. The device also enters the idle mode in the same way after power-on sequence is completed.

  • Page 210: Power Commands

    6.4 Defect Management When one of following commands is issued, the command is executed normally and the device is still stayed in the standby mode. Reset (hardware or software) • STANDBY command • STANDBY IMMEDIATE command • INITIALIZE DEVICE PARAMETERS command •...

  • Page 211: Spare Area

    Operations 6.4.1 Spare area Following two types of spare area are provided for every physical head. 1) Spare cylinder for sector slip: used for alternating defective sectors at formatting in shipment (4 cylinders) 2) Spare cylinder for alternative assignment: used for automatic alternative assignment at read error occurrence. (4 cylinders) 6.4.2 Alternating defective sectors The two alternating methods described below are available:...

  • Page 212: Figure 6.8 Alternate Cylinder Assignment

    6.4 Defect Management (2) Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder. This processing is performed when the alternate assignment is specified in the FORMAT TRACK command or when the automatic alternate processing is performed at read error occurrence.

  • Page 213: Data Buffer Configuration

    Operations An unrecoverable write error occurs during write error retry, automatic alternate assignment is performed. 6.5 Read-Ahead Cache After read command which involves read data from the disk medium is completed, the read-ahead cache function reads the subsequent data blocks automatically and stores the data to the data buffer.

  • Page 214

    6.5 Read-Ahead Cache READ SECTOR (S) • READ MULTIPLE • READ DMA • When caching operation is disabled by the SET FEATURES command, no caching operation is performed. (2) Data that are object of caching operation Follow data are object of caching operation. 1) Read-ahead data read from the medium to the data buffer after completion of the command that are object of caching operation.

  • Page 215: Usage Of Read Segment

    Operations − READ MULTIPLE − WRITE SECTOR(S) − WRITE MULTIPLE − WRITE VERIFY SECTOR(S) 3) Caching operation is inhibited by the SET FEATURES command. 4) Issued command is terminated with an error. 5) Soft reset or hard reset occurs, or power is turned off. 6) The device enters the sleep mode.

  • Page 216: Sequential Read

    6.5 Read-Ahead Cache 2) Transfers the requested data that already read to the host system with reading the requested data from the disk media. Stores the read-requested data upto this point Empty area Read-requested data 3) After reading the requested data and transferring the requested data to the host system had been completed, the disk drive stops command execution without performing the read-ahead operation.

  • Page 217

    Operations 1) At receiving the sequential read command, the disk drive sets the DAP and HAP to the start address of the segment and reads the requested data from the load of the segment. Mis-hit data Empty area 2) The disk drive transfers the requested data that is already read to the host system with reading the requested data.

  • Page 218

    6.5 Read-Ahead Cache Sequential hit When the previously executed read command is the sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive transfers the hit data in the buffer to the host system.

  • Page 219: Full Hit (hit All)

    Operations 4) Finally, the cache data in the buffer is as follows. Read-ahead data Start LBA Last LBA Non-sequential command immediately after sequential command When a sequential read command (first read) has been executed, the first read operation should be stopped if a non-sequential read command has been received and then, ten or more of the non-sequential read commands have been received.

  • Page 220: Partially Hit

    6.5 Read-Ahead Cache 3) The cache data for next read command is as follows. Cache data Start LBA Last LBA 6.5.3.4 Partially hit A part of requested data including a lead sector are stored in the data buffer. The disk drive starts the data transfer from the address of the hit data corresponding to the lead sector of the requested data, and reads remaining requested data from the disk media directly.

  • Page 221: Write Cache

    Operations 3) The cache data for next read command is as follows. Cache data Start LBA Last LBA 6.6 Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is physically sequent the data of previous command and random write operation is performed.

  • Page 222

    6.6 Write Cache The drive uses a cache data of the last write command as a read cache data. When a read command is issued to the same address after the write command (cache hit), the read operation to the disk medium is not performed. If an error occurs during the write operation, the device retries the processing.

  • Page 223

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  • Page 224

    Glossary Actuator Head positioning assembly. The actuator consists of a voice coil motor and head arm. If positions the read-write (R-W) head. AT bus A bus between the host CPU and adapter board ATA (AT Attachment) standard The ATA standard is for a PC AT interface regulated to establish compatibility between products manufactured by different vendors.

  • Page 225

    Glossary MTBF Mean time between failures. The MTBF is calculated by dividing the total operation time (total power-on time) by the number of failures in the disk drive during operation. MTTR Mean time to repair. The MTTR is the average time required for a service person to diagnose and repair a faulty drive.

  • Page 226

    Glossary Status The status is a piece of one-byte information posted from the drive to the host when command execution is ended. The status indicates the command termination state. Voice coil motor. The voice coil motor is excited by one or more magnets. In this drive, the VCM is used to position the heads accurately and quickly.

  • Page 227

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  • Page 228: Acronyms And Abbreviations

    Acronyms and Abbreviations Hard disk drive ABRT Aborted command Automatic idle control IDNF ID not found AMNF Address mark not found IRQ14 Interrupt request 14 AT attachment American wire gage Light emitting diode Bad block detected BIOS Basic input-output system Mega-byte MB/S Mega-byte per seconds...

  • Page 229

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  • Page 230

    List any errors or suggestions for improvement. Page Line Contents Please send this form to the address below. We will use your comments in planning future editions. Address: Fujitsu Learning Media Limited 22-7 Minami-Ooi 6-Chome Shinagawa-Ku Tokyo 140-0013 JAPAN Fax: 81-3-5762-8073...

  • Page 231

    MHL2300AT, MHM2200AT, MHM2150AT, MHM2100AT DISK DRIVES C141-E104-03EN PRODUCT MANUAL MHL2300AT, MHM2200AT, MHM2150AT, MHM2100AT DISK DRIVES C141-E104-03EN PRODUCT MANUAL...

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