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Advanced Dynamic Execution
The Pentium III Xeon processor has a 10-stage pipeline. However, the large
number of transistors in each pipeline stage means that the processor is
limited to speeds under 1 GHz, due to latency in the pipeline.
The Xeon Processor MP has a 20-stage pipeline, which can hold up to 126
concurrent instructions in flight and up to 48 reads and 24 writes active in the
pipeline. The lower complexity of each stage also means that future clock
speed increases are possible.
It is important to note, however, that the longer pipeline means that it now
takes more clock cycles to execute the same instruction when compared to
the Pentium III Xeon.
Comparing the Xeon Processor MP with the Pentium III Xeon and current
operating systems (Windows 2000, Linux with 2.4 kernel), good rules of
thumb are:
– 1.5 GHz Xeon Processor MP/512 KB L3
MB L2 Xeon
– 1.6 GHz Xeon Processor MP/1 MB L3
MB L2 Xeon
The next generations of operating systems will likely improve performance of
the MP processor as they take advantage of the NetBurst architecture. These
include Windows .NET and the Linux 2.5/2.6 kernels.
For more information about the features of the Xeon Processor MP, go to:
1.4.2 Intel Xeon Processor DP
The Xeon DP is similar to the Xeon MP and is also based on the Intel NetBurst
micro-architecture. The Xeon DP was designed by Intel to be suitable only in
uniprocessor and two-way SMP processor systems. However, with the use of the
IBM XA-32 chipset, the x440 can have up to four Xeon DP processors installed.
The Xeon DP models of the x440 models use 2.4 GHz processors, part
37L3533.
The key differences between the processors are listed in Table 1-2.
Table 1-2 Differences between the Xeon DP and the Xeon MP
Feature
Maximum CPUs per SMP Expansion Module
Maximum CPUs per x440 node
16
IBM ^ xSeries 440 Planning and Installation Guide
5-20% faster than 900 MHz 2
15-35% faster than 900 MHz 2
Xeon Processor DP
Xeon Processor MP
Two
Four
Four
Eight
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