Pci Delay Transaction; Onchip Ide Function; Onchip Device Function; Onboard Super Io Function - JETWAY V333DAR1C Manual

PCI Master 1 WS Write
PCI Master 1 WS Read
CPU to AGP Post Write

PCI Delay Transaction

Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
¡ ü ¡ ý ¡ ú ¡ û
F5:Previous Values
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
3-7 Integrated Peripherals
CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
> OnChip IDE Function
> OnChip Device Function
> Onboard Super IO Function

Init Display First

Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
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F5:Previous Values

OnChip IDE Function

Please refer to section 3-7-1

OnChip Device Function

Please refer to section 3-7-2

Onboard Super IO Function

Please refer to section 3-7-3
Init Display First
This item allows you to decide to activate whether PCI Slot or AGP VGA first. The settings
are: PCI Slot, AGP Slot.
3-7-1 OnChip IDE Function
CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
Disabled
Disabled
Disabled
Disabled
F6:Optimized Defaults
Integrated Peripherals
Press Enter
Press Enter
Press Enter
PCI Slot
F6:Optimized Defaults
OnChip IDE Function
30
Item Help
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F1:General Help
F7:Standard Defaults
Item Help
Menu Level >
F1:General Help
F7:Standard Defaults