TYAN TOMCAT IVS D Manual page 54

SingleBit Correctable Error
This option if enabled will assert SERR# upon the detection of a single
bit error (SBE). The default is disabled.
MultiBit Uncorrectable Error
This option if enabled will assert SERR# upon the detection of a multi
bit error (MBE) or parity error. The default is disabled.
Bad Parity On Uncorrectable Error
The TXC forces bad parity on PCI read data starting from the time an
uncorrectable DRAM error is detected,until the end of the current
cycle.
The default is disabled.
PCI 2.1 Passive Release Enable
If enabled, this option causes the PIIX3 to use the passive release
mechanism on the PHOLD# signal. If disabled the PHOLD# signal
behaves as it did previously with the Triton I chipset.
The default is enabled.
Delayed Transaction Enable
If enabled the delayed transaction mechanism is used when the PIIX3 is
the target of a PCI transaction. The default is enabled.
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