TYAN TOMCAT IVS D Manual page 34

w Chipset Features
The DRAM timings can be altered from the default to optimize system
performance. Be aware though that these settings are sensitive to the
type and speed of DRAMs being used and can cause lockups or data
lost if set incorrectly. The default settings should work with most
DRAMs.
w DRAM RAS# Precharge Time
DRAM must continually be refreshed or it will lose its data. Normally,
DRAM is refreshed entirely as the result of a single request. This option
allows you to determine the number of CPU clocks allocated for the
Row Address Strobe to accumulate its charge before the DRAM is
refreshed. If insufficient time is allowed, refresh may be incomplete
and data will be lost. A lower setting may increase performance.
The default value is 4 clocks.
w DRAM R/W Leadoff Timing
This sets the number of CPU clocks allowed before reads and
writes to DRAM are performed. The default of 8/7 would set the
leadoff timing for reads to eight clocks and writes to seven clocks.
A lower setting may increase performance.
The default value is 8/7.
w DRAM RAS to CAS Delay
When DRAM is refreshed, both rows and columns are addressed
separately. This option allows you to determine the timing of the
transition from Row Address Strobe (RAS) to Column Address
Strobe(CAS). A lower setting may increase performance.
The default is 3 cpu clock delay.
w DRAM Read/Write Burst Timing
This sets the timing for Burst mode reads from DRAM. Burst read and
write requests are generated by the CPU in four separate parts. The
"x" is the leadoff cycle and is determined by the chipset and the memory
timing. The remaining four numbers is the actual data cycles. The lower
the timing numbers, the faster the system will address memory.
The default for read burst timing is x4444.
The default for write burst timing is x4444.
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