TYAN Titan Turbo S1573S ATX-2 Manual page 39

DRAM Read Burst (EDO/FP)
Sets the timing for reads from EDO (Extended Data Output) or FP[M]
(Fast Page Mode) memory. The lower you set the timing numbers, the
faster the system will address the memory. Selecting timing numbers
lower than the installed DRAM is able to support can result in memory
errors.
DRAM Write Burst Timing
Sets the timing for writes to memory. As above, the lower the timing
values, the faster the system will address the memory. Note that
selecting timing numbers lower than the installed DRAM is able to
support can result in memory errors.
Fast EDO Leadoff
Unless you have EDO DRAMs in a synchronous cache or cacheless
system, select Disabled. Enabling will cause a 1-HCLK pull-in for all
read leadoff latencies for EDO DRAMs (i.e., page hits, page misses,
and row misses). You should also select Disabled if any of the DRAM
rows contains FPM DRAMs.
Refresh RAS# Assertion
Selects the number of clock cycles in which RAS# is asserted for
refresh cycles.
Fast RAS To CAS delay
Inserts a timing delay between the CAS and RAS strobe signals when
DRAM is refreshed, read from, or written to.
DRAM Page Idle Timer
Selects the time in HCLKs that the DRAM controller waits to close a
DRAM page after the CPU becomes idle.
DRAM Enhanced Paging
When Enabled, the chipset keeps the page open until a page/row miss.
When Disabled, the chipset uses additional data to keep the DRAM
page open when the host may be only temporarily absent.
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