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DS593 (v1.2.1) March 17, 2011
Features
•
High-performance FPGA and PROM programming and
configuration
•
Includes innovative FPGA-based acceleration
firmware encapsulated in a small form factor pod
attached to the cable
•
Leverages high-speed Slave Serial mode
programming interface
•
Recommended for prototyping use only
•
Easy to use
•
Fully integrated and optimized for use with Xilinx®
iMPACT software
•
Intuitive multiple cable management from a single
application
•
Supported on the following operating systems:
-
Microsoft Windows XP Professional
-
Microsoft Windows Vista
-
Red Hat Enterprise Linux
-
SUSE Linux Enterprise
•
Automatically senses and adapts to target I/O
voltage
•
Interfaces to devices operating at 5V (TTL), 3.3V
(LVCMOS), 2.5V, 1.8V and 1.5V
•
Intuitive flyleads-to-cable interface labeling
Platform Cable USB II Description
Much more than just a simple USB cable, Platform Cable
USB II
(Figure
1) provides integrated firmware (hardware
and software) to deliver high-performance, reliable and
easy-to-perform configuration of Xilinx devices.
Platform Cable USB II attaches to user hardware for the
purpose of configuring Xilinx FPGAs, programming Xilinx
PROMs and CPLDs, and directly programming third-party
SPI flash devices. In addition, the cable provides a means of
indirectly programming Platform Flash XL, third-party SPI
flash memory devices, and third-party parallel NOR flash
© Copyright 2008–2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS593 (v1.2.1) March 17, 2011
35
www.xilinx.com
Platform Cable USB II
•
Reliable
•
Backwards compatibility with Platform Cable USB,
including Pb-Free (RoHS-compliant)
•
USB Integrators Forum (USB-IF) certified
•
CE and FCC compliant
•
Leverages industry standards, including JTAG
Boundary-Scan IEEE 1149.1, SPI and USB 2.0
•
Programs and configures all Xilinx devices
•
XC18V00 ISP PROMs
•
Platform Flash XCF00S/XCF00P/XL PROMs
•
All Virtex®, Spartan® and XC4000 FPGA families
•
XC9500 / XC9500XL / XC9500XV and
CoolRunner™ XPLA3 / CoolRunner-II CPLDs
Note:
Xilinx iMPACT software is required for
programming and configuration
•
Third-party PROM device programming support
•
Directly programs selected Serial Peripheral
Interface (SPI) flash memory devices
•
Indirectly programs selected SPI or parallel flash
memory devices via FPGA JTAG port
•
Highly optimized for use with Xilinx design tools
•
ISE® Foundation™ Software
•
Embedded Development Kit
•
ChipScope™ Pro Analyzer
•
System Generator for DSP
memory devices via the FPGA JTAG port. Furthermore,
Platform Cable USB II is a cost effective tool for debugging
embedded software and firmware when used with
applications such as Xilinx's Embedded Development Kit
and ChipScope Pro Analyzer.
Platform Cable USB II is an upgrade to and replaces
Platform Cable USB. Similar to its popular predecessor,
Platform Cable USB II is intended for prototyping
environments only. Platform Cable USB II is backwards
PN 0011051 04
1
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Table of Contents
Related Manuals for Xilinx HW-USB-II-G
Summarization of Contents
Features
High-performance FPGA and PROM Programming
Enables high-speed FPGA and PROM programming and configuration.
Reliable Operation and Compliance
Ensures reliable performance, certified by USB-IF, CE, and FCC standards.
Ease of Use and System Compatibility
Features intuitive operation, broad OS support, and adaptive I/O voltage.
Third-Party PROM Device Support
Supports direct and indirect programming of third-party SPI flash memory devices.
Optimized for Xilinx Design Tools
Integrates seamlessly with Xilinx IMPACT, ISE, and other development tools.
Physical Description
Plastic Case Physical Description
Details the recyclable, fire-retardant plastic case and internal EMI shielding.
Operation
Minimum Host System Requirements
Specifies the necessary host computer hardware for using the cable.
Operating Power
Describes the cable's bus-powered nature and power consumption.
Device Driver Installation
Guides users on installing the required proprietary device driver for the cable.
Firmware Updates
Covers the process and necessity of updating the cable's microcontroller and FPGA firmware.
Hot Plug and Play
Details the ability to connect/disconnect the cable without system reboot.
Connecting to the Cable in IMPACT
Explains how to establish a connection using the Xilinx IMPACT GUI.
Select a Flow
Guides on selecting the appropriate configuration flow within IMPACT.
Establishing a Connection
Outlines methods for connecting the cable to the target system via IMPACT.
Multiple USB Cable Management
Cable Setup Information Dialog
Explains the dialog box for selecting specific USB cables.
Configuration Clock Speed
Clock Speed Selections
Lists the available TCK_CCLK_SCK frequencies for the cable.
IMPACT Cable Status Bar
Status Bar Information
Details the information displayed in the iMPACT cable status bar.
Status Indicator
Status LED Behavior
Describes LED colors and their meaning for target voltage and firmware updates.
System Suspend
Suspend Warning When IMPACT is Busy
Shows the warning message when suspend is attempted during an IMPACT operation.
Platform Cable USB II Connections
High Performance Ribbon Cable
Details the supplied ribbon cable for connecting to target systems.
Flying Wire Adapter
Describes the adapter for connecting to legacy target systems using flying wires.
Physical Connection to the Host
Standard A-B Host Interface Cable
Details the detachable USB A-B cable and host receptacle.
Target Interface Connectors
2 mm Connector Dimensions and Signal Assignments
Provides pinout and physical dimensions for the 2-mm target interface connector.
Target System Connections
JTAG and Slave Serial Topologies
Shows typical routing for JTAG and Slave Serial connections.
Direct SPI
Direct SPI Topology Example
Illustrates a direct SPI connection to a flash device.
Indirect SPI Programming
Describes indirect SPI programming via the target FPGA's JTAG port.
Indirect BPI Programming
Details indirect BPI programming via the target FPGA's JTAG port.
Target Interface Reference Voltage and Signals
Target Reference Voltage Sensing (VREF)
Explains VREF sensing and its role in output buffer operation.
Bidirectional Signal Pins
Lists and describes the five bidirectional signal pins on the cable.
Output Driver Structure
Details the output buffer circuitry and its behavior.
Input Receive Structure
Target Interface Receiver Topology
Shows the schematic of the input receiver buffer.
Pseudo Ground Signal
PGND Signal Diagram
Illustrates the PGND signal buffer and its connections.
HALT_INIT_WP Signal in iMPACT
Enabling the HALT Signal in IMPACT
Guides on enabling the HALT signal via the iMPACT programming properties.
Timing Specifications
TDI/DIN/TMS/PROG Timing
Details timing for TDI, DIN, TMS, and PROG signals relative to TCK.
TDO/MISO Timing Considerations
TCK and TDO Timing
Explains timing relationships between TCK and TDO signals.
Signal Integrity
Differential Clock Buffer Example
Shows an example of using differential clock buffers for signal integrity.
USB Hub Types and Cable Performance
Maximum Port Current
Describes the cable's current draw and limitations with certain hubs.
Total Bandwidth
Explains bandwidth considerations for USB 2.0 and USB 1.1 connections.
Interface Pin Descriptions
2-mm Connector Signal Assignments
Provides pinout and descriptions for the 2-mm target interface connector.
Platform Cable USB II Operating Characteristics
Absolute Maximum Ratings
Lists the extreme operating conditions for the cable.
Recommended DC Operating Conditions
Specifies normal operating voltage, temperature, and current ranges.
DC Electrical Characteristics
Provides detailed DC voltage and current parameters.
Switching Characteristics
Details timing parameters for signal transitions.
USB-IF Compliance
USB-IF Compliance Program
Explains the tests and certification process for USB compliance.
Regulatory Information
FCC Notice
Provides compliance information for Class A digital devices under FCC rules.
Industry Canada Information
States compliance with Canadian ICES-003 for Class A digital apparatus.
Ordering and Marking Information
Ordering Information
Specifies the product number for the cable and accessories.
Marking Information
Details the model name and serial prefix for identification.
Revision History
Document Revision History
Lists dates, versions, and descriptions of document revisions.
Notice of Disclaimer
Xilinx Limited Warranty Disclaimer
Outlines limitations of the Xilinx limited warranty for product usage.
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