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M2S150
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Microsemi M2S150 User Manual
Soc fpga and igloo2 fpga fabric
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Contents
Table of Contents
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Table of Contents
Table of Contents
1 Revision History
Revision 7.0
Revision 6.0
Revision 5.0
Revision 4.0
Revision 3.0
Revision 2.0
Revision 1.0
Revision 0.0
2 Fabric Architecture
Introduction
Fabric Resources
Figure 1 Smartfusion2/Igloo2 Fabric Architecture for M2S050/M2GL050
Table 1 Fabric Resources for Smartfusion2 Devices
Architecture Overview
Logic Element
Figure 2 Functional Block Diagram of Logic Element
Table 2 Fabric Resources for IGLOO2 Devices
Interface Logic Element
I/O Module
FPGA Routing Architecture
Figure 3 Functional Block Diagram of MSIO
Figure 4 Logic Cluster Top-Level Layout
Figure 5 Interface Cluster
Figure 6 Fabric Routing Structure
Fabric Array Coordinate System
Figure 7 M2S050/M2GL050 and M2S060/M2GL060 Fabric Logical Coordinates
Figure 8 M2S025/M2GL025 Fabric Logical Coordinates
Figure 9 M2S010/M2GL010 Fabric Logical Coordinates
Table 3 Fabric Array Coordinate Systems
3 Lsram
Introduction
Features
LSRAM Resources
Table 4 Smartfusion2 and IGLOO2 LSRAM (18Kb Blocks) Resource Table
Functional Description
Figure 10 Simplified Functional Block Diagram for LSRAM
Port List
Table 5 Port List for LSRAM Macro (RAM1KX18)
Port Descriptions
Table 6 Depth/Width Mode Selection
Table 7 Read/Write Operation Selection
Table 8 Address Bus Used and Unused Bits
Table 9 Data Input Buses Used and Unused Bits
Table 10 Data Output Buses Used and Unused Bits
Table 11 Port Select Control Signals
Memory Modes
Dual-Port Mode
Figure 11 Data Path for Dual-Port Mode
Two-Port Mode
Figure 12 Data Path for Two-Port Mode
Table 12 Data Width Configurations for LSRAM in Dual-Port Mode
Table 13 Data Width Configurations for LSRAM in Two-Port Mode
Operating Modes
Read Operation
Figure 13 Read Operation Timing Waveforms
Write Operation
Figure 14 RADDR Synchronizer
Table 14 Read Operation Timing Parameters
Figure 15 Write Operation Timing Waveforms
Table 15 Write Operation Timing Parameters
Reset Operation
Block Select Operation
Figure 16 Asynchronous Reset Operation
Table 16 Asynchronous Reset Timing Parameters
Figure 17 Block Select Timings
Table 17 Block Selection Timing Parameters
Collision
How to Use LSRAM
Design Flow
Table 18 Collision Operation Description
Figure 18 Ports of the LSRAM Configured as Dual-Port SRAM - DPSRAM Macro in Libero Soc
Table 19 Port Description for the DPSRAM Macro
Figure 19 Ports of the LSRAM Configured as Two-Port SRAM - TPSRAM Macro in Libero Soc
Table 20 Port Description for the TPSRAM Macro
Figure 20 Ram1Kx18 Macro
Figure 21 Coreahblsram IP in Libero Soc
Figure 22 Coreapblsram IP in Libero Soc
Table 21 Port Description for the Coreapblsram IP
Table 22 Port Description for the Coreahblsram IP
LSRAM Use Model
Figure 23 Two-Port SRAM with W36 and R18
Table 23 Two-Port Configurations Requiring Two LSRAM Blocks
4 Micro SRAM (Μsram)
Introduction
Features
Μsram Resource Table
Table 24 Smartfusion2 and IGLOO2 Μsram (1Kb Blocks) Resource Table
Functional Description
Architecture Overview
Figure 24 Simplified Functional Block Diagram of Μsram
Port List
Table 25 Port List for Μsram
Port Description
Table 26 Width/Depth Mode Selection
Table 27 Address Bus Used and Unused Bits
Table 28 Data Input Buses Used and Unused Bits
Table 29 Data Output Buses Used and Unused Bits
Table 30 Port Select Control Signals
Operating Modes
Read Operation
Figure 25 Timing Waveforms for Synchronous-Asynchronous Read Operation
Table 31 Timing Parameters for Synchronous-Asynchronous Read Operation
Figure 26 Timing Waveforms for Synchronous-Synchronous Read Operation
Table 32 Timing Parameters for Synchronous-Synchronous Read Operation
Figure 27 Timing Waveforms for Synchronous Latched Read Operation
Table 33 Timing Parameters for Synchronous Latched Read Operation
Figure 28 Timing Waveforms for Read Operations with Asynchronous Inputs Without Pipeline Registers
Figure 29 Timing Waveforms for Read Operations with Asynchronous Inputs with Pipeline Registers
Table 34 Timing Parameters of the Asynchronous Read Mode Without Pipeline Registers
Table 35 Timing Parameters of the Asynchronous Read Mode with Pipeline Registers
Write Operation
Figure 30 Timing Waveforms for Read Operations with Asynchronous Inputs with Latched Outputs
Table 36 Timing Parameters of the Asynchronous Read Mode with Latched Outputs
Reset Operation
Figure 31 Timing Waveforms for the Write Operation
Table 37 Timing Parameters of the Write Operation
Figure 32 Timing Waveforms for Asynchronous Reset
Figure 33 Timing Waveforms for Synchronous Reset
Table 38 Timing Parameters of the Asynchronous Reset
Collision
Table 39 Timing Parameters of the Synchronous Reset
Table 40 Collision Scenarios
How to Use Μsram
Design Flow
Figure 34 Μsram IP Macro in Libero Soc
Table 41 Port Description for the Μsram-IP Macro
Figure 35 Ram64X18 Macro
5 Math Blocks
Introduction
Features
Math Block Resource Table
Table 42 Smartfusion2 and IGLOO2 Math Blocks Resource
Functional Description
Architecture Overview
Figure 36 Functional Block Diagram of the Math Block
Figure 37 Functional Block Diagram of the Math Block in Normal Mode
Figure 38 Functional Block Diagram of the Math Block in DOTP Mode
Table 43 Truth Table for Propagating Operand D of the Adder or Accumulator
How to Use Math Blocks
Design Flow
Figure 39 Math Block Macro
Table 44 Math Block Pin Descriptions
Math Block Use Models
Figure 40 Non-Pipelined 35 X 35 Multiplier
Figure 41 Pipeline 35 X 35 Multiplier
Figure 42 9-Bit Complex Multiplication Using DOTP Mode
Figure 43 Rounding Using C-Input and CARRYIN
Table 45 Rounding Examples
Figure 44 Rounding and Trimming of the Final Sum
Figure 45 Rounding and Trimming of the Final Sum
Coding Style Examples
6 I/Os
Introduction
Functional Description
Figure 46 I/O Interconnection
Receive Buffer
Transmit Buffer
Figure 47 IOA Architecture
Figure 48 DDR Support in Low Power Flash Devices
Low-Power Exit
On-Die Termination
I/O Banks
Simultaneous Switching Noise
GND Bounce and VDDI Bounce
Figure 49 a Sample Switching Output Buffer Showing Parasitic Inductance
Figure 50 Basic Block Diagram of Quiet I/O Surrounded by SSO Bus
Table 46 MSIO SSO Guidelines for M2S010 - FG484 Device
Table 47 MSIOD SSO Guidelines for M2S010 - FG484 Device
Table 48 DDRIO SSO Guidelines for M2S010 - FG484 Device
Table 49 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S025 - FG484 Device
Table 50 MSIO SSO Guidelines for M2S050 - FG896 Device
Table 51 MSIOD SSO Guidelines for M2S050 - FG896 Device
Table 52 DDRIO SSO Guidelines for M2S050 - FG896 Device
Table 53 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S060 - FG676 Device
Table 54 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S090 - FG676 Device
Table 55 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S090 - FCS325 Device
Table 56 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S150 - FC1152 Device
Supported I/O Standards
Table 57 Supported I/O Standards
Single-Ended Standards
Voltage-Referenced Standards
Differential Standards
Table 58 IOA Pair Design Rules
Table 59 Status of the
I/O Programmable Features
Programmable Slew-Rate Control
Figure 51 Programmable Slew-Rate
Table 60 Smartfusion2 and IGLOO2 I/O Features
Table 61 Programmable Slew Rate Control
Programmable Input Delay
Programmable Weak Pull-Up and Pull-Down
Figure 52 Programmable Input Delay
Table 62 Table
Programmable Schmitt Trigger Receiver
Programmable Pre-Emphasis
Figure 53 Programmable Weak Pull-Up and Pull-Down
Figure 54 Programmable Schmitt Trigger Receiver
Bus Keeper
Figure 55 Programmable Pre-Emphasis
Figure 56 Bus Keeper Configuration in I/O Editor
Table 63 I/O Programmable Features and Standards
Receiver ODT Configuration
Receiver ODT Configuration for MSIO and MSIOD Banks
Figure 57 Receiver ODT Configuration
Receiver ODT Configuration for DDRIO Banks
Table 64 ODT Impedance Values
Table 65 ODT Configuration Options for MSIO, MSIOD, and Ddrios
Table 66 DDRIO ODT Configuration- for I/O Connected to Fabric
Table 67 DDRIO ODT Configuration- for I/O Connected to DDR Controller
Driver Impedance Configuration
Figure 58 Output Drive Impedance
Table 68 Driver Impedance Configurations
Driver Impedance Configuration for Ddrios
Driver Impedance Configuration for Msio/Msiods
Table 69 Driver Impedance Configurations for Msio/Msiods
Table 70 Driver Impedance Configurations for Ddrios
I/O Buffer Structure
Internal Clamp Diode
Figure 59 Driver Impedance Configurations for Msio/Msiods
Table 71 Driver Impedance Configurations for Ddrios Without DDR Controller
Low-Power Signature Mode and Activity Mode
Signature Mode
Activity Mode
3.3 V Input Tolerance in 2.5 V MSIOD/DDRIO Banks
Figure 60 Simulation Setup
Input Tolerance and Output Driving Compatibility (Only MSIO)
5 V Input Tolerance
Table 72 Table 73 F
Figure 61 5 V-Input Tolerance Solution 1
Figure 62 5 V Input Tolerance Solution 2
Output Driving Compatibility
I/Os in Conjunction with Fabric, MDDR/FDDR, and MSS/HPMS Peripherals
Ddrios with MDDR/FDDR
Ddrios with Fabric
Figure 63 5 V Input Tolerance Solution 3
Table 74 Slew Rate Control
Msios/Msiods with MSS or HPMS Peripherals
Msios/Msiods with Fabric
Jtag I/O
Table 75 JTAG Pin Description
Table 76 Recommended Tie-Off Values for the TCK and TRST Pins
Dedicated I/O
Device Reset I/O
Crystal Oscillator I/O
Figure 64 Chip Level Resets from Device Reset
Table 77 Device Reset I/O Pin
Table 78 Crystal Oscillator I/O Pins
Serdes I/O
7 Glossary
Acronyms
Terminology
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Revision 7.0
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See also:
Configuration Manual
,
User Manual
UG0445
User Guide
SmartFusion2 SoC FPGA and IGLOO2 FPGA Fabric
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