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ST STM32F303 B Series Reference Manual

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STM32F303xB/C/D/E, STM32F303x6/8, STM32F328x8,

STM32F358xC, STM32F398xE advanced ARM

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32F303xB/C/D/E, STM32F303x6/x8, STM32F328x8, STM32F358xC

and STM32F398xE microcontroller memory and peripherals. The STM32F303xB/C/D/E,

STM32F303x6/x8, STM32F328x8, STM32F358xC and STM32F398xE devices will be

referred to as STM32F3xx throughout the document, unless otherwise specified.

The STM32F3xx is a family of microcontrollers with different memory sizes, packages and

peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

relevant datasheets.

For information on the ARM

STM32F3xx/STM32F4xx programming manual (PM0214).

Related documents

• STM32F303xB/C, STM32F303xD/E, STM32F303x6/8, STM32F328x8, STM32F358xC

and STM32F398xE datasheets available from the company website at www.st.com.

• STM32F3xx/F4xx Cortex

company website at www.st.com.

January 2017

®

®

C

-M4 core with FPU, please refer to the

ORTEX

® -M4 programming manual (PM0214) available from the

DocID022558 Rev 8

RM0316

Reference manual

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Summary of Contents for ST STM32F303 B Series

Page 1 ORTEX STM32F3xx/STM32F4xx programming manual (PM0214). Related documents • STM32F303xB/C, STM32F303xD/E, STM32F303x6/8, STM32F328x8, STM32F358xC and STM32F398xE datasheets available from the company website at www.st.com. ® -M4 programming manual (PM0214) available from the • STM32F3xx/F4xx Cortex company website at www.st.com. January 2017...
Page 2: Table Of Contents
Contents RM0316 Contents Overview of the manual ........43 Documentation conventions .
Page 3 RM0316 Contents 4.3.3 Option byte block write protection ......77 Flash interrupts ..........77 Flash register description .
Page 4 Contents RM0316 7.2.1 Power on reset (POR)/power down reset (PDR) ....97 7.2.2 Programmable voltage detector (PVD) ......99 7.2.3 External NPOR signal .
Page 5 RM0316 Contents 8.3.19 From TIM to IRTIM ........122 Reset and clock control (RCC) .
Page 6 Contents RM0316 9.4.13 Clock configuration register 3 (RCC_CFGR3) ....162 9.4.14 RCC register map ........166 Flexible static memory controller (FSMC) .
Page 7 RM0316 Contents 11.3.3 I/O port control registers ........232 11.3.4 I/O port data registers .
Page 8 Contents RM0316 12.1.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) ........252 12.1.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) .
Page 9 RM0316 Contents 14.1.3 Interrupt and exception vectors ......285 14.2 Extended interrupts and events controller (EXTI) ....292 14.2.1 Main features .
Page 10 Contents RM0316 15.3.11 Channel selection (SQRx, JSQRx) ......321 15.3.12 Channel-wise programmable sampling time (SMPR1, SMPR2) ..322 15.3.13 Single conversion mode (CONT=0) .
Page 11 RM0316 Contents 15.5.12 ADC regular sequence register 3 (ADCx_SQR3, x=1..4) ..396 15.5.13 ADC regular sequence register 4 (ADCx_SQR4, x=1..4) ..397 15.5.14 ADC regular Data Register (ADCx_DR, x=1..4) .
Page 12 Contents RM0316 16.9 DMA request ..........427 16.10 DAC registers .
Page 13 RM0316 Contents 17.5 COMP registers ......... . . 447 17.5.1 COMP1 control and status register (COMP1_CSR) .
Page 14 Contents RM0316 19.3.5 Spread spectrum feature ........492 19.3.6 Max count error .
Page 15 RM0316 Contents 20.3.13 Combined PWM mode ........539 20.3.14 Combined 3-phase PWM mode .
Page 16 Contents RM0316 20.4.21 TIM1/TIM8/TIM20 option registers (TIMx_OR) ....594 20.4.22 TIM1/TIM8/TIM20 capture/compare mode register 3 (TIMx_CCMR3) 595 20.4.23 TIM1/TIM8/TIM20 capture/compare register 5 (TIMx_CCR5) ..596 20.4.24 TIM1/TIM8/TIM20 capture/compare register 6 (TIMx_CCR6) .
Page 17 RM0316 Contents 21.4.6 TIMx event generation register (TIMx_EGR) ....655 21.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) ... 656 21.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) .
Page 18 Contents RM0316 23.2 TIM15 main features ........683 23.3 TIM16/TIM17 main features .
Page 19 RM0316 Contents 23.5.13 TIM15 capture/compare register 1 (TIM15_CCR1) ....733 23.5.14 TIM15 capture/compare register 2 (TIM15_CCR2) ....734 23.5.15 TIM15 break and dead-time register (TIM15_BDTR) .
Page 20 Contents RM0316 25.4 IWDG registers ..........761 25.4.1 Key register (IWDG_KR) .
Page 21 RM0316 Contents 27.3.10 RTC synchronization ........783 27.3.11 RTC reference clock detection .
Page 22 Contents RM0316 28.4.1 I2C block diagram ........818 28.4.2 I2C clock requirements .
Page 23 RM0316 Contents 29.3 USART extended features ........886 29.4 USART implementation .
Page 24 Contents RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) ... . . 952 30.1 Introduction ..........952 30.2 SPI main features .
Page 25 RM0316 Contents 30.9.2 SPI control register 2 (SPIx_CR2) ......1000 30.9.3 SPI status register (SPIx_SR) ......1003 30.9.4 SPI data register (SPIx_DR) .
Page 26 Contents RM0316 31.9 CAN registers ..........1030 31.9.1 Register access protection .
Page 27 RM0316 Contents 33.6.1 MCU device ID code ........1095 33.6.2 Boundary scan TAP .
Page 28 Contents RM0316 33.17.4 TPUI frame synchronization packets ......1115 33.17.5 Transmission of the synchronization frame packet ....1116 33.17.6 Synchronous mode .
Page 29 RM0316 List of tables List of tables Table 1. Available features related to each product ........43 Table 2.
Page 30 List of tables RM0316 Table 46. FMC_BCRx bit fields ........... . 183 Table 47.
Page 31 RM0316 List of tables Table 96. Analog watchdog channel selection ......... 354 Table 97.
Page 32 List of tables RM0316 Table 143. Comparison of analog vs. digital filters ........821 Table 144.
Page 33: List Of Tables
RM0316 List of tables Table 192. DATA transfer (33 bits) ..........1099 Table 193.
Page 34 List of figures RM0316 List of figures Figure 1. STM32F303xB/C and STM32F358xC system architecture ......48 Figure 2. STM32F303x6/8 and STM32F328x8 system architecture .
Page 35 RM0316 List of figures Figure 49. STM32F303xB/C/D/E, STM32F358xC and STM32F398xE DMA2 request mapping . . . 274 Figure 50. External interrupt/event block diagram ........293 Figure 51.
Page 36 List of figures RM0316 Figure 95. ADCy_AWDx_OUT signal generation (on a single regular channel) ....357 Figure 96. ADCy_AWDx_OUT signal generation (on all injected channels) ....357 Figure 97.
Page 37 RM0316 List of figures Figure 141. Counter timing diagram with prescaler division change from 1 to 2 ....509 Figure 142. Counter timing diagram with prescaler division change from 1 to 4 ....509 Figure 143.
Page 38 List of figures RM0316 Figure 193. Control circuit in reset mode ..........559 Figure 194.
Page 39 RM0316 List of figures Figure 244. Triggering TIM2 with Enable of TIM3 ........644 Figure 245.
Page 40 List of figures RM0316 Figure 292. I2C block diagram ........... . . 818 Figure 293.
Page 41 RM0316 List of figures Figure 344. Hardware flow control between 2 USARTs ........923 Figure 345.
Page 42 List of figures RM0316 Figure 395. Filtering mechanism - example ..........1024 Figure 396.
Page 43: Overview Of The Manual
RM0316 Overview of the manual Overview of the manual Table 1. Available features related to each product Peripherals STM32F303xB/C STM32F303xD/E STM32F358xC STM32F398xE STM32F303x6/8 STM32F328x6/8 Section 9: Reset and Available Available Available Available Available Available clock control (RCC) Section 11: General- Up to 87 Up to 115 Up to 86...
Page 44 Overview of the manual RM0316 Table 1. Available features related to each product (continued) Peripherals STM32F303xB/C STM32F303xD/E STM32F358xC STM32F398xE STM32F303x6/8 STM32F328x6/8 Section 21: General- purpose TIM2,3&4 TIM2,3&4 TIM2,3&4 TIM2,3&4 TIM2&3 TIM2&3 timers (TIM2/TIM3/T IM4) Section 23: General- purpose TIM15,16&17 TIM15,16&17 TIM15,16&17 TIM15,16&17 TIM15,16&17...
Page 45 RM0316 Overview of the manual Table 1. Available features related to each product (continued) Peripherals STM32F303xB/C STM32F303xD/E STM32F358xC STM32F398xE STM32F303x6/8 STM32F328x6/8 Section 31: Controller Available Available Available Available Available Available area network (bxCAN) Section 32: Universal serial bus full- Available Available Not Available Not Available...
Page 46: Documentation Conventions
Documentation conventions RM0316 Documentation conventions List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit. write-only (w) Software can only write to this bit. Reading this bit returns the reset value. read/clear (rc_w1) Software can read as well as clear this bit by writing 1.
Page 47: System And Memory Overview
RM0316 System and memory overview System and memory overview System architecture The STM32F303xB/C/D/E, STM32F358xC and STM32F398xE main system consists of: • Five masters: ® – Cortex -M4 core I-bus ® – Cortex -M4 core D-bus ® – Cortex -M4 core S-bus –...
Page 48: Figure 1. Stm32F303Xb/C And Stm32F358Xc System Architecture
System and memory overview RM0316 Figure 1. STM32F303xB/C and STM32F358xC system architecture Figure 2. STM32F303x6/8 and STM32F328x8 system architecture 48/1141 DocID022558 Rev 8...
Page 49: S0: I-Bus
RM0316 System and memory overview Figure 3. STM32F303xDxE and STM32F398xE system architecture 3.1.1 S0: I-bus ® This bus connects the Instruction bus of the Cortex -M4 core to the BusMatrix. This bus is used by the core to fetch instructions. The targets of this bus are the internal Flash memory, the SRAM and the CCM SRAM.
Page 50: Busmatrix
System and memory overview RM0316 3.1.5 BusMatrix The BusMatrix manages the access arbitration between Masters. The arbitration uses a Round Robin algorithm. The BusMatrix is composed of five masters (CPU AHB, System bus, DCode bus, ICode bus, DMA1&2 bus) and seven slaves (FLITF, SRAM, CCM SRAM, AHB2GPIO and AHB2APB1/2 bridges, and ADC).
Page 51: Memory Organization
RM0316 Memory organization 3.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
Page 52 RM0316 Table 2. STM32F303xB/C and STM32F358xC peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4002 4000 - 0x4002 43FF Section 19.6.11 on page 504 0x4002 3400 - 0x4002 3FFF Reserved 0x4002 3000 - 0x4002 33FF Section 6.4.6 on page 93 0x4002 2400 - 0x4002 2FFF Reserved...
Page 53 RM0316 Table 2. STM32F303xB/C and STM32F358xC peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4000 7400 - 0x4000 77FF DAC1 Section 16.10.15 on page 438 0x4000 7000 - 0x4000 73FF Section 7.4.3 on page 110 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 6800 - 0x4000 6BFF...
Page 54: Table 3. Stm32F303Xd/E And Stm32F398Xe Peripheral Register Boundary
RM0316 Table 2. STM32F303xB/C and STM32F358xC peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x0804 0000 - 0x0FFF FFFF ~128 M Reserved 0x0800 0000 - 0x0803 FFFF 256 K Main Flash memory 0x0004 0000 - 0x07FF FFFF ~128 M Reserved Main Flash memory,...
Page 55 RM0316 Table 3. STM32F303xD/E and STM32F398xE peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4002 4000 - 0x4002 43FF Section 19.6.11 on page 504 0x4002 3400 - 0x4002 3FFF Reserved 0x4002 3000 - 0x4002 33FF Section 6.4.6 on page 93 0x4002 2400 - 0x4002 2FFF Reserved...
Page 56 RM0316 Table 3. STM32F303xD/E and STM32F398xE peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4000 7800 - 0x4000 7BFF I2C3 Section 28.7.12 on page 883 0x4000 7400 - 0x4000 77FF DAC1 Section 16.10.15 on page 438 0x4000 7000 - 0x4000 73FF Section 7.4.3 on page 110 0x4000 6C00 - 0x4000 6FFF...
Page 57: Table 4. Stm32F303X6/8 And Stm32F328X8 Peripheral Register Boundary
RM0316 Table 3. STM32F303xD/E and STM32F398xE peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x1000 0000 - 0x1000 3FFF 16 K CCM SRAM 0x0808 0000 - 0x0FFF FFFF ~128 M Reserved 0x0800 0000 - 0x0807 FFFF 512 K Main Flash memory 0x0008 0000 - 0x07FF FFFF...
Page 58 RM0316 Table 4. STM32F303x6/8 and STM32F328x8 peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4001 4C00 - 0x4001 7FFF 13 K Reserved 0x4001 4800 - 0x4001 4BFF TIM17 Section 23.6.17 on page 755 0x4001 4400 - 0x4001 47FF TIM16 0x4001 4000 - 0x4001 43FF TIM15...
Page 59 RM0316 Table 4. STM32F303x6/8 and STM32F328x8 peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4000 9800 - 0x4000 9BFF DAC2 Section 16.10.15 on page 438 0x4000 7800 - 0x4000 97FF Reserved 0x4000 7400 - 0x4000 77FF DAC1 Section 16.10.15 on page 438 0x4000 7000 - 0x4000 73FF...
Page 60: Embedded Sram
RM0316 Table 4. STM32F303x6/8 and STM32F328x8 peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x0001 0000 - 0x07FF FFFF ~128 M Reserved Main Flash memory, system memory or 0x0000 000 - 0x0000 FFFF 64 K SRAM depending on BOOT configuration 1.
Page 61: Ccm Sram Write Protection
RM0316 TIMER 20, 1, 8, 15, 16 and 17, by setting the SRAM_PARITY_LOCK control bit in the SYSCFG configuration register 2 (SYSCFG_CFGR2). In case of parity error, the SRAM Parity Error flag (SRAM_PEF) is set in the SYSCFG configuration register 2 (SYSCFG_CFGR2).
Page 62: Flash Memory Overview
RM0316 Flash memory overview The Flash memory is composed of two distinct physical areas: • The main Flash memory block. It contains the application program and user data if necessary. • The information block. It is composed of two parts: –...
Page 63: Embedded Boot Loader
RM0316 3.5.1 Embedded boot loader The embedded boot loader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory through: • USART1 (PA9/PA10), USART2 (PD5/PD6) or USB (DFU) on STM32F303xB/C devices, •...
Page 64: Embedded Flash Memory
Embedded Flash memory RM0316 Embedded Flash memory Flash main features Up to 512 Kbytes of Flash memory in STM32F303xD/E, up to 256 Kbytes of Flash memory in STM32F303xB/C and STM32F358xC devices and up to 64 Kbytes of Flash memory in STM32F303x6/8 and STM32F328x8 devices.
Page 65: Table 7. Flash Module Organization
Flash memory through one of the following interfaces: USART1, USART2 or USB (DFU) on devices with internal regulator ON and USART or I2C on devices with internal regulator OFF. It is programmed by ST when the device is manufactured, and protected against spurious write/erase operations. For further details, please refer to the AN2606 available from www.st.com.
Page 66: Read Operations
Embedded Flash memory RM0316 4.2.2 Read operations The embedded Flash module can be addressed directly, as a common memory space. Any data read operation accesses the content of the Flash module through dedicated read senses and provides the requested data. The read interface consists of a read controller on one side to access the Flash memory and an AHB interface on the other side to interface with the CPU.
Page 67: Flash Program And Erase Operations
RM0316 Embedded Flash memory Access latency In order to maintain the control signals to read the Flash memory, the ratio of the prefetch controller clock period to the access time of the Flash memory has to be programmed in the Flash access control register with the LATENCY[2:0] bits.
Page 68 Embedded Flash memory RM0316 program/erase operation has completed. This means that code or data fetches cannot be made while a program/erase operation is ongoing. For program and erase operations on the Flash memory (write/erase), the internal RC oscillator (HSI) must be ON. Unlocking the Flash memory After reset, the FPEC is protected against unwanted write or erase operations.
Page 69: Figure 4. Programming Procedure
RM0316 Embedded Flash memory Figure 4. Programming procedure The Flash memory interface preliminarily reads the value at the addressed main Flash memory location and checks that it has been erased. If not, the program operation is skipped and a warning is issued by the PGERR bit in FLASH_SR register (the only exception to this is when 0x0000 is programmed.
Page 70 Embedded Flash memory RM0316 Check that no main Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register. Set the PG bit in the FLASH_CR register. Perform the data write (half-word) at the desired address. Wait until the BSY bit is reset in the FLASH_SR register. Check the EOP flag in the FLASH_SR register (it is set when the programming operation has succeeded), and then clear it by software.
Page 71: Figure 5. Flash Memory Page Erase Procedure
RM0316 Embedded Flash memory Figure 5. Flash memory Page Erase procedure Mass Erase The Mass Erase command can be used to completely erase the user pages of the Flash memory. The information block is unaffected by this procedure. The following sequence is recommended: Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register...
Page 72: Figure 6. Flash Memory Mass Erase Procedure
Embedded Flash memory RM0316 Figure 6. Flash memory Mass Erase procedure Option byte programming The option bytes are programmed differently from normal user addresses. The number of option bytes is limited to 8 (4 for write protection, 1 for readout protection, 1 for hardware configuration, and 2 for data storage).
Page 73 RM0316 Embedded Flash memory The value of the addressed option byte is first read to check it is really erased. If not, the program operation is skipped and a warning is issued by the WRPRTERR bit in the FLASH_SR register. The end of the program operation is indicated by the EOP bit in the FLASH_SR register.
Page 74: Memory Protection
Table Table 8. Flash memory read protection status RDP byte value RDP complement value Read protection level Level 0 (ST production 0xAA 0x55 configuration) Any value (not necessarily Any value except 0xAA or complementary) except 0x55 and...
Page 75 RM0316 Embedded Flash memory Level 1: Read protection This is the default protection level when RDP option byte is erased. It is defined as well when RDP value is at any value different from 0xAA and 0xCC, or even if the complement is not correct.
Page 76: Write Protection
Embedded Flash memory RM0316 Table 9. Access status versus protection level and execution modes Debug/ BootFromRam/ User execution Protection BootFromLoader Area level Read Write Erase Read Write Erase Main Flash memory System memory Option bytes Backup registers 1. When the protection level 2 is active, the Debug port, the boot from RAM and the boot from system memory are disabled.
Page 77: Option Byte Block Write Protection
RM0316 Embedded Flash memory Write unprotection To disable the write protection, two application cases are provided: • Case 1: Read protection disabled after the write unprotection: – Erase the entire option byte area by using the OPTER bit in the Flash memory control register (FLASH_CR).
Page 78: Flash Register Description
Embedded Flash memory RM0316 Flash register description The Flash memory registers have to be accessed by 32-bit words (half-word and byte accesses are not allowed). 4.5.1 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0030 Res. Res. Res.
Page 79: Flash Option Key Register (Flash_Optkeyr)
RM0316 Embedded Flash memory 4.5.3 Flash option key register (FLASH_OPTKEYR) Address offset: 0x08 Reset value: xxxx xxxx All the register bits are write-only and return a 0 when read. OPTKEYR[31:16] OPTKEYR[15:0] Bits 31:0 OPTKEYR: Option byte key These bits represent the keys to unlock the OPTWRE. 4.5.4 Flash status register (FLASH_SR) Address offset: 0x0C...
Page 80: Flash Control Register (Flash_Cr)
Embedded Flash memory RM0316 Bit 2 PGERR: Programming error Set by hardware when an address to be programmed contains a value different from '0xFFFF' before programming. Reset by writing 1. Note: The STRT bit in the FLASH_CR register should be reset before starting a programming operation.
Page 81: Flash Address Register (Flash_Ar)
RM0316 Embedded Flash memory Bit 7 LOCK: Lock Write to 1 only. When it is set, it indicates that the Flash is locked. This bit is reset by hardware after detecting the unlock sequence. In the event of unsuccessful unlock operation, this bit remains set until the next reset.
Page 82: Option Byte Register (Flash_Obr)
Bit 8: WDG_SW Bits 7:3 Reserved, must be kept at reset value. Bit 2:1 RDPRT[1:0]: Read protection Level status 00: Read protection Level 0 is enabled (ST production set up) 01: Read protection Level 1 is enabled 10: Reserved 11: Read protection Level 2 is enabled Note: These bits are read-only.
Page 83: Write Protection Register (Flash_Wrpr)
RM0316 Embedded Flash memory 4.5.8 Write protection register (FLASH_WRPR) Address offset: 0x20 Reset value: 0xFFFF FFFF WRP[31:16] WRP[15:0] Bits 31:0 WRP: Write protect This register contains the write-protection option bytes loaded by the OBL. These bits are read-only. Flash register map Table 11.
Page 84 Embedded Flash memory RM0316 Table 11. Flash interface - register map and reset values (continued) Offset Register FLASH_ 0x01C Reset value FLASH_ WRP[31:0] WRPR 0x020 Reset value Refer to Section 3.2.2: Memory map and register boundary addresses for the register boundary addresses.
Page 85: Option Byte Description
RM0316 Option byte description Option byte description There are eight option bytes. They are configured by the end user depending on the application requirements. As a configuration example, the watchdog may be selected in hardware or software mode. A 32-bit word is split up as follows in the option bytes. Table 12.
Page 86: Table 14. Description Of The Option Bytes
Option byte description RM0316 Table 14. Description of the option bytes Flash memory Option bytes address Bits [31:24]: nUSER Bits [23:16]: USER: User option byte (stored in FLASH_OBR[15:8]) This byte is used to configure the following features: - Select the watchdog event: Hardware or software - Reset event when entering Stop mode - Reset event when entering Standby mode Bit 23: Reserved...
Page 87 RM0316 Option byte description Table 14. Description of the option bytes (continued) Flash memory Option bytes address WRPx: Flash memory write protection option bytes Bits [31:24]: nWRP1 Bits [23:16]: WRP1 (stored in FLASH_WRPR[15:8]) Bits [15:8]: nWRP0 Bits [7:0]: WRP0 (stored in FLASH_WRPR[7:0]) 0x1FFF F808 0: Write protection active 1: Write protection not active...
Page 88: Cyclic Redundancy Check Calculation Unit (Crc)
Cyclic redundancy check calculation unit (CRC) RM0316 Cyclic redundancy check calculation unit (CRC) Introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 89: Crc Functional Description
RM0316 Cyclic redundancy check calculation unit (CRC) CRC functional description 6.3.1 CRC block diagram Figure 7. CRC calculation unit block diagram 6.3.2 CRC internal signals Table 15. CRC internal input/output signals Signal name Signal type Description crc_hclk Digital input AHB clock 6.3.3 CRC operation The CRC calculation unit has a single 32-bit read/write data register (CRC_DR).
Page 90 Cyclic redundancy check calculation unit (CRC) RM0316 The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register. For example: input data 0x1A2B3C4D is used for CRC calculation as: 0x58D43CB2 with bit-reversal done by byte 0xD458B23C with bit-reversal done by half-word...
Page 91: Crc Registers
RM0316 Cyclic redundancy check calculation unit (CRC) CRC registers 6.4.1 Data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF DR[31:16] DR[15:0] Bits 31:0 DR[31:0]: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read.
Page 92: Control Register (Crc_Cr)
Cyclic redundancy check calculation unit (CRC) RM0316 6.4.3 Control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. REV_ Res. Res. Res. Res. Res. Res.
Page 93: Crc Polynomial (Crc_Pol)
RM0316 Cyclic redundancy check calculation unit (CRC) Bits 31:0 CRC_INIT: Programmable initial CRC value This register is used to write the CRC initial value. 6.4.5 CRC polynomial (CRC_POL) Address offset: 0x14 Reset value: 0x04C11DB7 POL[31:16] POL[15:0] Bits 31:0 POL[31:0]: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation.
Page 94: Power Control (Pwr)
Power control (PWR) RM0316 Power control (PWR) Power supplies An internal regulator is embedded in the STM32F3xx devices. • The internal regulator is enabled in the STM32F3xx MCUs: The STM32F303x6/8/B/C/D/E devices require a 2.0 V - 3.6 V operating supply voltage ) and a 2.0 V - 3.6 V analog supply voltage (V ).
Page 95: Figure 9. Power Supply Overview (Stm32F3X8 Devices)
RM0316 Power control (PWR) Figure 9. Power supply overview (STM32F3x8 devices) The following supply voltages are available: • and V : external power supply for I/Os and core. These supply voltages are provided externally through V and V pins. V = 2.0 to 3.6 V(STM32F303x6/8/B/C/D/E devices) or 1.8 V ±...
Page 96: Independent A/D And D/A Converter Supply And Reference Voltage
Power control (PWR) RM0316 7.1.1 Independent A/D and D/A converter supply and reference voltage To improve conversion accuracy, the ADC and the DAC have an independent power supply which can be separately filtered and shielded from noise on the PCB. The ADC and DAC voltage supply input is available on a separate VDDA pin.
Page 97: Voltage Regulator
RM0316 Power control (PWR) If no external battery is used in the application, it is recommended to connect V externally to V with a 100 nF external ceramic decoupling capacitor (for more details refer to AN4206). When the RTC domain is supplied by V (analog switch connected to V ), the following functions are available:...
Page 98: Figure 10. Power On Reset/Power Down Reset Waveform
Power control (PWR) RM0316 Figure 10. Power on reset/power down reset waveform 98/1141 DocID022558 Rev 8...
Page 99: Programmable Voltage Detector (Pvd)
RM0316 Power control (PWR) 7.2.2 Programmable voltage detector (PVD) User can use the PVD to monitor the V power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register (PWR_CR). The PVD is enabled by setting the PVDE bit. A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate if V...
Page 100: Low-Power Modes
Power control (PWR) RM0316 Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. Several low- power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event.
Page 101: Slowing Down System Clocks
RM0316 Power control (PWR) 7.3.1 Slowing down system clocks In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode. For more details refer to Section 9.4.2: Clock configuration register (RCC_CFGR).
Page 102: Stop Mode
Power control (PWR) RM0316 Table 18. Sleep-now Sleep-now mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 and Mode entry – SLEEPONEXIT = 0 ® ® Refer to the ARM Cortex -M4 System Control register. If WFI was used for entry: Interrupt: Refer to Table 82: STM32F303xB/C/D/E, STM32F358xC and...
Page 103 RM0316 Power control (PWR) If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB access is finished. In Stop mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option.
Page 104: Entering Standby Mode
Power control (PWR) RM0316 Table 20. Stop mode Stop mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® ® – Set SLEEPDEEP bit in ARM Cortex -M4 System Control register – Clear PDDS bit in Power Control register (PWR_CR) –...
Page 105: Table 21. Standby Mode
RM0316 Power control (PWR) Section 25.3: IWDG functional description Section 25: Independent watchdog (IWDG). • real-time clock (RTC): this is configured by the RTCEN bit in the RTC domain control register (RCC_BDCR) • Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR).
Page 106: Auto-Wakeup From Low-Power Mode
Power control (PWR) RM0316 7.3.6 Auto-wakeup from low-power mode The RTC can be used to wakeup the MCU from low-power mode without depending on an external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the RTC domain control register (RCC_BDCR):...
Page 107: Power Control Registers
RM0316 Power control (PWR) Power control registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 7.4.1 Power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) PLS[2:0] PVDE CSBF CWUF PDDS LPDS...
Page 108: Power Control/Status Register (Pwr_Csr)
Power control (PWR) RM0316 Bit 2 CWUF: Clear wakeup flag. This bit is always read as 0. 0: No effect 1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write) Bit 1 PDDS: Power down deepsleep. This bit is set and cleared by software. It works together with the LPDS bit. 0: Enter Stop mode when the CPU enters Deepsleep.
Page 109 RM0316 Power control (PWR) Bit 8 EWUP1: Enable WKUP1 pin This bit is set and cleared by software. 0: WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup the device from Standby mode. 1: WKUP1 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP1 pin wakes-up the system from Standby mode).
Page 110: Pwr Register Map
Power control (PWR) RM0316 7.4.3 PWR register map The following table summarizes the PWR registers. Table 22. PWR register map and reset values Offset Register PWR_CR PLS[2:0] 0x000 Reset value PWR_CSR 0x004 Reset value Refer to Section 3.2.2: Memory map and register boundary addresses for the register boundary addresses.
Page 111: Peripheral Interconnect Matrix
RM0316 Peripheral interconnect matrix Peripheral interconnect matrix Introduction Several STM32F3 peripherals have internal interconnections. Knowing these interconnections allows the following benefits: • Autonomous communication between peripherals, • Efficient synchronization between peripherals, • Discard the software latency and minimize GPIOs configuration, •...
Page 112 Peripheral interconnect matrix RM0316 Table 23. STM32F3xx peripherals interconnect matrix (continued) Destination 112/1141 DocID022558 Rev 8...
Page 113 RM0316 Peripheral interconnect matrix Table 23. STM32F3xx peripherals interconnect matrix (continued) Destination DocID022558 Rev 8 113/1141...
Page 114 Peripheral interconnect matrix RM0316 Table 23. STM32F3xx peripherals interconnect matrix (continued) Destination 114/1141 DocID022558 Rev 8...
Page 115: Interconnection Details
RM0316 Peripheral interconnect matrix 1. X means interconnect, and “-” means no interconnect. 2. Not in STM32F303x6/8 and STM32F328x8. 3. Only in STM32F303x6/8 and STM32F328x8. Interconnection details 8.3.1 DMA interconnections Hardware DMA requests are managed by peripherals. The DMA channels dedicated to each peripheral are summarized in Section 13.4.7: DMA request mapping.
Page 116: From Opamp To Adc
Peripheral interconnect matrix RM0316 The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event. The input (to ADC) is on signal EXT[15:0], JEXT[15:0]. The connection between timers and ADCs or also EXTI & ADCs is provided in: • Table 90: ADC1 (master) &...
Page 117: From Vrefint To Adc
RM0316 Peripheral interconnect matrix 8.3.8 From VREFINT to ADC VREFINT is internally connected to channel 18 of the four ADCs. This allows the monitoring of its value as described in Section 15.3.32: Monitoring the internal voltage reference. 8.3.9 From COMP to TIM The comparators outputs can be redirected internally to different timer inputs: •...
Page 118 Peripheral interconnect matrix RM0316 Table 27. Comparator outputs to timer inputs (continued) COMP output selection TIM1 TIM8 TIM2 TIM3 TIM4 TIM15 TIM16 TIM17 TIM20 Note: When the comparator output is configured to be connected internally to timers break input, the following must be considered: 1/ COMP1/2/3/5/6 can be used to control TIM1/8/20_BRK_ACTH (this break is always active high with no digital filter) and to control also TIM1/8/20_BRK2 input.
Page 119: From Tim To Comp
RM0316 Peripheral interconnect matrix 8.3.10 From TIM to COMP The timers output can be selected as comparators outputs blanking signals using the “COMPx_BLANKING” bits in “COMPx_CSR” register. More details on the blanking function can be found in Section 17.3.6: Comparator output blanking function.
Page 120: From Tim To Opamp
Peripheral interconnect matrix RM0316 Table 30. DAC output selection as OPAMP non inverting input Non inverting input OPAMP1 OPAMP3 OPAMP4 DAC channel DAC1_CH2 DAC1_CH2 DAC1_CH1 8.3.14 From TIM to OPAMP The switch between OPAMP inverting and non-inverting inputs can be done automatically. This automatic switch is triggered by the TIM1 CC6 output arriving on the OPAMP input multiplexers.
Page 121: From Break Input Sources To Tim
RM0316 Peripheral interconnect matrix Table 31. Timer synchronization SLAVE TIM1 TIM8 TIM20 TIM2 TIM3 TIM4 TIM15 TIM1 TIM8_ITR0 TIM20_ITR0 TIM2_ITR0 TIM3_ITR0 TIM4_ITR0 TIM8 TIM20_ITR1 TIM2_ITR1 TIM4_ITR3 TIM2 TIM1_ITR1 TIM8_ITR1 TIM3_ITR1 TIM4_ITR1 TIM15_ITR0 TIM3 TIM1_ITR2 TIM8_ITR3 TIM2_ITR2 TIM4_ITR2 TIM15_ITR1 TIM4 TIM1_ITR3 TIM8_ITR2 TIM20_ITR2 TIM2_ITR3...
Page 122: From Tim And Exti To Dac
Peripheral interconnect matrix RM0316 More details are provided in Section 9.2.14: Internal/external clock measurement with TIM16. 8.3.18 From TIM and EXTI to DAC A timer counter may be used as a trigger for DAC conversions. The TRGO event is the internal signal that will trigger conversion. The following table provides a summary of DACs interconnections with timers: This is described in Section 16.5.4: DAC trigger...
Page 123: Reset And Clock Control (Rcc)
RM0316 Reset and clock control (RCC) Reset and clock control (RCC) Reset There are three types of reset, defined as system reset, power reset and RTC domain reset. 9.1.1 Power reset A power reset is generated when one of the following events occurs: Power-on/power-down reset (POR/PDR reset) When exiting Standby mode A power reset sets all registers to their reset values except the RTC domain (see...
Page 124: Rtc Domain Reset
Reset and clock control (RCC) RM0316 Figure 12. Simplified diagram of the reset circuit Software reset ® The SYSRESETREQ bit in Cortex-M4 F Application Interrupt and Reset Control Register ® must be set to force a software reset on the device. Refer to the STM32F3xx/F4xx Cortex M4 programming manual (PM0214) for more details.
Page 125: Clocks
RM0316 Reset and clock control (RCC) The Backup registers are also reset when one of the following events occurs: RTC tamper detection event. Change of the read out protection from level 1 to level 0. Clocks Three different clock sources can be used to drive the system clock (SYSCLK): •...
Page 126: Figure 13. Stm32F303Xb/C And Stm32F358Xc Clock Tree
Reset and clock control (RCC) RM0316 ® The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock ® (HCLK) divided by 8. The SysTick can work either with this clock or directly with the Cortex clock (HCLK), configurable in the SysTick Control and Status Register. Figure 13.
Page 127: Figure 14. Stm32F303Xdxe And Stm32F398Xe Clock Tree
RM0316 Reset and clock control (RCC) is the PLL and the AHB and APB2 prescalers are set to ‘1’. 3. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). When the programmable factor is ‘1’, the AHB prescaler must be equal to ‘1’. Figure 14.
Page 128: Figure 15. Stm32F303X6/8 And Stm32F328X8 Clock Tree
Reset and clock control (RCC) RM0316 1. For full details about the internal and external clock source characteristics, please refer to the Electrical characteristics section in the device datasheet. 2. TIMx (x = 1/2/3/4/8/15/16/17/20) can be clocked from the PLL running at 144 MHz when the system clock source is the PLL and AHB or APB2 subsystem clocks are not divided by more than 2 cumulatively.
Page 129: Hse Clock
RM0316 Reset and clock control (RCC) ® FCLK acts as Cortex-M4 F free-running clock. For more details refer to the ® STM32F3xx/F4xx Cortex -M4 programming manual (PM0214). 9.2.1 HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: •...
Page 130: Hsi Clock
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T =25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 131: Pll
RM0316 Reset and clock control (RCC) The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or not. At startup, the HSI RC output clock is not released until this bit is set by hardware. The HSI RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR).
Page 132: Lsi Clock
Reset and clock control (RCC) RM0316 External source (LSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. Select this mode by setting the LSEBYP and LSEON bits in the RTC domain control register (RCC_BDCR).
Page 133: Adc Clock
RM0316 Reset and clock control (RCC) causes a switch of the system clock to the HSI oscillator and the disabling of the HSE oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.
Page 134: Watchdog Clock
Reset and clock control (RCC) RM0316 In this configuration: • On the STM32F303xB/C and STM32F358xC, AHB and APB2 prescalers are set to 1, i.e. AHB and APB2 clocks are not divided with respect to the system clock. • On the STM32F303xD/E, STM32F303x6/8 and STM32F328x8 AHB or APB2 subsystem clocks are not divided by more than 2 cumulatively with respect to the system clock.
Page 135: Internal/External Clock Measurement With Tim16
RM0316 Reset and clock control (RCC) 9.2.14 Internal/external clock measurement with TIM16 It is possible to indirectly measure the frequency of all on-board clock sources by mean of the TIM16 channel 1 input capture. As represented on Figure Figure 17. Frequency measurement with TIM16 in capture mode The input capture channel of the Timer 16 can be a GPIO line or an internal clock of the MCU.
Page 136: Low-Power Modes
Reset and clock control (RCC) RM0316 The basic concept consists in providing a relative measurement (e.g. the HSE/LSI ratio): the precision is therefore closely related to the ratio between the two clock sources. The higher the ratio is, the better the measurement will be. Low-power modes APB peripheral clocks and DMA clock can be disabled by software.
Page 137: Rcc Registers
RM0316 Reset and clock control (RCC) RCC registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. 9.4.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access PLLON HSICAL[7:0]...
Page 138: Clock Configuration Register (Rcc_Cfgr)
Reset and clock control (RCC) RM0316 Bit 16 HSEON: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:8 HSICAL[7:0]: HSI clock calibration...
Page 139 RM0316 Reset and clock control (RCC) Bit 31 PLLNODIV: Do not divide PLL to MCO (in STM32F303x6/8 and STM32F328x8 , STM32F303xDxE and STM32F398xE only) This bit is set and cleared by software. It switch-off divider-by-2 for PLL connection to MCO 0: PLL is divided by 2 before MCO 1: PLL is not divided before MCO Bits 30:28 MCOPRE: Microcontroller Clock Output Prescaler (in STM32F303x6/8 and STM32F328x8 ,...
Page 140 Reset and clock control (RCC) RM0316 Bits 21:18 PLLMUL: PLL multiplication factor These bits are written by software to define the PLL multiplication factor. These bits can be written only when PLL is disabled. Caution: The PLL output frequency must not exceed 72 MHz. 0000: PLL input clock x 2 0001: PLL input clock x 3 0010: PLL input clock x 4...
Page 141 RM0316 Reset and clock control (RCC) Bits 13:11 PPRE2: APB high-speed prescaler (APB2) Set and cleared by software to control the division factor of the APB2 clock (PCLK). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Bits 10:8 PPRE1: APB Low-speed prescaler (APB1)
Page 142: Clock Interrupt Register (Rcc_Cir)
Reset and clock control (RCC) RM0316 9.4.3 Clock interrupt register (RCC_CIR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access CSSC RDYC RDYC RDYC RDYC RDYC CSSF RDYIE RDYIE RDYIE RDYIE RDYIE RDYF RDYF RDYF RDYF...
Page 143 RM0316 Reset and clock control (RCC) Bit 11 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled Bit 10 HSIRDYIE: HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization.
Page 144: Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
Reset and clock control (RCC) RM0316 Bit 2 HSIRDYF: HSI ready interrupt flag Set by hardware when the HSI clock becomes stable and HSIRDYDIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.
Page 145 RM0316 Reset and clock control (RCC) Bit 17 TIM16RST: TIM16 timer reset Set and cleared by software. 0: No effect 1: Reset TIM16 timer Bit 16 TIM15RST: TIM15 timer reset Set and cleared by software. 0: No effect 1: Reset TIM15 timer Bit 15 SPI4RST: SPI4 reset (only onSTM32F303xD/E and STM32F398xE devices) Set and cleared by software.
Page 146: Reset And Clock Control (Rcc)
Reset and clock control (RCC) RM0316 9.4.5 APB1 peripheral reset register (RCC_APB1RSTR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access I2C3 I2C2 I2C1 UART5 UART4 USART3 USART2 DAC1 DAC2R SPI3 SPI2 TIM7 TIM6 TIM4 TIM3...
Page 147 RM0316 Reset and clock control (RCC) Bit 22 I2C2RST: I2C2 reset (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices only) Set and cleared by software. 0: No effect 1: Reset I2C2 Bit 21 I2C1RST: I2C1 reset Set and cleared by software. 0: No effect 1: Reset I2C1 Bit 20 UART5RST: UART5 reset (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices only)
Page 148: Ahb Peripheral Clock Enable Register (Rcc_Ahbenr)
Reset and clock control (RCC) RM0316 Bit 5 TIM7RST: TIM7 timer reset Set and cleared by software. 0: No effect 1: Reset TIM7 Bit 4 TIM6RST: TIM6 timer reset Set and cleared by software. 0: No effect 1: Reset TIM6 Bit 3 Reserved, must be kept at reset value.
Page 149 RM0316 Reset and clock control (RCC) Bits 31:30 Reserved, must be kept at reset value. Bit 29 ADC34EN: ADC3 and ADC4 enable (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices only) Set and reset by software. 0: ADC3 and ADC4 clock disabled 1: ADC3 and ADC4 clock enabled Bit 28 ADC12EN: ADC1 and ADC2 enable Set and reset by software.
Page 150: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
Reset and clock control (RCC) RM0316 Bit 16 IOPHEN: IO port H clock enable. (Only on STM32F303xDxE) Set and cleared by software. 0: IO port H clock disabled 1: IO port H clock enabled Bits 15:7 Reserved, must be kept at reset value. Bit 6 CRCEN: CRC clock enable Set and cleared by software.
Page 151 RM0316 Reset and clock control (RCC) TIM20 TIM17 TIM16 TIM15 TIM8 TIM1 SPI4E USART SPI1 CFGEN Bits 31:21 Reserved, must be kept at reset value. Bit 20 TIM20EN: TIM20 timer clock enable (STM32F303xD/E and STM32F398xE only) Set and cleared by software. 0: TIM20 timer clock disabled 1: TIM20 timer clock enabled Bit 19 Reserved, must be kept at reset value.
Page 152: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr)
Reset and clock control (RCC) RM0316 Bit 11 TIM1EN: TIM1 timer clock enable Set and cleared by software. 0: TIM1 timer clock disabled 1: TIM1 timer clock enabled Bits 10:1 Reserved, must be kept at reset value. Bit 0 SYSCFGEN: SYSCFG clock enable Set and cleared by software.
Page 153 RM0316 Reset and clock control (RCC) Bit 26 DAC2EN: DAC2 interface clock enable (STM32F303x6/8 and STM32F328x8 devices only) Set and cleared by software. 0: DAC2 interface clock disabled 1: DAC2 interface clock enabled Bit 25 CANEN: CAN clock enable Set and reset by software. 0: CAN clock disabled 1: CAN clock enabled Bit 24 Reserved, must be kept at reset value.
Page 154 Reset and clock control (RCC) RM0316 Bit 14 SPI2EN: SPI2 clock enable (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices only) Set and cleared by software. 0: SPI2 clock disabled 1: SPI2 clock enabled Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGEN: Window watchdog clock enable Set and cleared by software.
Page 155: Rtc Domain Control Register (Rcc_Bdcr)
RM0316 Reset and clock control (RCC) 9.4.9 RTC domain control register (RCC_BDCR) Address offset: 0x20 Reset value: 0x0000 0018h reset by RTC domain Reset. Access: 0 wait state 3, word, half-word and byte access ” ” Wait states are inserted in case of successive accesses to this register. Note: The LSEON, LSEBYP, RTCSEL and RTCEN bits of the RTC domain control register...
Page 156: Control/Status Register (Rcc_Csr)
Reset and clock control (RCC) RM0316 Bit 2 LSEBYP: LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable.
Page 157 RM0316 Reset and clock control (RCC) Bit 29 IWDGRSTF: Independent window watchdog reset flag Set by hardware when an independent watchdog reset from V domain occurs. Cleared by writing to the RMVF bit. 0: No watchdog reset occurred 1: Watchdog reset occurred Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs.
Page 158: Ahb Peripheral Reset Register (Rcc_Ahbrstr)
Reset and clock control (RCC) RM0316 9.4.11 AHB peripheral reset register (RCC_AHBRSTR) Address: 0x28 Reset value: 0x0000 0000 Access: no wait states, word, half-word and byte access IOPGR IOPHR ADC34 ADC12 IOPF IOPE IOPD IOPC IOPB IOPA FMCR 1. Only on STM32F303xDxE. Bits 31:30 Reserved, must be kept at reset value.
Page 159: Clock Configuration Register 2 (Rcc_Cfgr2)
RM0316 Reset and clock control (RCC) Bit 20 IOPDRST: I/O port D reset Set and cleared by software. 0: No effect 1: Reset I/O port D Bit 19 IOPCRST: I/O port C reset Set and cleared by software. 0: No effect 1: Reset I/O port C Bit 18 IOPBRST: I/O port B reset Set and cleared by software.
Page 160 Reset and clock control (RCC) RM0316 Bits 13:9 ADC34PRES: ADC34 prescaler (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE only) Set and reset by software to control PLL clock to ADC34 division factor. 0xxxx: ADC34 clock disabled, ADC34 can use AHB clock 10000: PLL clock divided by 1 10001: PLL clock divided by 2 10010: PLL clock divided by 4 10011: PLL clock divided by 6...
Page 161 RM0316 Reset and clock control (RCC) Bits 3:0 PREDIV: PREDIV division factor These bits are set and cleared by software to select PREDIV division factor. They can be written only when the PLL is disabled. Note: Bit 0 is the same bit as bit17 in Clock configuration register (RCC_CFGR), so modifying bit17...
Page 162: Clock Configuration Register 3 (Rcc_Cfgr3)
Reset and clock control (RCC) RM0316 9.4.13 Clock configuration register 3 (RCC_CFGR3) Address: 0x30 Reset value: 0x0000 0000 Access: no wait states, word, half-word and byte access TIM34 TIM2 USART3SW[1:0] USART2SW[1:0] UART5SW[1:0] UART4SW[1:0] TIM20 TIM17 TIM16 TIM15 I2C3 TIM8S TIM1 I2C2 I2C1 USART1SW[1:0]...
Page 163 RM0316 Reset and clock control (RCC) Bits 19:18 USART3SW[1:0]: USART3 clock source selection This bit is set and cleared by software to select the USART3 clock source. 00: PCLK selected as USART3 clock source (default) 01: System clock (SYSCLK) selected as USART3 clock 10: LSE clock selected as USART3 clock 11: HSI clock selected as USART3 clock Note:...
Page 164 Reset and clock control (RCC) RM0316 Bit 10 TIM15SW: Timer15 clock source selection Set and reset by software to select TIM15 clock source. The bit is writable only when the following conditions occur: system clock source is the PLL and AHB or APB2 subsystem clocks are not divided by more than 2 cumulatively. The bit is reset by hardware when exiting from the previous condition (user must set the bit again in case of a new switch is required) 0: PCLK2 clock (doubled frequency when prescaled) (default)
Page 165 RM0316 Reset and clock control (RCC) Bit 4 I2C1SW: I2C1 clock source selection This bit is set and cleared by software to select the I2C1 clock source. 0: HSI clock selected as I2C1 clock source (default) 1: SYSCLK clock selected as I2C1 clock Bits 3:2 Reserved, must be kept at reset value.
Page 166: Rcc Register Map
Reset and clock control (RCC) RM0316 9.4.14 RCC register map The following table gives the RCC register map and the reset values. Table 33. RCC register map and reset values Offset Register RCC_CR HSICAL[7:0] HSITRIM[4:0] 0x00 Reset value PLLMUL[3:0 PPRE2 PPRE1 RCC_CFGR HPRE[3:0]...
Page 167 RM0316 Reset and clock control (RCC) Table 33. RCC register map and reset values (continued) Offset Register RCC_BDCR 0x20 [1:0] [1:0] Reset value RCC_CSR 0x24 Reset value RCC_AHBRSTR 0x28 Reset value ADC34PRES ADC12PRES RCC_CFGR2 PREDIV[3:0] [4:0] [4:0] 0x2C Reset value RCC_CFGR3 0x30 Reset value...
Page 168: Flexible Static Memory Controller (Fsmc)
Flexible static memory controller (FSMC) RM0316 Flexible static memory controller (FSMC) Note: Only the STM32F303xD/E and STM32F398xE devices include the FSMC. The Flexible static memory controller (FSMC) includes two memory controllers: • The NOR/PSRAM memory controller • The NAND/PC Card memory controller This memory controller is also named Flexible memory controller (FMC).
Page 169: Block Diagram
RM0316 Flexible static memory controller (FSMC) when crossing a page boundary (for PSRAM). In this case, the AHB burst is broken into two FIFO entries. At startup the FMC pins must be configured by the user application. The FMC I/O pins which are not used by the application can be used for other purposes.
Page 170: Ahb Interface
Flexible static memory controller (FSMC) RM0316 10.3 AHB interface The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses.
Page 171: External Device Address Mapping
RM0316 Flexible static memory controller (FSMC) Therefore, some simple transaction rules must be followed: • AHB transaction size and memory data size are equal There is no issue in this case. • AHB transaction size is greater than the memory size: In this case, the FMC splits the AHB transaction into smaller consecutive memory accesses to meet the external data width.
Page 172: Nor/Psram Address Mapping
Flexible static memory controller (FSMC) RM0316 Figure 19. FMC memory banks 10.4.1 NOR/PSRAM address mapping HADDR[27:26] bits are used to select one of the four memory banks as shown in Table Table 34. NOR/PSRAM bank selection HADDR[27:26] Selected bank Bank 1 - NOR/PSRAM 1 Bank 1 - NOR/PSRAM 2 Bank 1 - NOR/PSRAM 3 Bank 1 - NOR/PSRAM 4...
Page 173: Nand Flash Memory/Pc Card Address Mapping
RM0316 Flexible static memory controller (FSMC) 1. In case of a 16-bit external memory width, the FMC will internally use HADDR[25:1] to generate the address for external memory FMC_A[24:0]. Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0]. Wrap support for NOR Flash/PSRAM Wrap burst mode for synchronous memories is not supported.
Page 174: Nor Flash/Psram Controller
Flexible static memory controller (FSMC) RM0316 consecutive write operations to the address section are required to specify the full address. • To read or write data, the software reads or writes the data from/to any memory location in the data section. Since the NAND Flash memory automatically increments addresses, there is no need to increment the address of the data section to access consecutive memory locations.
Page 175: External Memory Interface Signals
RM0316 Flexible static memory controller (FSMC) The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through dedicated registers (see Section 10.5.6: NOR/PSRAM controller registers). The programmable memory parameters include access times (see Table 38) and support for wait management (for PSRAM and NOR Flash accessed in burst mode).
Page 176: Table 40. 16-Bit Multiplexed I/O Nor Flash Memory
Flexible static memory controller (FSMC) RM0316 NOR Flash memory, 16-bit multiplexed I/Os Table 40. 16-bit multiplexed I/O NOR Flash memory FMC signal name Function Clock (for synchronous access) A[25:16] Address bus 16-bit multiplexed, bidirectional address/data bus (the 16-bit address AD[15:0] A[15:0] and data D[15:0] are multiplexed on the databus) NE[x] Chip Select, x = 1..4...
Page 177: Supported Memories And Transactions
RM0316 Flexible static memory controller (FSMC) 16-Bit Table 42. multiplexed I/O PSRAM (continued) FMC signal name Function 16-bit multiplexed, bidirectional address/data bus (the 16-bit address AD[15:0] A[15:0] and data D[15:0] are multiplexed on the databus) Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. NE[x] CRAM)) Output enable...
Page 178: General Timing Rules
Flexible static memory controller (FSMC) RM0316 Table 43. NOR Flash/PSRAM: Example of supported memories and transactions (continued) Allowed/ Memory Device Mode data Comments data size size allowed Asynchronous Asynchronous Use of byte lanes NBL[1:0] Asynchronous Asynchronous Asynchronous Split into 2 FMC accesses PSRAM Asynchronous Split into 2 FMC accesses...
Page 179: Nor Flash/Psram Controller Asynchronous Transactions
RM0316 Flexible static memory controller (FSMC) 10.5.4 NOR Flash/PSRAM controller asynchronous transactions Asynchronous static memories (NOR Flash, PSRAM, SRAM) • Signals are synchronized by the internal clock HCLK. This clock is not issued to the memory • The FMC always samples the data before de-asserting the NOE signal. This guarantees that the memory data hold timing constraint is met (minimum Chip Enable high to data transition is usually 0 ns) •...
Page 180: Table 44. Fmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0316 Figure 21. Mode1 write access waveforms The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the DATAST value must be greater than zero (DATAST >...
Page 181: Table 45. Fmc_Btrx Bit Fields
RM0316 Flexible static memory controller (FSMC) Table 44. FMC_BCRx bit fields (continued) Bit name Value to set number MUXE MBKEN Table 45. FMC_BTRx bit fields Bit name Value to set number 31:30 Reserved 29-28 ACCMOD Don’t care 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care...
Page 182: Figure 22. Modea Read Access Waveforms
Flexible static memory controller (FSMC) RM0316 Mode A - SRAM/PSRAM (CRAM) OE toggling Figure 22. ModeA read access waveforms 1. NBL[1:0] are driven low during the read access Figure 23. ModeA write access waveforms 182/1141 DocID022558 Rev 8...
Page 183: Table 46. Fmc_Bcrx Bit Fields
RM0316 Flexible static memory controller (FSMC) The differences compared with mode1 are the toggling of NOE and the independent read and write timings. Table 46. FMC_BCRx bit fields Bit name Value to set number 31-21 Reserved 0x000 CCLKEN As needed CBURSTRW 0x0 (no effect in asynchronous mode) 18:16...
Page 184: Table 48. Fmc_Bwtrx Bit Fields
Flexible static memory controller (FSMC) RM0316 Table 48. FMC_BWTRx bit fields Bit name Value to set number 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST HCLK cycles) for write 15-8 DATAST...
Page 185: Figure 25. Mode2 Write Access Waveforms
RM0316 Flexible static memory controller (FSMC) Figure 25. Mode2 write access waveforms Figure 26. ModeB write access waveforms The differences with mode1 are the toggling of NWE and the independent read and write timings when extended mode is set (Mode B). DocID022558 Rev 8 185/1141...
Page 186: Table 49. Fmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0316 Table 49. FMC_BCRx bit fields Bit name Value to set number 31-21 Reserved 0x000 CCLKEN As needed CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 Reserved Set to 1 if the memory supports this feature. Otherwise keep at ASYNCWAIT EXTMOD 0x1 for mode B, 0x0 for mode 2...
Page 187: Table 51. Fmc_Bwtrx Bit Fields
RM0316 Flexible static memory controller (FSMC) Table 51. FMC_BWTRx bit fields Bit number Bit name Value to set 31-30 Reserved 29-28 ACCMOD 0x1 if extended mode is set 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) Duration of the access second phase (DATAST HCLK cycles) for 15-8 DATAST...
Page 188: Table 52. Fmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0316 Figure 28. ModeC write access waveforms The differences compared with mode1 are the toggling of NOE and the independent read and write timings. Table 52. FMC_BCRx bit fields Bit No. Bit name Value to set 31-21 Reserved 0x000...
Page 189: Table 53. Fmc_Btrx Bit Fields
RM0316 Flexible static memory controller (FSMC) Table 52. FMC_BCRx bit fields (continued) Bit No. Bit name Value to set MUXEN MBKEN Table 53. FMC_BTRx bit fields Bit No. Bit name Value to set 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT 23-20 CLKDIV 19-16 BUSTURN...
Page 190: Figure 29. Moded Read Access Waveforms
Flexible static memory controller (FSMC) RM0316 Mode D - asynchronous access with extended address Figure 29. ModeD read access waveforms Figure 30. ModeD write access waveforms 190/1141 DocID022558 Rev 8...
Page 191: Table 55. Fmc_Bcrx Bit Fields
RM0316 Flexible static memory controller (FSMC) The differences with mode1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings. Table 55. FMC_BCRx bit fields Bit No. Bit name Value to set 31-21 Reserved 0x000...
Page 192: Table 57. Fmc_Bwtrx Bit Fields
Flexible static memory controller (FSMC) RM0316 Table 57. FMC_BWTRx bit fields Bit No. Bit name Value to set 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST + 1 HCLK cycles) for 15-8 DATAST...
Page 193: Table 58. Fmc_Bcrx Bit Fields
RM0316 Flexible static memory controller (FSMC) Figure 32. Muxed write access waveforms The difference with mode D is the drive of the lower address byte(s) on the data bus. Table 58. FMC_BCRx bit fields Bit No. Bit name Value to set 31-21 Reserved 0x000...
Page 194: Table 59. Fmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0316 Table 58. FMC_BCRx bit fields (continued) Bit No. Bit name Value to set MUXEN MBKEN Table 59. FMC_BTRx bit fields Bit No. Bit name Value to set 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care...
Page 195: Figure 33. Asynchronous Wait During A Read Access Waveforms
RM0316 Flexible static memory controller (FSMC) The memory asserts the WAIT signal aligned to NOE/NWE which toggles: ≥ × DATAST HCLK max_wait_assertion_time The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): > max_wait_assertion_time address_phase hold_phase then: ≥...
Page 196: Synchronous Transactions
Flexible static memory controller (FSMC) RM0316 Figure 34. Asynchronous wait during a write access waveforms 1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register. 10.5.5 Synchronous transactions The memory clock, FMC_CLK, is a submultiple of HCLK. It depends on the value of CLKDIV and the MWID/ AHB data size, following the formula given below: FMC_CLK divider ratio max CLKDIV...
Page 197 RM0316 Flexible static memory controller (FSMC) Caution: Some NOR Flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR Flash latency and the FMC DATLAT parameter can be either: • NOR Flash latency = (DATLAT + 2) CLK clock cycles •...
Page 198: Figure 35. Wait Configuration Waveforms
Flexible static memory controller (FSMC) RM0316 Figure 35. Wait configuration waveforms 198/1141 DocID022558 Rev 8...
Page 199: Flexible Static Memory Controller (Fsmc)
RM0316 Flexible static memory controller (FSMC) Figure 36. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) 1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low. Table 60.
Page 200: Table 61. Fmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0316 Table 60. FMC_BCRx bit fields (continued) Bit No. Bit name Value to set WRAPMOD WAITPOL to be set according to memory BURSTEN Reserved FACCEN Set according to memory support (NOR Flash memory) MWID As needed MTYP 0x1 or 0x2 MUXEN...
Page 201: Table 62. Fmc_Bcrx Bit Fields
RM0316 Flexible static memory controller (FSMC) Figure 37. Synchronous multiplexed write mode waveforms - PSRAM (CRAM) 1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0. 2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active. Table 62.
Page 202: Table 63. Fmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0316 Table 62. FMC_BCRx bit fields (continued) Bit No. Bit name Value to set WRAPMOD WAITPOL to be set according to memory BURSTEN no effect on synchronous write Reserved FACCEN Set according to memory support MWID As needed MTYP...
Page 203: Nor/Psram Controller Registers
RM0316 Flexible static memory controller (FSMC) 10.5.6 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control registers 1..4 (FMC_BCR1..4) Address offset: 8 * (x – 1), x = 1...4 Reset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.
Page 204 Flexible static memory controller (FSMC) RM0316 Bit 14 EXTMOD: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. 0: values inside FMC_BWTR register are not taken into account (default after reset) 1: values inside FMC_BWTR register are taken into account Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: –...
Page 205 RM0316 Flexible static memory controller (FSMC) Bits 5:4 MWID: Memory data bus width. Defines the external memory device width, valid for all type of memories. 00: 8 bits 01: 16 bits (default after reset) 10: reserved, do not use 11: reserved, do not use Bits 3:2 MTYP: Memory type.
Page 206 Flexible static memory controller (FSMC) RM0316 Bits 31:30 Reserved, must be kept at reset value Bits 29:28 ACCMOD: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 00: access mode A 01: access mode B 10: access mode C...
Page 207 RM0316 Flexible static memory controller (FSMC) Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read (and read-to- write) transaction. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ).
Page 208 Flexible static memory controller (FSMC) RM0316 Bits 15:8 DATAST: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 20 Figure 32), used in asynchronous accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 1 × HCLK clock cycles 0000 0010: DATAST phase duration = 2 ×...
Page 209 RM0316 Flexible static memory controller (FSMC) SRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4) Address offset: 0x104 + 8 * (x – 1), x = 1...4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories.
Page 210: Nand Flash/Pc Card Controller
Flexible static memory controller (FSMC) RM0316 Bits 15:8 DATAST: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 20 Figure 32), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 1 ×...
Page 211: External Memory Interface Signals
RM0316 Flexible static memory controller (FSMC) Table 64. Programmable NAND Flash/PC Card access parameters Parameter Function Access mode Unit Min. Max. Number of clock cycles (HCLK) Memory setup AHB clock cycle required to set up the address Read/Write time (HCLK) before the command assertion Minimum duration (in HCLK clock AHB clock cycle...
Page 212: Table 66. 16-Bit Nand Flash
Flexible static memory controller (FSMC) RM0316 16-bit NAND Flash memory Table 66. 16-bit NAND Flash FMC signal name Function A[17] NAND Flash address latch enable (ALE) signal A[16] NAND Flash command latch enable (CLE) signal D[15:0] 16-bit multiplexed, bidirectional address/data bus NCE[x] Chip Select, x = 2, 3 NOE(= NRE)
Page 213: Nand Flash / Pc Card Supported Memories And Transactions
RM0316 Flexible static memory controller (FSMC) 10.6.2 NAND Flash / PC Card supported memories and transactions Table 68 shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND Flash / PC Card controller are shown in gray. Table 68.
Page 214: Nand Flash Operations
Flexible static memory controller (FSMC) RM0316 Figure 38. NAND Flash/PC Card controller waveforms for common memory access 1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses. 2. For write access, the hold phase delay is (MEMHOLD) HCLK cycles and for read access is (MEMHOLD + 2) HCLK cycles.
Page 215: Nand Flash Prewait Functionality
RM0316 Flexible static memory controller (FSMC) to implement the prewait functionality needed by some NAND Flash memories (see details in Section 10.6.5: NAND Flash prewait functionality). The controller waits for the NAND Flash memory to be ready (R/NB signal high), before starting a new access to the same or another memory bank.
Page 216: Computation Of The Error Correction Code (Ecc) In Nand Flash Memory
Flexible static memory controller (FSMC) RM0316 When this functionality is required, it can be ensured by programming the MEMHOLD value to meet the t timing. However any CPU read access to the NAND Flash memory has a hold delay of (MEMHOLD + 2) HCLK cycles and CPU write access has a hold delay of (MEMHOLD) HCLK cycles inserted between the rising edge of the NWE signal and the next access.
Page 217: Pc Card/Compactflash Operations
RM0316 Flexible static memory controller (FSMC) To perform an ECC computation: Enable the ECCEN bit in the FMC_PCR2/3 register. Write data to the NAND Flash memory page. While the NAND page is written, the ECC block computes the ECC value. Read the ECC value available in the FMC_ECCR2/3 register and store it in a variable.
Page 218: Table 69. 16-Bit Pc-Card Signals And Access Type
Flexible static memory controller (FSMC) RM0316 transfers at even addresses: nCE1 will be asserted low, NCE2 will be asserted high and only the even bytes will be valid. • Accesses to I/O space can be either 8-bit or 16 bit AHB accesses. Table 69.
Page 219: Nand Flash/Pc Card Controller Registers
RM0316 Flexible static memory controller (FSMC) PWAITEN bit in the FMC_PCRx register. To detect correctly the nWAIT assertion, the MEMWAITx/ATTWAITx/IOWAITx bits must be programmed as follows: max_wait_assertion_time ≥ xxWAITx ------------------------------------------------------------------ - HCLK where max_wait_assertion_time is the maximum time taken by NWAIT to go low once nOE/nWE or nIORD/nIOWR is low.
Page 220 Flexible static memory controller (FSMC) RM0316 Bits 5:4 PWID: Data bus width. Defines the external memory device width. 00: 8 bits 01: 16 bits (default after reset). This value is mandatory for PC Cards. 10: reserved, do not use 11: reserved, do not use Bit 3 PTYP: Memory type.
Page 221 RM0316 Flexible static memory controller (FSMC) Bit 6 FEMPT: FIFO empty. Read-only bit that provides the status of the FIFO 0: FIFO not empty 1: FIFO empty Bit 5 IFEN: Interrupt falling edge detection enable bit 0: Interrupt falling edge detection request disabled 1: Interrupt falling edge detection request enabled Bit 4 ILEN: Interrupt high-level detection enable bit 0: Interrupt high-level detection request disabled...
Page 222 Flexible static memory controller (FSMC) RM0316 Bits 31:24 MEMHIZx: Common memory x data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the start of a PC Card/NAND Flash write access to common memory space on socket x. This is only valid for write transactions: 0000 0000: (0x00) 0 HCLK cycle (for PC Card) / 1 HCLK cycle (for NAND Flash) 1111 1110: (0xFF) 255 HCLK cycles (for PC Card) / 256 HCLK cycles (for NAND Flash)
Page 223 RM0316 Flexible static memory controller (FSMC) Bits 31:24 ATTHIZ: Attribute memory x data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a PC CARD/NAND Flash write access to attribute memory space on socket x. Only valid for write transaction: 0000 0000: 0 HCLK cycle 1111 1110: 255 HCLK cycles...
Page 224 Flexible static memory controller (FSMC) RM0316 Bits 31:24 IOHIZx: I/O x data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a PC Card write access to I/O space on socket x. Only valid for write transaction: 0000 0000: 0 HCLK cycle 1111 1111: 255 HCLK cycles Bits 23:16 IOHOLDx: I/O x hold time...
Page 225: Table 70. Ecc Result Relevant Bits
RM0316 Flexible static memory controller (FSMC) ECC result registers 2/3 (FMC_ECCR2/3) Address offset: 0x54 + 0x20 * (x – 1), x = 2 or 3 Reset value: 0x0000 0000 These registers contain the current error correction code value computed by the ECC computation modules of the FMC controller (one module per NAND Flash memory bank).
Page 226: Flexible Static Memory Controller (Fsmc)
Flexible static memory controller (FSMC) RM0316 10.7 FMC register map The following table summarizes the FMC registers. Table 71. FMC register map Offset Register 0x00 FMC_BCR1 0x08 FMC_BCR2 0x10 FMC_BCR3 0x18 FMC_BCR4 ACCM 0x04 FMC_BTR1 DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET ACCM 0x0C...
Page 227 RM0316 Flexible static memory controller (FSMC) Table 71. FMC register map (continued) Offset Register 0x68 FMC_PMEM2 MEMHIZx MEMHOLDx MEMWAITx MEMSETx 0x88 FMC_PMEM3 MEMHIZx MEMHOLDx MEMWAITx MEMSETx 0xA8 FMC_PMEM4 MEMHIZx MEMHOLDx MEMWAITx MEMSETx 0x6C FMC_PATT2 ATTHIZx ATTHOLDx ATTWAITx ATTSETx 0x8C FMC_PATT3 ATTHIZx ATTHOLDx ATTWAITx...
Page 228: General-Purpose I/Os (Gpio)
General-purpose I/Os (GPIO) RM0316 General-purpose I/Os (GPIO) 11.1 Introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).
Page 229: Figure 40. Basic Structure Of An I/O Port Bit
RM0316 General-purpose I/Os (GPIO) GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read and the modify access. Figure 40 Figure 41 show the basic structures of a standard and a 5 V tolerant I/O port bit, respectively.
Page 230: Table 72. Port Bit Configuration Table
General-purpose I/Os (GPIO) RM0316 Table 72. Port bit configuration table MODER(i) OSPEEDR(i) PUPDR(i) OTYPER(i) I/O configuration [1:0] [1:0] [1:0] GP output GP output PP + PU GP output PP + PD Reserved SPEED [1:0] GP output GP output OD + PU GP output OD + PD Reserved (GP output OD)
Page 231: General-Purpose I/O (Gpio)
RM0316 General-purpose I/Os (GPIO) 11.3.1 General-purpose I/O (GPIO) During and just after reset, the alternate functions are not active and most of the I/O ports are configured in input floating mode. The debug pins are in AF pull-up/pull-down after reset: •...
Page 232: I/O Port Control Registers
General-purpose I/Os (GPIO) RM0316 – For the ADC, DAC, OPAMP, and COMP, configure the desired I/O in analog mode in the GPIOx_MODER register and configure the required function in the ADC, DAC, OPAMP, and COMP registers. – For the additional functions like RTC, WKUPx and oscillators, configure the required function in the related RTC, PWR and RCC registers.
Page 233: Gpio Locking Mechanism
RM0316 General-purpose I/Os (GPIO) 11.3.6 GPIO locking mechanism It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same).
Page 234: Output Configuration
General-purpose I/Os (GPIO) RM0316 Figure 42. Input floating/pull up/pull down configurations 11.3.10 Output configuration When the I/O port is programmed as output: • The output buffer is enabled: – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated) –...
Page 235: Alternate Function Configuration
RM0316 General-purpose I/Os (GPIO) Figure 43. Output configuration 11.3.11 Alternate function configuration When the I/O port is programmed as alternate function: • The output buffer can be configured in open-drain or push-pull mode • The output buffer is driven by the signals coming from the peripheral (transmitter enable and data) •...
Page 236: Analog Configuration
General-purpose I/Os (GPIO) RM0316 11.3.12 Analog configuration When the I/O port is programmed as analog configuration: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). •...
Page 237: Gpio Registers
RM0316 General-purpose I/Os (GPIO) 11.4 GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table The peripheral registers can be written in word, half word or byte mode. 11.4.1 GPIO port mode register (GPIOx_MODER) (x =A..H) Address offset:0x00...
Page 238: Gpio Port Output Speed Register (Gpiox_Ospeedr)
General-purpose I/Os (GPIO) RM0316 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 OTy: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type. 0: Output push-pull (reset state) 1: Output open-drain 11.4.3 GPIO port output speed register (GPIOx_OSPEEDR)
Page 239: Gpio Port Input Data Register (Gpiox_Idr) (X = A..h
RM0316 General-purpose I/Os (GPIO) Bits 2y+1:2y PUPDRy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down 00: No pull-up, pull-down 01: Pull-up 10: Pull-down 11: Reserved 11.4.5 GPIO port input data register (GPIOx_IDR) (x = A..H) Address offset: 0x10 Reset value: 0x0000 XXXX (where X means undefined) Res.
Page 240: Gpio Port Bit Set/Reset Register (Gpiox_Bsrr) (X = A..h
General-purpose I/Os (GPIO) RM0316 11.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..H) Address offset: 0x18 Reset value: 0x0000 0000 BR15 BR14 BR13 BR12 BR11 BR10 BS15 BS14 BS13 BS12 BS11 BS10 Bits 31:16 BRy: Port x reset bit y (y = 0..15) These bits are write-only.
Page 241: Gpio Alternate Function Low Register (Gpiox_Afrl)
RM0316 General-purpose I/Os (GPIO) Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active.
Page 242: Gpio Alternate Function High Register (Gpiox_Afrh)
General-purpose I/Os (GPIO) RM0316 11.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..H) Address offset: 0x24 Reset value: 0x0000 0000 AFR15[3:0] AFR14[3:0] AFR13[3:0] AFR12[3:0] AFR11[3:0] AFR10[3:0] AFR9[3:0] AFR8[3:0] Bits 31:0 AFRy[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFRy selection: 1000: AF8...
Page 243: Gpio Register Map
RM0316 General-purpose I/Os (GPIO) 11.4.12 GPIO register map The following table gives the GPIO register map and reset values. Table 73. GPIO register map and reset values Offset Register GPIOA_MODER 0x00 Reset value GPIOB_MODER 0x00 Reset value GPIOx_MODER (where x = C..H) 0x00 Reset value GPIOx_OTYPER...
Page 244 General-purpose I/Os (GPIO) RM0316 Table 73. GPIO register map and reset values (continued) Offset Register GPIOB_PUPDR 0x0C Reset value GPIOx_IDR (where x = A..H) 0x10 Reset value GPIOx_ODR (where x = A..H) 0x14 Reset value GPIOx_BSRR (where x = A..H) 0x18 Reset value GPIOx_LCKR...
Page 245: System Configuration Controller (Syscfg)
RM0316 System configuration controller (SYSCFG) System configuration controller (SYSCFG) The STM32F3xx devices feature a set of configuration registers. The main purposes of the system configuration controller are the following: • Enabling/disabling I C Fm+ on some I/O ports • Remapping some DMA trigger sources from TIM16, TIM17, TIM6, DAC1_CH1, and DAC1_CH2,TIM7, and ADC4 to different DMA channels (also SPI1, I2C1, ADC2 in STM32F303x6/8 and STM32F328x8) •...
Page 246 System configuration controller (SYSCFG) RM0316 Bits 31:26 FPU_IE[5..0]: Floating Point Unit interrupts enable bits FPU_IE[5]: Inexact interrupt enable FPU_IE[4]: Input normal interrupt enable FPU_IE[3]: Overflow interrupt enable FPU_IE[2]: underflow interrupt enable FPU_IE[1]: Divide-by-zero interrupt enable FPU_IE[0]: Invalid operation interrupt enable Bit 25: Reserved, must be kept at reset value.
Page 247 RM0316 System configuration controller (SYSCFG) Bit 14 TIM7_DAC1_CH2_DMA_RMP: TIM7 and DAC channel2 DMA remap This bit is set and cleared by software. It controls the remapping of TIM7(UP) and DAC channel2 DMA request. 0: No remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA2 channel 4 in STM32F303xB/C and STM32F358xC devices) 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) Note: In STM32F303x6/8 and STM32F328x8, this bit must be set as there is no DMA2 in...
Page 248: Syscfg Ccm Sram Protection Register (Syscfg_Rcr)
System configuration controller (SYSCFG) RM0316 Bit 5 USB_IT_RMP: USB interrupt remap (STM32F303xB/C/D/E devices only) This bit is set and cleared by software. It controls the USB interrupts mapping. 0: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively.
Page 249: Syscfg External Interrupt Configuration Register 1
RM0316 System configuration controller (SYSCFG) 12.1.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] Bits 31:16 Reserved, must be kept at reset value.
Page 250: Syscfg External Interrupt Configuration Register 2
System configuration controller (SYSCFG) RM0316 Bits 11:8 EXTI2[3:0]: EXTI 2 configuration bits These bits are written by software to select the source input for the EXTI2 external interrupt. x000: PA[2] pin x001: PB[2] pin x010: PC[2] pin x011: PD[2] pin x100: PE[2] pin x101: PF[2] pin x110:PG[2] pin...
Page 251 RM0316 System configuration controller (SYSCFG) Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 EXTI7[3:0]: EXTI 7 configuration bits These bits are written by software to select the source input for the EXTI7 external interrupt. x000: PA[7] pin x001: PB[7] pin x010: PC[7] pin x011: PD[7] pin...
Page 252: Syscfg External Interrupt Configuration Register 3
System configuration controller (SYSCFG) RM0316 12.1.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 EXTI11[3:0]: EXTI 11 configuration bits These bits are written by software to select the source input for the EXTI11 external interrupt.
Page 253 RM0316 System configuration controller (SYSCFG) Bits 11:8 EXTI10[3:0]: EXTI 10 configuration bits These bits are written by software to select the source input for the EXTI10 external interrupt. x000: PA[10] pin x001: PB[10] pin x010: PC[10] pin x011:PD[10] pin x100:PE[10] pin x101:PF[10] pin x110:PG[10] pin other configurations: reserved...
Page 254: Syscfg External Interrupt Configuration Register 4
System configuration controller (SYSCFG) RM0316 12.1.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] Bits 31:16 Reserved, must be kept at reset value.
Page 255: Syscfg Configuration Register 2 (Syscfg_Cfgr2)
RM0316 System configuration controller (SYSCFG) Bits 11:8 EXTI14[3:0]: EXTI14 configuration bits These bits are written by software to select the source input for the EXTI14 external interrupt. x000: PA[14] pin x001: PB[14] pin x010: PC[14] pin x011: PD[14] pin x100: PE[14] pin x101:PF[14] pin x110:PG[14] pin Other configurations: reserved...
Page 256 System configuration controller (SYSCFG) RM0316 Bits 31:9 Reserved, must be kept at reset value Bit 8 SRAM_PEF: SRAM parity error flag This bit is set by hardware when an SRAM parity error is detected. It is cleared by software by writing ‘1’. 0: No SRAM parity error detected 1: SRAM parity error detected Bits 7:5 Reserved, must be kept at reset value...
Page 257: Syscfg Configuration Register 3 (Syscfg_Cfgr3)
RM0316 System configuration controller (SYSCFG) 12.1.8 SYSCFG configuration register 3 (SYSCFG_CFGR3) Note: This register is available in STM32F303x6/x8 and STM32F328 devices only. Address offset: 0x50 System reset value: 0x0000 0200 ADC2_DMA_ I2C1_TX_DMA_ I2C1_RX_DMA_ SPI1_TX_DMA_ SPI1_RX_DMA_ Bits 31:10 Reserved, must be kept at reset value Bit 9 ADC2_DMA_RMP[1]: ADC2 DMA controller remapping bit 0: ADC2 mapped on DMA2 1: ADC2 mapped on DMA1...
Page 258: System Configuration Controller (Syscfg)
System configuration controller (SYSCFG) RM0316 Bits 5:4 I2C1_RX_DMA_RMP: I2C1_RX DMA remapping bit This bit is set and cleared by software. It defines on which DMA1 channel I2C1_RX is mapped. 00: I2C1_RX mapped on DMA1 CH7 01: I2C1_RX mapped on DMA1 CH3 10: I2C1_RX mapped on DMA1 CH5 11: I2C1_RX mapped on DMA1 CH7 Bits 3:2 SPI1_TX_DMA_RMP: SPI1_TX DMA remapping bit...
Page 259 RM0316 System configuration controller (SYSCFG) Bits 31:14 Reserved, must be kept at reset value Bit 13 ADC34_JEXT14_RMP - Controls the Input trigger of ADC34 injected channel JEXT14: 0: Trigger source is TIM7_TRGO 1: Trigger source is TIM20_CC2 Bit 12 ADC34_JEXT11_RMP - Controls the Input trigger of ADC34 injected channel JEXT11: 0: Trigger source is TIM1_CC3 1: Trigger source is TIM20_TRGO2...
Page 260 System configuration controller (SYSCFG) RM0316 Bit 2 ADC12_EXT5_RMP - Controls the Input trigger of ADC12 regular channel EXT5 0: Trigger source is TIM4_CC4 1: Trigger source is TIM20_CC1 Bit 1 ADC12_EXT3_RMP - Controls the Input trigger of ADC12 regular channel EXT3: 0: Trigger source is TIM2_CC2 1: Trigger source is TIM20_TRGO2 Bit 0 ADC12_EXT2_RMP - Controls the Input trigger of ADC12 regular channel EXT2:...
Page 261: Syscfg Register Map
RM0316 System configuration controller (SYSCFG) 12.1.10 SYSCFG register map The following table gives the SYSCFG register map and the reset values. Table 74. SYSCFG register map and reset values Offset Register SYSCFG_CFGR1 FPU_IE[5..0] 0x00 Reset value SYSCFG_RCR PAGE[15:0]_WP 0x04 Reset value SYSCFG_EXTICR1 EXTI3[3:0] EXTI2[3:0]...
Page 262 System configuration controller (SYSCFG) RM0316 Table 74. SYSCFG register map and reset values (continued) Offset Register SYSCFG_CFGR4 0x48 Reset value Refer to Section 3.2.2: Memory map and register boundary addresses for the register boundary addresses. 262/1141 DocID022558 Rev 8...
Page 263: Direct Memory Access Controller (Dma)
RM0316 Direct memory access controller (DMA) Direct memory access controller (DMA) 13.1 Introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions.
Page 264: Dma Functional Description
Direct memory access controller (DMA) RM0316 13.4 DMA functional description The block diagram is shown in the following figure. Figure 46. DMA block diagram 1. DMA2 is not available in STM32F303x6/8 and STM32F328x8 devices. The DMA controller performs direct memory transfer by sharing the system bus with the ®...
Page 265: Arbiter
RM0316 Direct memory access controller (DMA) release the Acknowledge. If there are more requests, the peripheral can initiate the next transaction. In summary, each DMA transfer consists of three operations: • The loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register.
Page 266 Direct memory access controller (DMA) RM0316 transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in non-circular mode, no DMA request is served after the last transfer (that is once the number of data items to be transferred has reached zero). In order to reload a new number of data items to be transferred into the DMA_CNDTRx register, the DMA channel must be disabled.
Page 267: Programmable Data Width, Data Alignment And Endians
RM0316 Direct memory access controller (DMA) register. The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory mode may not be used at the same time as Circular mode. 13.4.4 Programmable data width, data alignment and endians When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in Table 76: Programmable data width &...
Page 268: Error Management
Direct memory access controller (DMA) RM0316 Addressing an AHB peripheral that does not support byte or halfword write operations When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does not support byte or halfword write operations (when HSIZE is not used by the peripheral) and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below:...
Page 269 RM0316 Direct memory access controller (DMA) (x=1..3)) are simply logically ORed before entering the DMA1. This means that on one channel, only one request must be enabled at a time. Refer to Figure 47: STM32F302xB/C/D/E and STM32F302x6/8 DMA1 request mapping Figure 48: STM32F303x6/8 and STM32F328x8 DMA1 request mapping.
Page 270: Figure 47. Stm32F302Xb/C/D/E And Stm32F302X6/8 Dma1 Request Mapping
Direct memory access controller (DMA) RM0316 Figure 47. STM32F302xB/C/D/E and STM32F302x6/8 DMA1 request mapping 1. DMA requests are mapped on this DMA channel only if the corresponding remapping bit is set in the SYSCFG_CFGR1 register. For more details, please refer to Section 12.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1) on page 245.
Page 271: Figure 48. Stm32F303X6/8 And Stm32F328X8 Dma1 Request Mapping
RM0316 Direct memory access controller (DMA) Figure 48. STM32F303x6/8 and STM32F328x8 DMA1 request mapping 1. TIM6_UP, DAC1_CH1, TIM7_UP, DAC1_CH2, TIM16_CH1, TIM16_UP, TIM17_CH1, TIM17_UP, DAC2_CH1, I2C1, SPI1 and DMA request are mapped on this DMA channel only if the corresponding remapping bit is set in the SYSCFG_CFGR1 or SYSCFG_CFGR3 register. For more details, please refer Section 12.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1) on page 245 Section 12.1.8: DocID022558 Rev 8...
Page 272: Table 78. Stm32F303Xb/C/D/E, Stm32F358Xc And Stm32F398Xe Summary Of Dma1 Requests
Direct memory access controller (DMA) RM0316 SYSCFG configuration register 3 (SYSCFG_CFGR3) on page 257. 2. SPI1_TX_DMA_RMP[1:0] bits in SYSCFG configuration register 2 (SYSCFG_CFGR2) allow remapping of SPI1_TX on channel 5 and 7. Table 78. STM32F303xB/C/D/E, STM32F358xC and STM32F398xE summary of DMA1 requests for each channel Peripherals Channel 1...
Page 273 RM0316 Direct memory access controller (DMA) Table 79. STM32F303x6/8 and STM32F328x8 summary of DMA1 requests for each channel (continued) Peripheral Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel6 Channel7 TIM1_CH4 TIM1 TIM1_CH1 TIM1_CH2 TIM1_TRIG TIM1_UP TIM1_CH3 TIM1_COM TIM2_CH2 TIM2 TIM2_CH3...
Page 274: Figure 49. Stm32F303Xb/C/D/E, Stm32F358Xc And Stm32F398Xe Dma2 Request Mapping
Direct memory access controller (DMA) RM0316 Figure 49. STM32F303xB/C/D/E, STM32F358xC and STM32F398xE DMA2 request mapping 1. DMA request mapped on this DMA channel only if the corresponding remapping bit is set in the SYSCFG_CFGR1 register. For more details, please refer to Section 12.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1) on page 245.
Page 275: Table 80. Stm32F303Xb/C/D/E, Stm32F358Xc And Stm32F398Xe Summary Of Dma2 Requests
RM0316 Direct memory access controller (DMA) Table 80 lists the DMA requests for each channel. Table 80. STM32F303xB/C/D/E, STM32F358xC and STM32F398xE summary of DMA2 requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 ADC2 ADC4 ADC2 ADC4...
Page 276: Dma Registers
Direct memory access controller (DMA) RM0316 13.5 DMA registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32- bit). 13.5.1 DMA interrupt status register (DMA_ISR) Address offset: 0x00...
Page 277: Dma Interrupt Flag Clear Register (Dma
RM0316 Direct memory access controller (DMA) 13.5.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. CTEIF7 CHTIF7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5 CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1 Bits 31:28 Reserved, must be kept at reset value.
Page 278: Dma Channel X Configuration Register (Dma_Ccrx)
Direct memory access controller (DMA) RM0316 13.5.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7 , where x = channel number) Address offset: 0x08 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 Res. Res. Res. Res. Res.
Page 279 RM0316 Direct memory access controller (DMA) Bit 5 CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable...
Page 280: Dma Channel X Number Of Data Register (Dma_Cndtrx) (X = 1
Direct memory access controller (DMA) RM0316 13.5.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number) Address offset: 0x0C + 0d20 × (channel number – 1) Reset value: 0x0000 0000 Res. Res. Res. Res.
Page 281: Dma Channel X Memory Address Register (Dma_Cmarx) (X = 1
RM0316 Direct memory access controller (DMA) 13.5.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number) Address offset: 0x14 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. MA [31:16] MA [15:0] Bits 31:0 MA[31:0]: Memory address...
Page 282: Dma Register Map
Direct memory access controller (DMA) RM0316 13.5.7 DMA register map The following table gives the DMA register map and the reset values. Table 81. DMA register map and reset values Offset Register DMA_ISR 0x00 Reset value DMA_IFCR 0x04 Reset value DMA_CCR1 [1:0] 0x08...
Page 283 RM0316 Direct memory access controller (DMA) Table 81. DMA register map and reset values (continued) Offset Register 0x40 Reserved DMA_CCR4 [1:0] 0x44 Reset value DMA_CNDTR4 NDT[15:0] 0x48 Reset value DMA_CPAR4 PA[31:0] 0x4C Reset value DMA_CMAR4 MA[31:0] 0x50 Reset value 0x54 Reserved DMA_CCR5 [1:0]...
Page 284 Direct memory access controller (DMA) RM0316 Table 81. DMA register map and reset values (continued) Offset Register DMA_CPAR7 PA[31:0] 0x88 Reset value DMA_CMAR7 MA[31:0] 0x8C Reset value 0x90 - Reserved 0xA7 Refer to Section 3.2.2 on page 51 for the register boundary addresses. 284/1141 DocID022558 Rev 8...
Page 285: Interrupts And Events
RM0316 Interrupts and events Interrupts and events 14.1 Nested vectored interrupt controller (NVIC) 14.1.1 NVIC main features ® • 74 maskable interrupt channels (not including the sixteen Cortex -M4 with FPU interrupt lines) • 16 programmable priority levels (4 bits of interrupt priority are used) •...
Page 286 Interrupts and events RM0316 Table 82. STM32F303xB/C/D/E, STM32F358xC and STM32F398xE vector table (continued) Type of Acronym Description Address priority settable SVCall System service call via SWI instruction 0x0000 002C settable PendSV Pendable request for system service 0x0000 0038 settable SysTick System tick timer 0x0000 003C settable...
Page 287 RM0316 Interrupts and events Table 82. STM32F303xB/C/D/E, STM32F358xC and STM32F398xE vector table (continued) Type of Acronym Description Address priority settable TIM2 TIM2 global interrupt 0x0000 00B0 settable TIM3 TIM3 global interrupt 0x0000 00B4 settable TIM4 TIM4 global interrupt 0x0000 00B8 settable I2C1_EV I2C1 event interrupt &...
Page 288 Interrupts and events RM0316 Table 82. STM32F303xB/C/D/E, STM32F358xC and STM32F398xE vector table (continued) Type of Acronym Description Address priority settable ADC4 ADC4 global interrupt 0x0000 0134 Reserved 0x0000 0138 Reserved 0x0000 013C COMP1 & COMP2 & COMP3 interrupts settable COMP1_2_3 combined with EXTI Lines 21, 22 and 29 0x0000 0140 interrupts.
Page 289: Table 83. Stm32F303X6/8 And Stm32F328X8 Vector Table
RM0316 Interrupts and events Table 83. STM32F303x6/8 and STM32F328x8 vector table Type of Acronym Description Address priority Reserved 0x0000 0000 fixed Reset Reset 0x0000 0004 Non maskable interrupt. The RCC Clock fixed Security System (CSS) is linked to the NMI 0x0000 0008 vector.
Page 290 Interrupts and events RM0316 Table 83. STM32F303x6/8 and STM32F328x8 vector table (continued) Type of Acronym Description Address priority settable DMA1_Channel7 DMA1 channel 7 interrupt 0x0000 0084 settable ADC1_2 ADC1 and ADC2 global interrupt 0x0000 0088 settable CAN_TX CAN_TX interrupts 0x0000 008C settable CAN_RX0 CAN_RX0 interrupts...
Page 291 RM0316 Interrupts and events Table 83. STM32F303x6/8 and STM32F328x8 vector table (continued) Type of Acronym Description Address priority Reserved 0x0000 0104 Reserved 0x0000 0108 Reserved 0x0000 010C Reserved 0x0000 0110 Reserved 0x0000 0114 settable TIM6_DAC1 TIM6 global and DAC1 underrun interrupts 0x0000 0118 settable TIM7_DAC2...
Page 292: Extended Interrupts And Events Controller (Exti)
Interrupts and events RM0316 Table 83. STM32F303x6/8 and STM32F328x8 vector table (continued) Type of Acronym Description Address priority Reserved 0x0000 0180 settable Floating point interrupt 0x0000 0184 14.2 Extended interrupts and events controller (EXTI) The extended interrupts and events controller (EXTI) manages the external and internal asynchronous events/interrupts and generates the event request to the CPU/Interrupt Controller and a wake-up request to the Power Manager.
Page 293: Block Diagram
RM0316 Interrupts and events 14.2.2 Block diagram The extended interrupt/event block diagram is shown in the following figure. Figure 50. External interrupt/event block diagram 14.2.3 Wakeup event management STM32F3xx devices are able to handle external or internal events in order to wake up the core (WFE).
Page 294: Functional Description
Interrupts and events RM0316 To accomplish this, the peripheral is asked to generate both a synchronized (to the system clock, e.g. APB clock) and an asynchronous version of the event. 14.2.5 Functional description For the external interrupt lines, to generate the interrupt, the interrupt line should be configured and enabled.
Page 295: External And Internal Interrupt/Event Line Mapping
RM0316 Interrupts and events 14.2.6 External and internal interrupt/event line mapping 36 interrupt/event lines are available: 8 lines are internal (including the reserved ones); the remaining 28 lines are external. The GPIOs are connected to the 16 external interrupt/event lines in the following manner: Figure 51.
Page 296 Interrupts and events RM0316 The remaining lines are connected as follows: • EXTI line 16 is connected to the PVD output • EXTI line 17 is connected to the RTC Alarm event • EXTI line 18 is connected to USB Device FS wakeup event (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices) •...
Page 297: Exti Registers
RM0316 Interrupts and events 14.3 registers EXTI Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 14.3.1 Interrupt mask register (EXTI_IMR1) Address offset: 0x00 Reset value: 0x1F80 0000 (See note below) MR31 MR30...
Page 298: Rising Trigger Selection Register (Exti_Rtsr1)
Interrupts and events RM0316 14.3.3 Rising trigger selection register (EXTI_RTSR1) Address offset: 0x08 Reset value: 0x0000 0000 TR31 TR30 TR29 Res. Res. Res. Res. Res. Res. TR22 TR21 TR20 TR19 TR18 TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:29 TRx: Rising trigger event configuration bit of line x (x = 31 to 29) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line.
Page 299: Software Interrupt Event Register (Exti_Swier1)
RM0316 Interrupts and events Note: The external wakeup lines are edge-triggered. No glitches must be generated on these lines. If a falling edge on an external interrupt line occurs during a write operation to the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line.
Page 300: Interrupt Mask Register (Exti_Imr2)
Interrupts and events RM0316 Bits 31:29 PRx: Pending bit on line x (x = 31 to 29) 0: No trigger request occurred 1: Selected trigger request occurred This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a ‘1’...
Page 301: Rising Trigger Selection Register (Exti_Rtsr2)
RM0316 Interrupts and events 14.3.9 Rising trigger selection register (EXTI_RTSR2) Address offset: 0x28 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 302: Pending Register (Exti_Pr2)
Interrupts and events RM0316 Address offset: 0x30 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWIER SWIER Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 303: Exti Register Map
RM0316 Interrupts and events 14.3.13 EXTI register map The following table gives the EXTI register map and the reset values. Table 84. External interrupt/event controller register map and reset values Offset Register EXTI_IMR1 MR[31:0] 0x00 Reset value EXTI_EMR1 MR[31:0] 0x04 Reset value EXTI_RTSR1 TR[22:0]...
Page 304 Interrupts and events RM0316 Table 84. External interrupt/event controller register map and reset values (continued) Offset Register EXTI_SWIER2 0x30 Reset value EXTI_PR2 0x34 Reset value Refer to Section 3.2.2: Memory map and register boundary addresses for the register boundary addresses. 304/1141 DocID022558 Rev 8...
Page 305: Analog-To-Digital Converters (Adc)
RM0316 Analog-to-digital converters (ADC) Analog-to-digital converters (ADC) 15.1 Introduction This section describes the implementation of up to 4 ADCs: • ADC1 and ADC2 are tightly coupled and can operate in dual mode (ADC1 is master). • ADC3 and ADC4 are tightly coupled and can operate in dual mode (ADC3 is master). Each ADC consists of a 12-bit successive approximation analog-to-digital converter.
Page 306: Adc Main Features
Analog-to-digital converters (ADC) RM0316 15.2 ADC main features • High-performance features – Up to 4x ADC, each can operate in dual mode. The table below summarizes the different external channels available per ADC. Table 85. ADC external channels mapping Device ADC1 ADC2 ADC3...
Page 307: Table 86. Adc Internal Channels Summary
RM0316 Analog-to-digital converters (ADC) • In addition, there are internal dedicated channels available per ADC. See the table below.: Table 86. ADC internal channels summary Total of internal Product ADC1 ADC2 ADC3 ADC4 channels – 1 channel connected to – 1 channel temperature connected –...
Page 308 Analog-to-digital converters (ADC) RM0316 • Start-of-conversion can be initiated: – by software for both regular and injected conversions – by hardware triggers with configurable polarity (internal timers events or GPIO input events) for both regular and injected conversions • Conversion modes –...
Page 309: Adc Functional Description
RM0316 Analog-to-digital converters (ADC) 15.3 ADC functional description 15.3.1 ADC block diagram Figure 52 shows the ADC block diagram and Table 88 gives the ADC pin description. Figure 52. ADC block diagram DocID022558 Rev 8 309/1141...
Page 310: Pins And Internal Signals
Analog-to-digital converters (ADC) RM0316 15.3.2 Pins and internal signals Table 87. ADC internal signals Signal Internal signal name Description type Up to 16 external trigger inputs for the regular conversions (can be connected to on-chip timers). EXT[15:0] Inputs These inputs are shared between the ADC master and the ADC slave.
Page 311: Clocks
RM0316 Analog-to-digital converters (ADC) 15.3.3 Clocks Dual clock domain architecture The dual clock-domain architecture means that each ADC clock is independent from the AHB bus clock. The input clock of the two ADCs (master and slave) can be selected between two different clock sources (see Figure 53: ADC clock scheme):...
Page 312 Analog-to-digital converters (ADC) RM0316 Figure 53. ADC clock scheme Refer to the RCC section to see how HCLK, ADC12_CK, and ADC34_CK can be generated. Clock ratio constraint between ADC clock and AHB clock There are generally no constraints to be respected for the ratio between the ADC clock and the AHB clock except if some injected channels are programmed.
Page 313: Adc1/2 And Adc3/4 Connectivity
RM0316 Analog-to-digital converters (ADC) 15.3.4 ADC1/2 and ADC3/4 connectivity ADC1 and ADC2 (respectively ADC3 and ADC4) are tightly coupled and share some external channels as described in Figure 54 Figure Figure 54. ADC1 and ADC2 connectivity DocID022558 Rev 8 313/1141...
Page 314 Analog-to-digital converters (ADC) RM0316 1. STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices only. 2. STM32F303x6/8 and STM32F328x8 devices only. 314/1141 DocID022558 Rev 8...
Page 315: Figure 55. Adc3 & Adc4 Connectivity
RM0316 Analog-to-digital converters (ADC) Figure 55. ADC3 & ADC4 connectivity DocID022558 Rev 8 315/1141...
Page 316: Slave Ahb Interface
Analog-to-digital converters (ADC) RM0316 15.3.5 Slave AHB interface The ADCs implement an AHB slave port for control/status register and data access. The features of the AHB interface are listed below: • Word (32-bit) accesses • Single cycle response • Response to all read/write accesses to the registers with zero wait states. The AHB slave interface does not support split/retry requests, and never generates AHB errors.
Page 317: Calibration (Adcal, Adcaldif, Adcx_Calfact)
RM0316 Analog-to-digital converters (ADC) For a complete description of how the input channels are connected for each ADC, refer to Figure 54: ADC1 and ADC2 connectivity on page 313 Figure 55: ADC3 & ADC4 connectivity on page 315. Caution: When configuring the channel “i” in differential input mode, its negative input voltage is connected to ADC_INi+1.
Page 318: Figure 56. Adc Calibration
Analog-to-digital converters (ADC) RM0316 ADCx_CALFACT register without recalibrating, supposing that the software has previously saved the calibration factor delivered during the previous calibration. The calibration factor can be written if the ADC is enabled but not converting (ADEN=1 and ADSTART=0 and JADSTART=0). Then, at the next start of conversion, the calibration factor will automatically be injected into the analog ADC.
Page 319: Figure 57. Updating The Adc Calibration Factor
RM0316 Analog-to-digital converters (ADC) Figure 57. Updating the ADC calibration factor Converting single-ended and differential analog inputs with a single ADC If the ADC is supposed to convert both differential and single-ended inputs, two calibrations must be performed, one with ADCALDIF=0 and one with ADCALDIF=1. The procedure is the following: Disable the ADC.
Page 320: Adc On-Off Control (Aden, Addis, Adrdy)
Analog-to-digital converters (ADC) RM0316 15.3.9 ADC on-off control (ADEN, ADDIS, ADRDY) First of all, follow the procedure explained in Section 15.3.6: ADC voltage regulator (ADVREGEN)). Once ADVREGEN[1:0] = 01, the ADC can be enabled and the ADC needs a stabilization time of t before it starts converting accurately, as shown in Figure...
Page 321: Constraints When Writing The Adc Control Bits
RM0316 Analog-to-digital converters (ADC) 15.3.10 Constraints when writing the ADC control bits The software is allowed to write the RCC control bits to configure and enable the ADC clock (refer to RCC Section), the control bits DIFSEL in the ADCx_DIFSEL register and the control bits ADCAL and ADEN in the ADCx_CR register, only if the ADC is disabled (ADEN must be equal to 0).
Page 322: Channel-Wise Programmable Sampling Time (Smpr1, Smpr2)
Analog-to-digital converters (ADC) RM0316 Warning: The user must ensure that only one of the four ADCs is converting V at the same time (it is forbidden to have REFINT several ADCs converting V at the same time). REFINT Note: To convert one of the internal analog channels, the corresponding analog sources must first be enabled by programming bits VREFEN, TSEN or VBATEN in the ADCx_CCR registers.
Page 323: Single Conversion Mode (Cont=0)
RM0316 Analog-to-digital converters (ADC) Example: With F = 72 MHz and a sampling time of 1.5 ADC clock cycles: ADC_CLK Tconv = (1.5 + 12.5) ADC clock cycles = 14 ADC clock cycles = 0.194 μs (for fast channels) The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for regular conversion).
Page 324: Starting Conversions (Adstart, Jadstart)
Analog-to-digital converters (ADC) RM0316 Inside the regular sequence, after each conversion is complete: • The converted data are stored into the 16-bit ADCx_DR register • The EOC (end of conversion) flag is set • An interrupt is generated if the EOCIE bit is set After the sequence of conversions is complete: •...
Page 325: Timing
RM0316 Analog-to-digital converters (ADC) JADSTART is cleared by hardware: • in single mode with software injected trigger (JEXTSEL=0x0) – at any end of injected conversion sequence (JEOS assertion) or at any end of sub-group processing if JDISCEN = 1 • in all cases (JEXTSEL=x) –...
Page 326: Figure 61. Stopping Ongoing Regular Conversions
Analog-to-digital converters (ADC) RM0316 When the JADSTP bit is set by software, any ongoing injected conversion is aborted with partial result discarded (ADCx_JDRy register is not updated with the current conversion). The scan sequence is also aborted and reset (meaning that relaunching the ADC would re- start a new sequence).
Page 327: Conversion On External Trigger And Trigger Polarity
RM0316 Analog-to-digital converters (ADC) Figure 62. Stopping ongoing regular and injected conversions 15.3.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) A conversion or a sequence of conversions can be triggered either by software or by an external event (e.g.
Page 328: Table 90. Adc1 (Master) & 2 (Slave) - External Triggers For Regular Channels
Analog-to-digital converters (ADC) RM0316 Note: The polarity of the regular trigger cannot be changed on-the-fly. Note: The polarity of the injected trigger can be anticipated and changed on-the-fly. Refer to Section 15.3.21: Queue of context for injected conversions. The EXTSEL[3:0] and JEXTSEL[3:0] control bits select which out of 16 possible events can trigger conversion for the regular and injected groups.
Page 329: Table 91. Adc1 & Adc2 - External Trigger For Injected Channels
RM0316 Analog-to-digital converters (ADC) Table 90. ADC1 (master) & 2 (slave) - External triggers for regular channels (continued) Name Source Type EXTSEL[3:0] TIM2_CC2 event or EXT3 Internal signal from on chip timers 0011 TIM20_TRGO2 EXT4 TIM3_TRGO event Internal signal from on chip timers 0100 EXT5 TIM4_CC4 event or TIM20_CC1...
Page 330: Table 92. Adc3 & Adc4 - External Trigger For Regular Channels
Analog-to-digital converters (ADC) RM0316 1. Only for STM32F303xD/E and STM32F398xE devices. Table 92. ADC3 & ADC4 - External trigger for regular channels Name Source Type EXTSEL[3..0] EXT0 TIM3_CC1 event Internal signal from on chip timers 0000 EXT1 TIM2_CC3 event Internal signal from on chip timers 0001 EXT2 TIM1_CC3 event...
Page 331: Injected Channel Management
RM0316 Analog-to-digital converters (ADC) Table 93. ADC3 & ADC4 - External trigger for injected channels (continued) Name Source Type JEXTSEL[3..0] TIM1_CC3 event or JEXT11 Internal signal from on chip timers 1011 TIM20_TRGO2 JEXT12 TIM3_TRGO event Internal signal from on chip timers 1100 JEXT13 TIM2_TRGO event...
Page 332: Discontinuous Mode (Discen, Discnum, Jdiscen)
Analog-to-digital converters (ADC) RM0316 If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected channels are continuously converted. Note: It is not possible to use both the auto-injected and discontinuous modes simultaneously. When the DMA is used for exporting regular sequencer’s data in JAUTO mode, it is necessary to program it in circular mode (CIRC bit set in DMA_CCRx register).
Page 333 RM0316 Analog-to-digital converters (ADC) Example: • DISCEN=1, n=3, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10, 11 – 1st trigger: channels converted are 1, 2, 3 (an EOC event is generated at each conversion). – 2nd trigger: channels converted are 6, 7, 8 (an EOC event is generated at each conversion).
Page 334: Queue Of Context For Injected Conversions
Analog-to-digital converters (ADC) RM0316 15.3.21 Queue of context for injected conversions A queue of context is implemented to anticipate up to 2 contexts for the next injected sequence of conversions. This context consists of: • Configuration of the injected triggers (bits JEXTEN[1:0] and JEXTSEL[3:0] in ADCx_JSQR register) •...
Page 335: Figure 65. Example Of Jsqr Queue Of Context (Sequence Change)
RM0316 Analog-to-digital converters (ADC) consumes the queue but others are still valid triggers as shown by the discontinuous mode example below (length = 3 for both contexts): • trigger, discontinuous. Sequence 1: context 1 consumed, 1 conversion carried out • trigger, disc.
Page 336: Figure 67. Example Of Jsqr Queue Of Context With Overflow Before Conversion
Analog-to-digital converters (ADC) RM0316 Queue of context: Behavior when a queue overflow occurs Figure 67 Figure 68 show the behavior of the context Queue if an overflow occurs before or during a conversion. Figure 67. Example of JSQR queue of context with overflow before conversion 1.
Page 337: Figure 69. Example Of Jsqr Queue Of Context With Empty Queue (Case Jqm=0)
RM0316 Analog-to-digital converters (ADC) It is recommended to manage the queue overflows as described below: • After each P context write into JSQR register, flag JQOVF shows if the write has been ignored or not (an interrupt can be generated). •...
Page 338: Figure 71. Flushing Jsqr Queue Of Context By Setting Jadstp=1 (Jqm=0). Case When Jadstp Occurs During An Ongoing Conversion
Analog-to-digital converters (ADC) RM0316 Flushing the queue of context The figures below show the behavior of the context Queue in various situations when the queue is flushed. Figure 71. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion. 1.
Page 339: Figure 73. Flushing Jsqr Queue Of Context By Setting Jadstp=1 (Jqm=0). Case When Jadstp Occurs Outside An Ongoing Conversion
RM0316 Analog-to-digital converters (ADC) Figure 73. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs outside an ongoing conversion 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Figure 74.
Page 340: Figure 75. Flushing Jsqr Queue Of Context By Setting Addis=1 (Jqm=0)
Analog-to-digital converters (ADC) RM0316 Figure 75. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0) 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Figure 76.
Page 341: Programmable Resolution (Res) - Fast Conversion Mode
RM0316 Analog-to-digital converters (ADC) Figure 77. Example of JSQR queue of context when changing SW and HW triggers 1. Parameters: P1: sequence of 1 conversion, hardware trigger (JEXTEN /=0x0) P2: sequence of 1 conversion, hardware trigger (JEXTEN /= 0x0) P3: sequence of 1 conversion, software trigger (JEXTEN = 0x0) P4: sequence of 1 conversion, hardware trigger (JEXTEN /= 0x0) 15.3.22 Programmable resolution (RES) - fast conversion mode...
Page 342: End Of Conversion Sequence (Eos, Jeos)
Analog-to-digital converters (ADC) RM0316 The ADC sets the EOC flag as soon as a new regular conversion data is available in the ADCx_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared by the software either by writing 1 to it or by reading ADCx_DR. The ADC sets the JEOC flag as soon as a new injected conversion data is available in one of the ADCx_JDRy register.
Page 343: Figure 79. Continuous Conversion Of A Sequence, Software Trigger
RM0316 Analog-to-digital converters (ADC) Figure 79. Continuous conversion of a sequence, software trigger 1. EXTEN=0x0, CONT=1 2. Channels selected = 1,9, 10, 17; AUTDLY=0. Figure 80. Single conversions of a sequence, hardware trigger 1. TRGx (over-frequency) is selected as trigger source, EXTEN = 01, CONT = 0 2.
Page 344: Data Management
Analog-to-digital converters (ADC) RM0316 15.3.26 Data management Data register, data alignment and offset (ADCx_DR, OFFSETy, OFFSETy_CH, ALIGN) Data and alignment At the end of each regular conversion channel (when EOC event occurs), the result of the converted data is stored into the ADCx_DR data register which is 16 bits wide. At the end of each injected conversion channel (when JEOC event occurs), the result of the converted data is stored into the corresponding ADCx_JDRy data register which is 16 bits wide.
Page 345: Figure 82. Right Alignment (Offset Disabled, Unsigned Value)
RM0316 Analog-to-digital converters (ADC) When reading data from ADCx_DR (regular channel) or from ADCx_JDRy (injected channel, y=1,2,3,4) corresponding to the channel “i”: • If one of the offsets is enabled (bit OFFSETy_EN=1) for the corresponding channel, the read data is signed. •...
Page 346: Figure 83. Right Alignment (Offset Enabled, Signed Value)
Analog-to-digital converters (ADC) RM0316 Figure 83. Right alignment (offset enabled, signed value) Figure 84. Left alignment (offset disabled, unsigned value) 346/1141 DocID022558 Rev 8...
Page 347: Figure 85. Left Alignment (Offset Enabled, Signed Value)
RM0316 Analog-to-digital converters (ADC) Figure 85. Left alignment (offset enabled, signed value) ADC overrun (OVR, OVRMOD) The overrun flag (OVR) notifies of a buffer overrun event, when the regular converted data was not read (by the CPU or the DMA) before new converted data became available. The OVR flag is set if the EOC flag is still 1 at the time when a new conversion completes.
Page 348: Figure 86. Example Of Overrun (Ovr)
Analog-to-digital converters (ADC) RM0316 Figure 86. Example of overrun (OVR) Note: There is no overrun detection on the injected channels since there is a dedicated data register for each of the four injected channels. Managing a sequence of conversion without using the DMA If the conversions are slow enough, the conversion sequence can be handled by the software.
Page 349: Dynamic Low-Power Features
RM0316 Analog-to-digital converters (ADC) corresponding to the new conversion is not transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid. Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten (refer to Section : ADC overrun (OVR, OVRMOD)).
Page 350 Analog-to-digital converters (ADC) RM0316 This is a way to automatically adapt the speed of the ADC to the speed of the system which will read the data. The delay is inserted after each regular conversion (whatever DISCEN=0 or 1) and after each sequence of injected conversions (whatever JDISCEN=0 or 1).
Page 351: Figure 87. Autodly=1, Regular Conversion In Continuous Mode, Software Trigger
RM0316 Analog-to-digital converters (ADC) Figure 87. AUTODLY=1, regular conversion in continuous mode, software trigger 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, CHANNELS = 1,2,3 3. Injected configuration DISABLED Figure 88. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0;...
Page 352 Analog-to-digital converters (ADC) RM0316 Figure 89. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=1, JDISCEN=1) 1. AUTDLY=1 2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=1, DISCNUM=1, CHANNELS = 1, 2, 3. 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=1, CHANNELS = 5,6 352/1141 DocID022558 Rev 8...
Page 353: Figure 90. Autodly=1, Regular Continuous Conversions Interrupted By Injected Conversions
RM0316 Analog-to-digital converters (ADC) Figure 90. AUTODLY=1, regular continuous conversions interrupted by injected conversions 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2, 3 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6 Figure 91. AUTODLY=1 in auto- injected mode (JAUTO=1) 1.
Page 354: Analog Window Watchdog
Analog-to-digital converters (ADC) RM0316 15.3.28 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) The three AWD analog watchdogs monitor whether some channels remain within a configured voltage range (window). Figure 92. Analog watchdog’s guarded area AWDx flag and interrupt An interrupt can be enabled for each of the 3 analog watchdogs by setting AWDxIE in the ADCx_IER register (x=1,2,3).
Page 355: Table 97. Analog Watchdog 1 Comparison
RM0316 Analog-to-digital converters (ADC) These thresholds are programmed in bits HT1[11:0] and LT1[11:0] of the ADCx_TR1 register for the analog watchdog 1. When converting data with a resolution of less than 12 bits (according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned).
Page 356: Figure 93. Adcy_Awdx_Out Signal Generation (On All Regular Channels)
Analog-to-digital converters (ADC) RM0316 1. The watchdog comparison is performed on the raw converted data before any alignment calculation and before applying any offsets (the data which is compared is not signed). ADCy_AWDx_OUT signal output generation Each analog watchdog is associated to an internal hardware signal ADCy_AWDx_OUT (y=ADC number, x=watchdog number) which is directly connected to the ETR input (external trigger) of some on-chip timers.
Page 357: Figure 94. Adcy_Awdx_Out Signal Generation (Awdx Flag Not Cleared By Sw)
RM0316 Analog-to-digital converters (ADC) Figure 94. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by SW) Figure 95. ADCy_AWDx_OUT signal generation (on a single regular channel) Figure 96. ADCy_AWDx_OUT signal generation (on all injected channels) DocID022558 Rev 8 357/1141...
Page 358: Dual Adc Modes
Analog-to-digital converters (ADC) RM0316 15.3.29 Dual ADC modes In devices with two ADCs or more, dual ADC modes can be used (see Figure 97): • ADC1 and ADC2 can be used together in dual mode (ADC1 is master) • ADC3 and ADC4 can be used together in dual mode (ADC3 is master) In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADCx master to the ADC slave, depending on the mode selected by the bits DUAL[4:0] in the ADCx_CCR register.
Page 359: Analog-To-Digital Converters (Adc)
RM0316 Analog-to-digital converters (ADC) Figure 97. Dual ADC block diagram External triggers also exist on slave ADC but are not shown for the purposes of this diagram. The ADC common data register (ADCx_CDR) contains both the master and slave ADC regular converted data. DocID022558 Rev 8 359/1141...
Page 360: Figure 98. Injected Simultaneous Mode On 4 Channels: Dual Adc Mode
Analog-to-digital converters (ADC) RM0316 Injected simultaneous mode This mode is selected by programming bits DUAL[4:0]=00101 This mode converts an injected group of channels. The external trigger source comes from the injected group multiplexer of the master ADC (selected by the JEXTSEL[3:0] bits in the ADCx_JSQR register).
Page 361 RM0316 Analog-to-digital converters (ADC) ongoing regular sequence and the associated delay phases are ignored. There is the same behavior for regular sequences occurring on the slave ADC. Regular simultaneous mode with independent injected This mode is selected by programming bits DUAL[4:0] = 00110. This mode is performed on a regular group of channels.
Page 362: Figure 99. Regular Simultaneous Mode On 16 Channels: Dual Adc Mode
Analog-to-digital converters (ADC) RM0316 Note: In MDMA mode (MDMA[1:0]=0b10 or 0b11), the user must program the same number of conversions in the master’s sequence as in the slave’s sequence. Otherwise, the remaining conversions will not generate a DMA request. Figure 99. Regular simultaneous mode on 16 channels: dual ADC mode If DISCEN=1 then each “n”...
Page 363 RM0316 Analog-to-digital converters (ADC) The minimum delay which separates 2 conversions in interleaved mode is configured in the DELAY bits in the ADCx_CCR register. This delay starts to count after the end of the sampling phase of the master conversion. This way, an ADC cannot start a conversion if the complementary ADC is still sampling its input (only one ADC can sample the input signal at a given time).
Page 364: Figure 100. Interleaved Mode On 1 Channel In Continuous Conversion Mode: Dual Adc Mode
Analog-to-digital converters (ADC) RM0316 Figure 100. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode Figure 101. Interleaved mode on 1 channel in single conversion mode: dual ADC mode If DISCEN=1, each “n” simultaneous conversions (“n” is defined by DISCNUM) of the regular sequence require a regular trigger event to occur.
Page 365: Figure 102. Interleaved Conversion With Injection
RM0316 Analog-to-digital converters (ADC) Figure 102. Interleaved conversion with injection Alternate trigger mode This mode is selected by programming bits DUAL[4:0] = 01001. This mode can be started only on an injected group. The source of external trigger comes from the injected group multiplexer of the master ADC. This mode is only possible when selecting hardware triggers: JEXTEN must not be 0x0.
Page 366: Figure 103. Alternate Trigger: Injected Group Of Each Adc
Analog-to-digital converters (ADC) RM0316 Figure 103. Alternate trigger: injected group of each ADC Note: Regular conversions can be enabled on one or all ADCs. In this case the regular conversions are independent of each other. A regular conversion is interrupted when the ADC has to perform an injected conversion.
Page 367: Figure 104. Alternate Trigger: 4 Injected Channels (Each Adc) In Discontinuous Mode
RM0316 Analog-to-digital converters (ADC) Figure 104. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode Combined regular/injected simultaneous mode This mode is selected by programming bits DUAL[4:0] = 00001. It is possible to interrupt the simultaneous conversion of a regular group to start the simultaneous conversion of an injected group.
Page 368: Figure 105. Alternate + Regular Simultaneous
Analog-to-digital converters (ADC) RM0316 Figure 105. Alternate + regular simultaneous If a trigger occurs during an injected conversion that has interrupted a regular conversion, the alternate trigger is served. Figure 106 shows the behavior in this case (note that the 6th trigger is ignored because the associated alternate conversion is not complete).
Page 369: Figure 107. Dma Requests In Regular Simultaneous Mode When Mdma=0B00
RM0316 Analog-to-digital converters (ADC) DMA requests in dual ADC mode In all dual ADC modes, it is possible to use two DMA channels (one for the master, one for the slave) to transfer the data, like in single mode (refer to Figure 107: DMA Requests in regular simultaneous mode when MDMA=0b00).
Page 370: Figure 108. Dma Requests In Regular Simultaneous Mode When Mdma=0B10
Analog-to-digital converters (ADC) RM0316 Figure 108. DMA requests in regular simultaneous mode when MDMA=0b10 Figure 109. DMA requests in interleaved mode when MDMA=0b10 370/1141 DocID022558 Rev 8...
Page 371: Temperature Sensor
RM0316 Analog-to-digital converters (ADC) Note: When using MDMA mode, the user must take care to configure properly the duration of the master and slave conversions so that a DMA request is generated and served for reading both data (master + slave) before a new conversion is available. •...
Page 372: Figure 110. Temperature Sensor Channel Block Diagram
RM0316 temperature sensor measurement, calibration values are stored in system memory for each device by ST during production. During the manufacturing process, the calibration data of the temperature sensor and the internal voltage reference are stored in the system memory area. The user application can then read them and use them to improve the accuracy of the temperature sensor or the internal reference.
Page 373: Vbat Supply Monitoring
RM0316 Analog-to-digital converters (ADC) Select the ADC1_IN16 input channel (with the appropriate sampling time). Program with the appropriate sampling time (refer to electrical characteristics section of the STM32F3xx datasheet). Set the TSEN bit in the ADC1_CCR register to wake up the temperature sensor from power-down mode.
Page 374: Monitoring The Internal Voltage Reference
Analog-to-digital converters (ADC) RM0316 Figure 111. V channel block diagram Note: The VBATEN bit must be set to enable the conversion of internal channel ADC1_IN17 BATEN 15.3.32 Monitoring the internal voltage reference It is possible to monitor the internal voltage reference (V ) to have a reference point for REFINT evaluating the ADC V...
Page 375 RM0316 Analog-to-digital converters (ADC) Calculating the actual V voltage using the internal reference voltage The V power supply voltage applied to the microcontroller may be subject to variation or not precisely known. The embedded internal voltage reference (V ) and its calibration REFINT data acquired by the ADC during the manufacturing process at V = 3.3 V can be used to...
Page 376: Adc Interrupts
Analog-to-digital converters (ADC) RM0316 15.4 ADC interrupts For each ADC, an interrupt can be generated: • After ADC power-up, when the ADC is ready (flag ADRDY) • On the end of any conversion for regular groups (flag EOC) • On the end of a sequence of conversion for regular groups (flag EOS) •...
Page 377: Adc Registers (For Each Adc)
RM0316 Analog-to-digital converters (ADC) 15.5 ADC registers (for each ADC) Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. Note: The STM32F303x6/8 and STM32F328x8 devices have only ADC1 and ADC2. 15.5.1 ADC interrupt and status register (ADCx_ISR, x=1 Address offset: 0x00 Reset value: 0x0000 0000 Res.
Page 378 Analog-to-digital converters (ADC) RM0316 Bit 6 JEOS: Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it. 0: Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software) 1: Injected conversions complete...
Page 379: Adc Interrupt Enable Register (Adcx_Ier, X=1
RM0316 Analog-to-digital converters (ADC) 15.5.2 ADC interrupt enable register (ADCx_IER, x=1 Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD3 AWD2 AWD1 EOSMP ADRDY Res. Res.
Page 380 Analog-to-digital converters (ADC) RM0316 Bit 5 JEOCIE: End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. 0: JEOC interrupt disabled. 1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set. Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no regular conversion is ongoing).
Page 381: Adc Control Register (Adcx_Cr, X=1
RM0316 Analog-to-digital converters (ADC) 15.5.3 ADC control register (ADCx_CR, x=1 Address offset: 0x08 Reset value: 0x2000 0000 ADCA ADVREGEN[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LDIF Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 382 Analog-to-digital converters (ADC) RM0316 Bit 5 JADSTP: ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured.
Page 383 RM0316 Analog-to-digital converters (ADC) Bit 2 ADSTART: ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion will start immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration).
Page 384: Adc Configuration Register (Adcx_Cfgr, X=1
Analog-to-digital converters (ADC) RM0316 15.5.4 ADC configuration register (ADCx_CFGR, x=1 Address offset: 0x0C Reset value: 0x0000 00000 JAWD1 AWD1 AWD1S JDISC DISC Res. AWD1CH[4:0] JAUTO DISCNUM[2:0] Res. CONT EXTEN[1:0] EXTSEL[3:0] ALIGN RES[1:0] Res. Bit 31 Reserved, must be kept at reset value. Bits 30:26 AWD1CH[4:0]: Analog watchdog 1 channel selection These bits are set and cleared by software.
Page 385 RM0316 Analog-to-digital converters (ADC) Bit 22 AWD1SGL: Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels 0: Analog watchdog 1 enabled on all channels 1: Analog watchdog 1 enabled on a single channel Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which...
Page 386 Analog-to-digital converters (ADC) RM0316 Bit 16 DISCEN: Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. 0: Discontinuous mode for regular channels disabled 1: Discontinuous mode for regular channels enabled Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1.
Page 387 RM0316 Analog-to-digital converters (ADC) Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. 00: Hardware trigger detection disabled (conversions can be launched by software) 01: Hardware trigger detection on the rising edge 10: Hardware trigger detection on the falling edge 11: Hardware trigger detection on both the rising and falling edges...
Page 388: Adc Sample Time Register 1 (Adcx_Smpr1, X=1
Analog-to-digital converters (ADC) RM0316 Bit 2 Reserved, must be kept at reset value. Bit 1 DMACFG: Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN=1. 0: DMA One Shot Mode selected 1: DMA Circular Mode selected For more details, refer to...
Page 389 RM0316 Analog-to-digital converters (ADC) Bits 31:30 Reserved, must be kept at reset value. Bits 29:3 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. 000: 1.5 ADC clock cycles 001: 2.5 ADC clock cycles 010: 4.5 ADC clock cycles...
Page 390: Adc Sample Time Register 2 (Adcx_Smpr2, X=1
Analog-to-digital converters (ADC) RM0316 15.5.6 ADC sample time register 2 (ADCx_SMPR2, x=1 Address offset: 0x18 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. SMP18[2:0] SMP17[2:0] SMP16[2:0] SMP15[2:1] SMP15_0 SMP14[2:0] SMP13[2:0] SMP12[2:0] SMP11[2:0] SMP10[2:0] Bits 31:27 Reserved, must be kept at reset value. Bits 26:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel.
Page 391: Adc Watchdog Threshold Register 2 (Adcx_Tr2, X = 1
RM0316 Analog-to-digital converters (ADC) Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to Section 15.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
Page 392: Adc Watchdog Threshold Register 3 (Adcx_Tr3, X=1
Analog-to-digital converters (ADC) RM0316 15.5.9 ADC watchdog threshold register 3 (ADCx_TR3, x=1 Address offset: 0x28 Reset value: 0x00FF 0000 Res. Res. Res. Res. Res. Res. Res. Res. HT3[7:0] Res. Res. Res. Res. Res. Res. Res. Res. LT3[7:0] Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3.
Page 393: Adc Regular Sequence Register 1 (Adcx_Sqr1, X=1
RM0316 Analog-to-digital converters (ADC) 15.5.10 ADC regular sequence register 1 (ADCx_SQR1, x=1 Address offset: 0x30 Reset value: 0x0000 0000 Res. Res. Res. SQ4[4:0] Res. SQ3[4:0] Res. SQ2[4] SQ2[3:0] Res. SQ1[4:0] Res. Res. L[3:0] Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence These bits are written by software with the channel number (1..18) assigned as the 4th in the regular conversion sequence.
Page 394: Adc Regular Sequence Register 2 (Adcx_Sqr2, X=1
Analog-to-digital converters (ADC) RM0316 Bits 10:6 SQ1[4:0]: 1st conversion in regular sequence These bits are written by software with the channel number (1..18) assigned as the 1st in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 395 RM0316 Analog-to-digital converters (ADC) Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence These bits are written by software with the channel number (1..18) assigned as the 7th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 396: Adc Regular Sequence Register 3 (Adcx_Sqr3, X=1
Analog-to-digital converters (ADC) RM0316 15.5.12 ADC regular sequence register 3 (ADCx_SQR3, x=1 Address offset: 0x38 Reset value: 0x0000 0000 Res. Res. Res. SQ14[4:0] Res. SQ13[4:0] Res. SQ12[4] SQ12[3:0] Res. SQ11[4:0] Res. SQ10[4:0] Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence These bits are written by software with the channel number (1..18) assigned as the 14th in the regular conversion sequence.
Page 397: Adc Regular Sequence Register 4 (Adcx_Sqr4, X=1
RM0316 Analog-to-digital converters (ADC) 15.5.13 ADC regular sequence register 4 (ADCx_SQR4, x=1 Address offset: 0x3C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SQ16[4:0] Res.
Page 398: Adc Regular Data Register (Adcx_Dr, X=1
Analog-to-digital converters (ADC) RM0316 15.5.14 ADC regular Data Register (ADCx_DR, x=1 Address offset: 0x40 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RDATA[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 RDATA[15:0]: Regular Data converted These bits are read-only.
Page 399: Adc Injected Sequence Register (Adcx_Jsqr, X=1
RM0316 Analog-to-digital converters (ADC) 15.5.15 ADC injected sequence register (ADCx_JSQR, x=1 Address offset: 0x4C Reset value: 0x0000 0000 Res. JSQ4[4:0] Res. JSQ3[4:0] Res. JSQ2[4:2] JSQ2[1:0] Res. JSQ1[4:0] JEXTEN[1:0] JEXTSEL[3:0] JL[1:0] Bit 31 Reserved, must be kept at reset value. Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence These bits are written by software with the channel number (1..18) assigned as the 4th in the injected conversion sequence.
Page 400 Analog-to-digital converters (ADC) RM0316 Bits 7:6 JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. 00: Hardware trigger detection disabled (conversions can be launched by software) 01: Hardware trigger detection on the rising edge 10: Hardware trigger detection on the falling edge 11: Hardware trigger detection on both the rising and falling edges...
Page 401: Adc Offset Register (Adcx_Ofry, X=1
RM0316 Analog-to-digital converters (ADC) 15.5.16 ADC offset register (ADCx_OFRy, x=1 4) (y=1..4) Address offset: 0x60, 0x64, 0x68, 0x6C Reset value: 0x0000 0000 OFFSETy OFFSETy_CH[4:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OFFSETy[11:0] Bit 31 OFFSETy_EN: Offset y Enable This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0].
Page 402: Adc Injected Data Register (Adcx_Jdry, X=1
Analog-to-digital converters (ADC) RM0316 15.5.17 ADC injected data register (ADCx_JDRy, x=1 4, y= 1..4) Address offset: 0x80 - 0x8C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. JDATA[15:0] Bits 31:16 Reserved, must be kept at reset value.
Page 403: Adc Analog Watchdog 3 Configuration Register
RM0316 Analog-to-digital converters (ADC) 15.5.19 ADC Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, Address offset: 0xA4 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD3CH[18:16] AWD3CH[15:1] Res. Bits 31:19 Reserved, must be kept at reset value. Bits 18:1 AWD3CH[18:1]: Analog watchdog 3 channel selection These bits are set and cleared by software.
Page 404: Adc Calibration Factors (Adcx_Calfact, X=1
Analog-to-digital converters (ADC) RM0316 Bits 31:19 Reserved, must be kept at reset value. Bits 18:16 DIFSEL[18:16]: Differential mode for channels 18 to 16. These bits are read only. These channels are forced to single-ended input mode (either connected to a single-ended I/O port or to an internal channel).
Page 405: Adc Common Registers
RM0316 Analog-to-digital converters (ADC) 15.6 ADC common registers These registers define the control and status registers common to master and slave ADCs: • One set of registers is related to ADC1 (master) and ADC2 (slave) • One set of registers is related to ADC3 (master) and ADC4 (slave) available in STM32F303xB/C and STM32F358xC devices 15.6.1 ADC Common status register (ADCx_CSR, x=12 or 34)
Page 406 Analog-to-digital converters (ADC) RM0316 Bit 17 EOSMP_SLV: End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADCx_ISR register. Bit 16 ADRDY_SLV: Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx_ISR register. Bits 15:11 Reserved, must be kept at reset value.
Page 407: Adc Common Control Register (Adcx_Ccr, X=12 Or 34)
RM0316 Analog-to-digital converters (ADC) 15.6.2 ADC common control register (ADCx_CCR, x=12 or 34) Address offset: 0x08 (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 VBAT VREF Res. Res. Res. Res. Res. Res.
Page 408 Analog-to-digital converters (ADC) RM0316 Bits 17:16 CKMODE[1:0]: ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): 00: CK_ADCx (x=123) (Asynchronous clock mode), generated at product level (refer to Section 6: Reset and clock control (RCC)) 01: HCLK/1 (Synchronous clock mode).
Page 409: Analog-To-Digital Converters (Adc)
RM0316 Analog-to-digital converters (ADC) Bits 11:8 DELAY: Delay between 2 sampling phases Set and cleared by software. These bits are used in dual interleaved modes. Refer to Table 100 for the value of ADC resolution versus DELAY bits values. Note: Software is allowed to write these bits only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Page 410: Adc Common Regular Data Register For Dual Mode
Analog-to-digital converters (ADC) RM0316 15.6.3 ADC common regular data register for dual mode (ADCx_CDR, x=12 or 34) Address offset: 0x0C (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 RDATA_SLV[15:0] RDATA_MST[15:0] Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC.
Page 411: Table 102. Adc Register Map And Reset Values For Each Adc
RM0316 Analog-to-digital converters (ADC) Table 102. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC, x=1..4) Offset Register ADCx_ISR 0x00 Reset value ADCx_IER 0x04 Reset value ADCx_CR 0x08 Reset value DISCNUM EXTSEL ADCx_CFGR AWD1CH[4:0] 0x0C...
Page 412 Analog-to-digital converters (ADC) RM0316 Table 102. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC, x=1..4) (continued) Offset Register OFFSET1_ ADCx_OFR1 OFFSET1[11:0] CH[4:0] 0x60 Reset value OFFSET2_ ADCx_OFR2 OFFSET2[11:0] CH[4:0] 0x64 Reset value OFFSET3_ ADCx_OFR3 OFFSET3[11:0]...
Page 413 RM0316 Analog-to-digital converters (ADC) Table 103. ADC register map and reset values (master and slave ADC common registers) offset =0x300, x=1 or 34) Offset Register ADCx_CSR 0x00 slave ADC2 or ADC4 master ADC1 or ADC3 Reset value 0x04 Reserved Res. ADCx_CCR DELAY[3:0] DUAL[4:0]...
Page 414: Digital-To-Analog Converter (Dac1 And Dac2)
Digital-to-analog converter (DAC1 and DAC2) RM0316 Digital-to-analog converter (DAC1 and DAC2) 16.1 Introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.
Page 415: Figure 113. Dac1 Block Diagram
RM0316 Digital-to-analog converter (DAC1 and DAC2) Figure 113. DAC1 block diagram 1. TIM8_TRGO and TIM4_TRGO are only available on STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices. 2. On STM32F303x6/8 and STM32F328, there is no output buffer on the DAC1 channel 2. There is instead a switch allowing to connect the DAC1_OUT2 to the corresponding I/O (PA5) (refer to DAC2 block diagram).
Page 416: Dac Output Buffer Enable/Dac Output Switch
Digital-to-analog converter (DAC1 and DAC2) RM0316 Figure 114. DAC2 block diagram (only on STM32F303x6/8 and STM32F328) Table 104. DACx pins Name Signal type Remarks Input, analog reference The higher/positive reference voltage for the DAC REF+ positive Input, analog supply Analog power supply Input, analog supply ground Ground for analog power supply DAC1_OUT1/2...
Page 417: Dac Channel Enable
RM0316 Digital-to-analog converter (DAC1 and DAC2) In the STM32F303x6/8 and STM32F328, the DAC1 channel 1 comes with an output buffer. The DAC1 channel2 does not have an output buffer, it has instead a switch allowing to connect the DAC1_OUT2 to the corresponding I/O (PA5). The switch can be enabled and disabled through the OUTEN2 bit in the DAC_CR register.
Page 418: Dac Channel Conversion
Digital-to-analog converter (DAC1 and DAC2) RM0316 16.5.2 DAC channel conversion The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx). Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset).
Page 419: Dac Output Voltage
RM0316 Digital-to-analog converter (DAC1 and DAC2) When a DAC channelx trigger arrives, the DAC channelx triangle counter, with the same triangle amplitude, is added to the DHRx register and the sum is transferred into DAC_DORx (three APB clock cycles later). The DAC channelx triangle counter is then updated.
Page 420: Dual-Mode Functional Description
Digital-to-analog converter (DAC1 and DAC2) RM0316 Table 106. External triggers (DAC2) (continued) Source Type TSEL[2:0] EXTI line9 External pin SWTRIG Software control bit Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on the selected external interrupt line 9, the last data stored into the DAC_DHRx register are transferred into the DAC_DORx register.
Page 421: Dac Channel Conversion In Dual Mode
RM0316 Digital-to-analog converter (DAC1 and DAC2) 16.6.2 DAC channel conversion in dual mode The DAC channel conversion in dual mode is performed in the same way as in single mode (refer to Section 16.5.2) except that the data have to be loaded by writing to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12RD.
Page 422 Digital-to-analog converter (DAC1 and DAC2) RM0316 Independent trigger with different LFSR generation To configure the DAC in this conversion mode (refer to Section 16.7: Noise generation), the following sequence is required: Set the two DAC channel trigger enable bits TEN1 and TEN2 Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits Configure the two DAC channel WAVEx[1:0] bits as “01”...
Page 423 RM0316 Digital-to-analog converter (DAC1 and DAC2) Simultaneous software start To configure the DAC in this conversion mode, the following sequence is required: Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) In this configuration, one APB clock cycles). Simultaneous trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: Set the two DAC channel trigger enable bits TEN1 and TEN2...
Page 424: Dac Output Voltage
Digital-to-analog converter (DAC1 and DAC2) RM0316 At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB clock cycles later). The LFSR2 counter is then updated. Simultaneous trigger with single triangle generation To configure the DAC in this conversion mode (refer to Section 16.8: Triangle-wave...
Page 425: Dac Trigger Selection
RM0316 Digital-to-analog converter (DAC1 and DAC2) 16.6.5 DAC trigger selection Refer to Section 16.5.4: DAC trigger selection 16.7 Noise generation In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The preloaded value in LFSR is 0xAAA.
Page 426: Triangle-Wave Generation
Digital-to-analog converter (DAC1 and DAC2) RM0316 16.8 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB clock cycles after each trigger event.
Page 427: Dma Request
RM0316 Digital-to-analog converter (DAC1 and DAC2) 16.9 DMA request Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests. A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set.
Page 428: Dac Registers
Digital-to-analog converter (DAC1 and DAC2) RM0316 16.10 DAC registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 16.10.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 BOFF2...
Page 429 RM0316 Digital-to-analog converter (DAC1 and DAC2) Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) These bits are available only in dual mode when wave generation is supported.
Page 430 Digital-to-analog converter (DAC1 and DAC2) RM0316 Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. 0: DAC channel1 DMA Underrun Interrupt disabled 1: DAC channel1 DMA Underrun Interrupt enabled Bit 12 DMAEN1: DAC channel1 DMA enable This bit is set and cleared by software.
Page 431 RM0316 Digital-to-analog converter (DAC1 and DAC2) Bit 2 TEN1: DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. 0: DAC channel1 trigger disabled and data written into the DAC_DHRx register are transferred one APB1 clock cycle later to the DAC_DOR1 register 1: DAC channel1 trigger enabled and data from the DAC_DHRx register are transferred three APB1 clock cycles later to the DAC_DOR1 register Note: When software trigger is selected, the transfer from the DAC_DHRx register to the...
Page 432: Dac Software Trigger Register (Dac_Swtrigr)
Digital-to-analog converter (DAC1 and DAC2) RM0316 16.10.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 433: Dac Channel1 12-Bit Left-Aligned Data Holding Register
RM0316 Digital-to-analog converter (DAC1 and DAC2) 16.10.4 DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC1DHR[11:0] Res. Res.
Page 434: Dac Channel2 12-Bit Left-Aligned Data Holding Register
Digital-to-analog converter (DAC1 and DAC2) RM0316 Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 16.10.7 DAC channel2 12-bit left-aligned data holding register (DAC_DHR12L2) Address offset: 0x18 Reset value: 0x0000 0000...
Page 435: Dual Dac 12-Bit Right-Aligned Data Holding Register
RM0316 Digital-to-analog converter (DAC1 and DAC2) 16.10.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 Res. Res. Res. Res. DACC2DHR[11:0] Res. Res. Res. Res. DACC1DHR[11:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
Page 436: Dac Channel1 Data Output Register (Dac_Dor1)
Digital-to-analog converter (DAC1 and DAC2) RM0316 DACC2DHR[7:0] DACC1DHR[7:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.
Page 437 RM0316 Digital-to-analog converter (DAC1 and DAC2) Res. Res. DMAUDR2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w1 Res. Res. DMAUDR1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w1 Bits 31:30 Reserved, must be kept at reset value.
Page 438: 16.10.15 Dac Register Map
Digital-to-analog converter (DAC1 and DAC2) RM0316 16.10.15 DAC register map Table 107 summarizes the DAC registers. Table 107. DAC register map and reset values Register Offset name DAC_CR 0x00 Reset value DAC_ SWTRIGR 0x04 Reset value DAC_ DACC1DHR[11:0] DHR12R1 0x08 Reset value DAC_ DACC1DHR[11:0]...
Page 439 RM0316 Digital-to-analog converter (DAC1 and DAC2) Table 107. DAC register map (continued)and reset values (continued) Register Offset name DAC_SR 0x34 Reset value Refer to Section 3.2.2 on page 51 for the register boundary addresses. DocID022558 Rev 8 439/1141...
Page 440: Comparator (Comp)
Comparator (COMP) RM0316 Comparator (COMP) 17.1 Introduction STM32F303xB/C/D/E, STM32F358xx and STM32F398xx embed seven general purpose comparators that can be used either as standalone devices (all terminal are available on I/Os) or combined with the timers. STM32F303x6/8 and STM32F328x8 embed three comparators, COMP2, COMP4 and COMP6.
Page 441: Comp Functional Description
RM0316 Comparator (COMP) 17.3 COMP functional description 17.3.1 COMP block diagram The block diagram of the comparators is shown in Figure 122: Comparator 1 and 2 block diagrams (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE) Figure 123: STM32F303xB/C/D/E, STM32F358xC and STM32F398xE comparator 7 block diagram.
Page 442: Figure 123. Stm32F303Xb/C/D/E, Stm32F358Xc And Stm32F398Xe Comparator 7
Comparator (COMP) RM0316 Figure 123. STM32F303xB/C/D/E, STM32F358xC and STM32F398xE comparator 7 block diagram 1. Only for STM32F303xB/C and STM32F358xC Figure 124. STM32F303x6/8 and STM32F328x8 comparators 2/4/6 block diagrams 1. In STM32F303x6/8 and STM32F328x8 devices, DAC1_CH2 and DAC2_CH1 outputs are connected 442/1141 DocID022558 Rev 8...
Page 443: Comp Pins And Internal Signals
RM0316 Comparator (COMP) directly, thus PA5 and PA6 are not available as COMPx_INM (x = 2,4,6) inputs. When DAC1_OUT2 and DAC2_OUT1 are connected internally to comparator non inverting input, the I/Os on which the DAC1_OUT and DAC2_OUT1 are mapped (PA5 and PA6) can be used as GPIOs. 17.3.2 COMP pins and internal signals The I/Os used as comparators inputs must be configured in analog mode in the GPIOs...
Page 444: Comp Reset And Clocks
Comparator (COMP) RM0316 Table 108. Comparator input/output summary (continued) Comparator inputs/outputs COMP1 COMP2 COMP3 COMP4 COMP5 COMP6 COMP7 PA10 Outputs on I/Os PA12 PA11 TIM1_OCrefClear TIM1_OCrefClear TIM8_OCrefClear TIM8_OCrefClear TIM8_OCrefClear TIM1_OCrefClear TIM1_IC1 TIM2_OCrefClear TIM3_IC3 TIM2_IC1 TIM2_IC2 TIM8_OCrefClear TIM2_IC4 Outputs to TIM3_IC2 TIM3_OCrefClear TIM3_OCrefClear TIM2_OCrefClear...
Page 445: Hysteresis (On Stm32F303Xb/C And Stm32F358Xc Only)
RM0316 Comparator (COMP) 17.3.5 Hysteresis (on STM32F303xB/C and STM32F358xC only) The comparator includes a programmable hysteresis to avoid spurious output transitions in case of noisy signals. The hysteresis can be disabled if it is not needed (for instance when exiting from low-power mode) to be able to force the hysteresis value using external components.
Page 446: Power Mode (Stm32F303Xb/C And Stm32F358Xc Only)
Comparator (COMP) RM0316 Figure 126. Comparator output blanking 17.3.7 Power mode (STM32F303xB/C and STM32F358xC only) The comparator power consumption versus propagation delay can be adjusted to have the optimum trade-off for a given application.The bits COMPxMODE[1:0] in COMPx_CSR registers can be programmed as follows: •...
Page 447: Comp Registers
RM0316 Comparator (COMP) 17.5 COMP registers 17.5.1 COMP1 control and status register (COMP1_CSR) Note: This register is available in STM32F303xB/C/D/E, STM32F358xC and STM32F398xE only Address offset: 0x1C Reset value: 0x0000 0000 COMP1HYST COMP1 COMP1 COMP1_ Res. Res. Res. Res. Res. Res.
Page 448 Comparator (COMP) RM0316 Bit 14 Reserved, must be kept at reset value. Bits 13:10 COMP1OUTSEL[3:0]: Comparator 1 output selection These bits select which Timer input must be connected with the comparator1 output. 0000: No selection 0001: (BRK_ACTH) Timer 1 break input 0010: (BRK2) Timer 1 break input 2 0011: Timer 8 break input 1 0100: Timer 8 break input 2...
Page 449: Comp2 Control And Status Register (Comp2_Csr)
RM0316 Comparator (COMP) Bits 3:2 COMP1MODE[1:0]: Comparator 1 mode (only in STM32F303xB/C and STM32F358xC devices) These bits control the operating mode of the comparator1 and allows to adjust the speed/consumption. 00: High speed 01: Medium speed 10: Low-power 11: Ultra-low-power Bit 1 COMP1_INP_DAC: Comparator 1 non inverting input connection to DAC output.
Page 450 Comparator (COMP) RM0316 Bit 21 Reserved, must be kept at reset value. Bits 20:18 COMP2_BLANKING[2:0]: Comparator 2 output blanking source These bits select which Timer output controls the comparator 1 output blanking. 000: No blanking 001: TIM1 OC5 selected as blanking source 010: TIM2 OC3 selected as blanking source 011: TIM3 OC3 selected as blanking source Other configurations: reserved...
Page 451: Comp3 Control And Status Register (Comp3_Csr)
RM0316 Comparator (COMP) Bit 9 COMP2WINMODE: Comparator 2 window mode (only in STM32F303xB/C and STM32F358xC devices) This bit selects the window mode: Both non inverting inputs of comparators share the non inverting input of Comparator 1 (PA1). 0: Comparators 1 and 2 can not be used in window mode. 1: Comparators 1 and 2 can be used in window mode.
Page 452 Comparator (COMP) RM0316 Reset value: 0x0000 0000 COMP3HYST COMP COMP Res. Res. Res. Res. Res. Res. Res. Res. Res. COMP3_BLANKING 3LOCK 3OUT [1:0] COMP3 COMP3MODE COMP COMP3 INPSEL Res. COMP3OUTSEL Res. Res. COMP3INMSEL[2:0] Res. 3POL [1:0] 1. Only in STM32F303xB/C and STM32F358xC. Bit 31 COMP3LOCK: Comparator 3 lock This bit is write-once.
Page 453 RM0316 Comparator (COMP) Bits 13:10 COMP3OUTSEL[3:0]: Comparator 3 output selection These bits are set and cleared by software if the COMP3_LOCK bit is not set. These bits select which Timer input must be connected with the comparator 3 output. 0000: No timer input 0001: (BRK_ACTH) Timer 1 break input 0010: (BRK2) Timer 1 break input 2 0011: (BRK_ACTH) Timer 8 break input...
Page 454: Comp4 Control And Status Register (Comp4_Csr)
Comparator (COMP) RM0316 Bits 3:2 COMP3MODE[1:0]: Comparator 3 mode (only in STM32F303xB/C and STM32F358xC devices.) These bits control the operating mode of the comparator 3 and allows to adjust the speed/consumption. 00: Ultra-low power 01: Low-power 10: Medium speed 11: High speed Bit 1 Reserved, must be kept at reset value.
Page 455 RM0316 Comparator (COMP) Bits 20:18 COMP4_BLANKING: Comparator 4 blanking source These bits select which Timer output controls the comparator 4 output blanking. 000: No blanking 001: TIM3 OC4 selected as blanking source 010: TIM8 OC5 selected as blanking source 011: TIM15 OC1 selected as blanking source Other configurations: reserved, must be kept at reset value Note: Depending on the product, when a timer is not available, the corresponding combination is reserved.
Page 456: Comp5 Control And Status Register (Comp5_Csr)
Comparator (COMP) RM0316 Bit 9 COMP4WINMODE: Comparator 4 window mode (only in STM32F303xB/C and STM32F358xC devices) This bit selects the window mode: both non inverting inputs comparators 3 and 4 share the non inverting input of Comparator 3 (PB14 or PD14) 0: Comparators 3 and 4 can not be used in window mode.
Page 457 RM0316 Comparator (COMP) Reset value: 0x0000 0000 COMP5HYST COMP COMP Res. Res. Res. Res. Res. Res. Res. Res. Res. COMP5_BLANKING 5LOCK 5OUT [1:0] COMP5 COMP5MODE COMP COMP5 INPSEL Res. COMP5OUTSEL Res. Res. COMP5INMSEL[2:0] Res. 5POL [1:0] 1. Only in STM32F303xB/C. Bit 31 COMP5LOCK: Comparator 5 lock This bit is write-once.
Page 458 Comparator (COMP) RM0316 Bits 13:10 COMP5OUTSEL[3:0]: Comparator 5 output selection These bits select which Timer input must be connected with the comparator 5 output. 0000: No timer input selected 0001: (BRK_ACTH) Timer 1 break input 0010: (BRK2) Timer 1 break input 2 0011: (BRK_ACTH) Timer 8 break input 0100: (BRK2) Timer 8 break input 2 0101: Timer 1 break input 2 or Timer 8 break input 2...
Page 459: Comp6 Control And Status Register (Comp6_Csr)
RM0316 Comparator (COMP) Bits 3:2 COMP5MODE[1:0]: Comparator 5 mode (Only in STM32F303xB/C and STM32F358xC devices) These bits control the operating mode of the comparator 5 and allows to adjust the speed/consumption. 00: Ultra-low power 01: Low-power 10: Medium speed 11: High speed Bit 1 Reserved, must be kept at reset value.
Page 460 Comparator (COMP) RM0316 Bits 20:18 COMP6_BLANKING: Comparator 6 blanking source These bits select which Timer output controls the comparator 6 output blanking. 000: No blanking 001: Reserved 010: TIM8 OC5 selected as blanking source 011: TIM2 OC4 selected as blanking source 100: TIM15 OC2 selected as blanking source Other configurations: reserved Note: Depending on the product, when a timer is not available, the corresponding combination is...
Page 461: Comp7 Control And Status Register (Comp7_Csr)
RM0316 Comparator (COMP) Bit 9 COMP6WINMODE: Comparator 6 window mode (only in STM32F303xB/C and STM32F358xC devices) This bit selects the window mode: both non inverting inputs of comparators 6 share the non inverting input of Comparator 5 (PD12 or PB13). 0: Comparators 5 and 6 can not be used in window mode.
Page 462 Comparator (COMP) RM0316 COMP7HYST COMP COMP Res. Res. Res. Res. Res. Res. Res. Res. Res. COMP7_BLANKING 7LOCK 7OUT [1:0] COMP7 COMP7MODE COMP COMP7 INPSEL Res. COMP7OUTSEL Res. Res. COMP7INMSEL[2:0] Res. 7POL [1:0] 1. Only in STM32F303xB/C and STM32F358xC devices. Bit 31 COMP7LOCK: Comparator 7 lock This bit is write-once.
Page 463 RM0316 Comparator (COMP) Bits 13:10 COMP7OUTSEL[3:0]: Comparator 7 output selection These bits select which Timer input must be connected with the comparator 7 output. 0001: (BRK) Timer 1 break input 0010: (BRK2) Timer 1 break input 2 0011: (BRK) Timer 8 break input 0100: (BRK2) Timer 8 break input 2 0101: Timer 1 break input 2 + Timer 8 break input 2 0110: Timer 1 OCrefclear input...
Page 464: Comp Register Map
Comparator (COMP) RM0316 17.5.8 COMP register map The following table summarizes the comparator registers. Table 109. COMP register map and reset values Offset Register COMP1OUT COMP1_CSR 0x1C [3:0] Reset value COMP2OUT COMP2_CSR SEL[3:0] 0x20 Reset value COMP3OUT COMP3_CSR SEL[3:0] 0x24 Reset value COMP4OUT COMP4_CSR...
Page 465 RM0316 Comparator (COMP) Table 109. COMP register map and reset values (continued) Offset Register COMP7OUT COMP7_CSR SEL[3:0] 0x34 Reset value Refer to Section 3.2.2 on page 51 for the register boundary addresses. DocID022558 Rev 8 465/1141...
Page 466: Operational Amplifier (Opamp)
Operational amplifier (OPAMP) RM0316 Operational amplifier (OPAMP) 18.1 OPAMP introduction STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices embed 4 operational amplifiers OPAMP1, OPAMP2, OPAMP3 and OPAMP4 and STM32F303x6/8 and STM32F328x8 devices embed 1 operational amplifier OPAMP2. They can either be used as standalone amplifiers or as follower / programmable gain amplifiers.
Page 467: Clock
RM0316 Operational amplifier (OPAMP) Table 110. Connections with dedicated I/O on STM32F303xB/C/D/E, STM32F358xC and STM32F398xE OPAMP1 OPAMP2 OPAMP3 OPAMP4 OPAMP1 OPAMP2 OPAMP3 OPAMP4 inverting inverting inverting inverting inverting inverting inverting inverting input input input input input input input input PA3 (VM1) PA1 (VP0) PA5 (VM1) PA7 (VP0)
Page 468: Operational Amplifiers And Comparators Interconnections
Operational amplifier (OPAMP) RM0316 18.3.3 Operational amplifiers and comparators interconnections Internal connections between the operational amplifiers and the comparators are useful in motor control applications. These connections are summarized in the following figures. Figure 127. STM32F303xB/C/D/E, STM32F358xC and STM32F398xE Comparators and operational amplifiers interconnections (part 1) 468/1141 DocID022558 Rev 8...
Page 469: Figure 128. Stm32F303Xb/C/D/E And Stm32F358Xc Comparators And Operational
RM0316 Operational amplifier (OPAMP) Figure 128. STM32F303xB/C/D/E and STM32F358xC comparators and operational amplifiers interconnections (part 2 ) 1. Only in STM32F303xB/C and STM32F358 devices. DocID022558 Rev 8 469/1141...
Page 470: Using The Opamp Outputs As Adc Inputs
Operational amplifier (OPAMP) RM0316 Figure 129. STM32F303x6/8 and STM32F328x8 comparator and operational amplifier connections 1. DAC1_CH2 and DAC2_CH1 outputs are connected directly, thus PA5 and PA6 are not available as inputs as COMP2_INM. They can be used as GPIOs. 18.3.4 Using the OPAMP outputs as ADC inputs In order to use OPAMP outputs as ADC inputs, the operational amplifiers must be enabled and the ADC must use the OPAMP output channel number:...
Page 471: Timer Controlled Multiplexer Mode
RM0316 Operational amplifier (OPAMP) applied on the inverting and non inverting OPAMP inputs connected together. The voltage applied to both inputs of the OPAMP can be measured (the OPAMP reference voltage can be output through the TSTREF bit and connected internally to an ADC channel; refer to Section 15: Analog-to-digital converters (ADC) on page 305).
Page 472: Opamp Modes
Operational amplifier (OPAMP) RM0316 Figure 130. Timer controlled Multiplexer mode 18.3.7 OPAMP modes The operational amplifier inputs and outputs are all accessible on terminals. The amplifiers can be used in multiple configuration environments: • Standalone mode (external gain setting mode) •...
Page 473: Figure 131. Standalone Mode: External Gain Setting Mode
RM0316 Operational amplifier (OPAMP) Figure 131. Standalone mode: external gain setting mode 1. This figure gives an example in an inverting configuration. Any other option is possible, including comparator mode. Follower configuration mode The amplifier can be configured as a follower, by setting the VM_SEL bits to 11 in the OPAMPx_CR register.
Page 474: Figure 132. Follower Configuration
Operational amplifier (OPAMP) RM0316 Figure 132. Follower configuration 1. This figure gives an example in an inverting configuration. Any other option is possible, including comparator mode. Programmable Gain Amplifier mode The Programmable Gain Amplifier (PGA) mode is enabled by writing the VM_SEL bits to 10 in the OPAMPx_CR register.
Page 475: Figure 133. Pga Mode, Internal Gain Setting (X2/X4/X8/X16), Inverting Input Not Used
RM0316 Operational amplifier (OPAMP) Figure 133. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used Figure 134. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering DocID022558 Rev 8 475/1141...
Page 476: Opamp Registers
Operational amplifier (OPAMP) RM0316 18.4 OPAMP registers 18.4.1 OPAMP1 control register (OPAMP1_CSR) Note: This register is only available in STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices. Address offset : 0x38 Reset value: 0xXXXX 0000 TSTR USER_ LOCK OUTCAL TRIMOFFSETN TRIMOFFSETP PGA_GAIN TRIM VMS_SE TCM_ FORCE...
Page 477 RM0316 Operational amplifier (OPAMP) Bits 17:14 PGA_GAIN: Gain in PGA mode 0X00 = Non-inverting gain = 2 0X01 = Non-inverting gain = 4 0X10 = Non-inverting gain = 8 0X11 = Non-inverting gain = 16 1000 = Non-inverting gain = 2 - Internal feedback connected to VM0 1001 = Non-inverting gain = 4 - Internal feedback connected to VM0 1010 = Non-inverting gain = 8 - Internal feedback connected to VM0 1011 = Non-inverting gain = 16 - Internal feedback connected to VM0...
Page 478: Opamp2 Control Register (Opamp2_Csr)
Operational amplifier (OPAMP) RM0316 Bits 3:2 VP_SEL: OPAMP1 Non inverting input selection. These bits are set and cleared by software. They are used to select the OPAMP1 non inverting input. 00: PA7 used as OPAMP1 non inverting input 01: PA5 used as OPAMP1 non inverting input 10: PA3 used as OPAMP1 non inverting input 11: PA1 used as OPAMP1 non inverting input Bit 1 FORCE_VP:...
Page 479 RM0316 Operational amplifier (OPAMP) Bit 18 USER_TRIM: User trimming enable. This bit is used to configure the OPAMP offset. 0: User trimming disabled. 1: User trimming enabled. Bits 17:14 PGA_GAIN: gain in PGA mode 0X00 = Non-inverting gain = 2 0X01 = Non-inverting gain = 4 0X10 = Non-inverting gain = 8 0X11 = Non-inverting gain = 16...
Page 480: Opamp3 Control Register (Opamp3_Csr)
Operational amplifier (OPAMP) RM0316 Bit 6:5 VM_SEL: OPAMP2 inverting input selection. Theses bits are set and cleared by software. They are used to select the OPAMP2 inverting input. 00: PC5 (VM0) used as OPAMP2 inverting input 01: PA5 (VM1) used as OPAMP2 inverting input 10: Resistor feedback output (PGA mode) 11: follower mode Bit 4 Reserved, must be kept at reset value.
Page 481 RM0316 Operational amplifier (OPAMP) Bit 31 LOCK: OPAMP 3 lock This bit is write-once. It is set by software. It can only be cleared by a system reset. This bit is used to configure the OPAMP3_CSR register as read-only. 0: OPAMP3_CSR is read-write. 1: OPAMP3_CSR is read-only.
Page 482 Operational amplifier (OPAMP) RM0316 Bits 10:9 VPS_SEL: OPAMP3 non inverting input secondary selection. These bits are set/reset by software. They allow selecting the OPAMP3 non inverting input when TCM_EN = 1. 00: PB13 used as OPAMP3 non inverting input 01: PA5 used as OPAMP3 non inverting input 10: PA1 used as OPAMP3 non inverting input 11: PB0used as OPAMP3 non inverting input Bit 8 VMS_SEL: OPAMP3 inverting input secondary selection...
Page 483: Opamp4 Control Register (Opamp4_Csr)
RM0316 Operational amplifier (OPAMP) 18.4.4 OPAMP4 control register (OPAMP4_CSR) Note: This register is only available in STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices. Address offset: 0x44 Reset value: 0xXXXX 0000 TSTR USER_ LOCK TRIMOFFSETN TRIMOFFSETP PGA_GAIN TRIM VMS_ TCM_ FORCE OPAMP PGA_GAIN CALSEL VPS_SEL VM_SEL...
Page 484 Operational amplifier (OPAMP) RM0316 Bits 17:14 PGA_GAIN: Gain in PGA mode 0X00 = Non-inverting gain = 2 0X01 = Non-inverting gain = 4 0X10 = Non-inverting gain = 8 0X11 = Non-inverting gain = 16 1000 = Non-inverting gain = 2 - Internal feedback connected to VM0 1001 = Non-inverting gain = 4 - Internal feedback connected to VM0 1010 = Non-inverting gain = 8 - Internal feedback connected to VM0 1011 = Non-inverting gain = 16 - Internal feedback connected to VM0...
Page 485 RM0316 Operational amplifier (OPAMP) Bits 3:2 VP_SEL: OPAMP4 Non inverting input selection. Theses bits are set and cleared by software. They allow selecting the OPAMP4 non inverting input. 00: PD11 used as OPAMP4 non inverting input 01: PB11 used as OPAMP4 non inverting input 10: PA4 used as OPAMP4 non inverting input 11: PB13 used as OPAMP4 non inverting input Bit 1 FORCE_VP:...
Page 486: Opamp Register Map
Operational amplifier (OPAMP) RM0316 18.4.5 OPAMP register map The following table summarizes the OPAMP registers. Table 112. OPAMP register map and reset values Offset Register OPAMP1_CSR 0x38 Reset value X X X X X X X X X X X X X X X X OPAMP2_CSR 0x3C Reset value...
Page 487: Touch Sensing Controller (Tsc)
RM0316 Touch sensing controller (TSC) Touch sensing controller (TSC) 19.1 Introduction The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (for example glass, plastic).
Page 488: Tsc Functional Description
Touch sensing controller (TSC) RM0316 19.3 TSC functional description 19.3.1 TSC block diagram The block diagram of the touch sensing controller is shown in Figure 135: TSC block diagram. Figure 135. TSC block diagram 19.3.2 Surface charge transfer acquisition overview The surface charge transfer acquisition is a proven, robust and efficient way to measure a capacitance.
Page 489: Figure 136. Surface Charge Transfer Analog I/O Group Structure
RM0316 Touch sensing controller (TSC) The remaining GPIOs are dedicated to the electrodes and are commonly called channels. For some specific needs (such as proximity detection), it is possible to simultaneously enable more than one channel per analog I/O group. Figure 136.
Page 490: Reset And Clocks
Touch sensing controller (TSC) RM0316 Table 113. Acquisition sequence summary G1_IO1 G1_IO2 G1_IO3 G1_IO4 State State description (electrode) (sampling) (electrode) (electrode) Output open- Input floating drain low with Input floating with analog switch Discharge all C with analog analog switch closed switch closed closed...
Page 491: Charge Transfer Acquisition Sequence
RM0316 Touch sensing controller (TSC) 19.3.4 Charge transfer acquisition sequence An example of a charge transfer acquisition sequence is detailed in Figure 138. Figure 138. Charge transfer acquisition sequence For higher flexibility, the charge transfer frequency is fully configurable. Both the pulse high state (charge of C ) and the pulse low state (transfer of charge from C to C...
Page 492: Spread Spectrum Feature
Touch sensing controller (TSC) RM0316 19.3.5 Spread spectrum feature The spread spectrum feature allows to generate a variation of the charge transfer frequency. This is done to improve the robustness of the charge transfer acquisition in noisy environments and also to reduce the induced emission. The maximum frequency variation is in the range of 10% to 50% of the nominal charge transfer period.
Page 493: Sampling Capacitor I/O And Channel I/O Mode Selection
RM0316 Touch sensing controller (TSC) 19.3.7 Sampling capacitor I/O and channel I/O mode selection To allow the GPIOs to be controlled by the touch sensing controller, the corresponding alternate function must be enabled through the standard GPIO registers and the GPIOxAFR registers.
Page 494: Acquisition Mode
Touch sensing controller (TSC) RM0316 Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR or TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. 19.3.8 Acquisition mode The touch sensing controller offers two acquisition modes:...
Page 495: Tsc Low-Power Modes
RM0316 Touch sensing controller (TSC) 19.4 TSC low-power modes Table 116. Effect of low-power modes on TSC Mode Description No effect Sleep TSC interrupts cause the device to exit Sleep mode. Stop TSC registers are frozen The TSC stops its operation until the Stop or Standby mode is exited. Standby 19.5 TSC interrupts...
Page 496: Tsc Registers
Touch sensing controller (TSC) RM0316 19.6 TSC registers Refer to Section 2.1 on page 46 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 19.6.1 TSC control register (TSC_CR) Address offset: 0x00 Reset value: 0x0000 0000 CTPH[3:0]...
Page 497 RM0316 Touch sensing controller (TSC) Bit 16 SSE: Spread spectrum enable This bit is set and cleared by software to enable/disable the spread spectrum feature. 0: Spread spectrum disabled 1: Spread spectrum enabled Note: This bit must not be modified when an acquisition is ongoing. Bit 15 SSPSC: Spread spectrum prescaler This bit is set and cleared by software.
Page 498: Tsc Interrupt Enable Register (Tsc_Ier)
Touch sensing controller (TSC) RM0316 Bit 2 AM: Acquisition mode This bit is set and cleared by software to select the acquisition mode. 0: Normal acquisition mode (acquisition starts as soon as START bit is set) 1: Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) Note: This bit must not be modified when an acquisition is ongoing.
Page 499: Tsc Interrupt Clear Register (Tsc_Icr)
RM0316 Touch sensing controller (TSC) 19.6.3 TSC interrupt clear register (TSC_ICR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 500: Tsc Interrupt Status Register (Tsc_Isr)
Touch sensing controller (TSC) RM0316 19.6.4 TSC interrupt status register (TSC_ISR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 501: Tsc I/O Analog Switch Control Register (Tsc_Ioascr)
RM0316 Touch sensing controller (TSC) 19.6.6 TSC I/O analog switch control register (TSC_IOASCR) Address offset: 0x18 Reset value: 0x0000 0000 G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 Bits 31:0 Gx_IOy: Gx_IOy analog switch enable These bits are set and cleared by software to enable/disable the Gx_IOy analog switch.
Page 502: Tsc I/O Channel Control Register (Tsc_Ioccr)
Touch sensing controller (TSC) RM0316 19.6.8 TSC I/O channel control register (TSC_IOCCR) Address offset: 0x28 Reset value: 0x0000 0000 G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 Bits 31:0 Gx_IOy: Gx_IOy channel mode These bits are set and cleared by software to configure the Gx_IOy as a channel I/O.
Page 503: Tsc I/O Group X Counter Register (Tsc_Iogxcr) (X = 1
RM0316 Touch sensing controller (TSC) Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 GxS: Analog I/O group x status These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. 0: Acquisition on analog I/O group x is ongoing or not started 1: Acquisition on analog I/O group x is complete Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O...
Page 504: Tsc Register Map
Touch sensing controller (TSC) RM0316 19.6.11 TSC register map Table 118. TSC register map and reset values Offset Register CTPH[3:0] CTPL[3:0] SSD[6:0] TSC_CR [2:0] 0x0000 Reset value TSC_IER 0x0004 Reset value TSC_ICR 0x0008 Reset value TSC_ISR 0x000C Reset value TSC_IOHCR 0x0010 Reset value 0x0014...
Page 505 RM0316 Touch sensing controller (TSC) Table 118. TSC register map and reset values (continued) Offset Register CNT[13:0] TSC_IOG3CR 0x003C Reset value CNT[13:0] TSC_IOG4CR 0x0040 Reset value CNT[13:0] TSC_IOG5CR 0x0044 Reset value CNT[13:0] TSC_IOG6CR 0x0048 Reset value CNT[13:0] TSC_IOG7CR 0x004C Reset value CNT[13:0] TSC_IOG8CR 0x0050...
Page 506: Advanced-Control Timers (Tim1/Tim8/Tim20)
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Advanced-control timers (TIM1/TIM8/TIM20) 20.1 TIM1/TIM8/TIM20 introduction The advanced-control timers (TIM1/TIM8/TIM20) consist of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 507: Figure 140. Advanced-Control Timer Block Diagram
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 140. Advanced-control timer block diagram 1. The internal break event source can be: A clock failure event generated by CSS. For further information on the CSS, refer to Section 8.2.7: Clock security system (CSS) A PVD output SRAM parity error signal ®...
Page 508: Tim1/Tim8/Tim20 Functional Description
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 20.3 TIM1/TIM8/TIM20 functional description 20.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 509: Figure 141. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 141. Counter timing diagram with prescaler division change from 1 to 2 Figure 142. Counter timing diagram with prescaler division change from 1 to 4 DocID022558 Rev 8 509/1141...
Page 510: Counter Modes
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 20.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1.
Page 511: Figure 143. Counter Timing Diagram, Internal Clock Divided By 1
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 143. Counter timing diagram, internal clock divided by 1 Figure 144. Counter timing diagram, internal clock divided by 2 DocID022558 Rev 8 511/1141...
Page 512: Figure 145. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Figure 145. Counter timing diagram, internal clock divided by 4 Figure 146. Counter timing diagram, internal clock divided by N 512/1141 DocID022558 Rev 8...
Page 513: Figure 147. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded)
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 147. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) Figure 148. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) DocID022558 Rev 8 513/1141...
Page 514 Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1.
Page 515: Figure 149. Counter Timing Diagram, Internal Clock Divided By 1
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 149. Counter timing diagram, internal clock divided by 1 Figure 150. Counter timing diagram, internal clock divided by 2 DocID022558 Rev 8 515/1141...
Page 516: Figure 151. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Figure 151. Counter timing diagram, internal clock divided by 4 Figure 152. Counter timing diagram, internal clock divided by N 516/1141 DocID022558 Rev 8...
Page 517: Figure 153. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 153. Counter timing diagram, update event when repetition counter is not used Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto- reload value down to 1 and generates a counter underflow event.
Page 518: Figure 154. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 519: Figure 155. Counter Timing Diagram, Internal Clock Divided By 2
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 155. Counter timing diagram, internal clock divided by 2 Figure 156. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 DocID022558 Rev 8 519/1141...
Page 520: Figure 157. Counter Timing Diagram, Internal Clock Divided By N
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Figure 157. Counter timing diagram, internal clock divided by N Figure 158. Counter timing diagram, update event with ARPE=1 (counter underflow) 520/1141 DocID022558 Rev 8...
Page 521: Repetition Counter
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 159. Counter timing diagram, Update event with ARPE=1 (counter overflow) 20.3.3 Repetition counter Section 20.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows. It is actually generated only when the repetition counter has reached zero.
Page 522: Figure 160. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 In Center aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was launched: if the RCR was written before launching the counter, the UEV occurs on the overflow.
Page 523: External Trigger Input
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) 20.3.4 External trigger input The timer features an external trigger input ETR. It can be used as: • external clock (external clock mode 2, see Section 20.3.5) • trigger for the slave mode (see Section 20.3.25) •...
Page 524: Clock Selection
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 20.3.5 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Encoder mode Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed...
Page 525: Figure 163. Ti2 External Clock Connection Example
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 163. TI2 external clock connection example For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 526: Figure 164. Control Circuit In External Clock Mode 1
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Figure 164. Control circuit in external clock mode 1 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 165 gives an overview of the external trigger input block.
Page 527: Figure 166. Control Circuit In External Clock Mode 2
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 528: Capture/Compare Channels
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 20.3.6 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler, except for channels 5 and 6) and an output stage (with comparator and output control). Figure 167 Figure 170 give an overview of one Capture/Compare channel.
Page 529: Figure 168. Capture/Compare Channel 1 Main Circuit
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 168. Capture/compare channel 1 main circuit DocID022558 Rev 8 529/1141...
Page 530: Figure 169. Output Stage Of Capture/Compare Channel (Channel 1, Idem Ch. 2 And 3)
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Figure 169. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) 1. OCxREF, where x is the rank of the complementary channel Figure 170. Output stage of capture/compare channel (channel 4) 530/1141 DocID022558 Rev 8...
Page 531: Input Capture Mode
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 171. Output stage of capture/compare channel (channel 5, idem ch. 6) 1. Not available externally. The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 532: Pwm Input Mode
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. • Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP bits to 0 in the TIMx_CCER register (rising edge in this case). •...
Page 533: Forced Output Mode
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) For example, the user can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): • Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).
Page 534: Output Compare Mode
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below. 20.3.10 Output compare mode This function is used to control an output waveform or indicate when a period of time has...
Page 535: Pwm Mode
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 173. Output compare mode, toggle on OC1 20.3.11 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 536: Figure 174. Edge-Aligned Pwm Waveforms (Arr=8)
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 510. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <...
Page 537: Figure 175. Center-Aligned Pwm Waveforms (Arr=8)
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting) on page 517. Figure 175 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, •...
Page 538: Asymmetric Pwm Mode
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 539: Combined Pwm Mode
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 176. Generation of 2 phase-shifted PWM signals with 50% duty cycle 20.3.13 Combined PWM mode Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers.
Page 540: Combined 3-Phase Pwm Mode
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Figure 177. Combined PWM mode on channel 1 and 3 20.3.14 Combined 3-phase PWM mode Combined 3-phase PWM mode allows one to three center-aligned PWM signals to be generated with a single programmable signal ANDed in the middle of the pulses. The OC5REF signal is used to define the resulting combined signal.
Page 541: Complementary Outputs And Dead-Time Insertion
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 178. 3-phase combined PWM signals with multiple trigger pulses per period The TRGO2 waveform shows how the ADC can be synchronized on given 3-phase PWM signals. Please refer to Section 20.3.26: ADC synchronization for more details. 20.3.15 Complementary outputs and dead-time insertion The advanced-control timers (TIM1/TIM8/TIM20) can output two complementary signals...
Page 542: Figure 179. Complementary Output With Dead-Time Insertion
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: •...
Page 543: Using The Break Function
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 181. Dead-time waveforms with delay greater than the positive pulse The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 20.4.18: TIM1/TIM8/TIM20 break and dead-time register (TIMx_BDTR) for delay calculation.
Page 544 Advanced-control timers (TIM1/TIM8/TIM20) RM0316 The source for BRK_ACTH can be : – A clock failure event generated by the CSS. For further information on the CSS, refer to Section 9.2.7: Clock security system (CSS) – COMP1/2/3/5/6 output – A PVD output –...
Page 545 RM0316 Advanced-control timers (TIM1/TIM8/TIM20) When one of the breaks occurs (selected level on one of the break inputs): • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the GPIO controller (selected by the OSSI bit). This feature is enabled even if the MCU oscillator is off.
Page 546: Figure 182. Various Output Behavior In Response To A Break Event On Bkin (Ossi = 1)
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Figure 182. Various output behavior in response to a break event on BKIN (OSSI = 1) 546/1141 DocID022558 Rev 8...
Page 547: Table 119. Behavior Of Timer Outputs Versus Brk/Brk2 Inputs
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) The two break inputs have different behaviors on timer outputs: – The BRK input can either disable (inactive state) or force the PWM outputs to a predefined safe state. – BRK2 can only disable (inactive state) the PWM outputs. The BRK has a higher priority than BRK2 input, as described in Table 119.
Page 548: Clearing The Ocxref Signal On An External Event
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Figure 184. PWM output state following BKIN assertion (OSSI=0) 20.3.17 Clearing the OCxREF signal on an external event The OCxREF signal of a given channel can be cleared when a high level is applied on the ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1).
Page 549: Figure 185. Clearing Timx Ocxref
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 185. Clearing TIMx OCxREF Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at the next counter overflow. DocID022558 Rev 8 549/1141...
Page 550: 6-Step Pwm Generation
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 20.3.18 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 551: One-Pulse Mode
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) 20.3.19 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 552: Retriggerable One Pulse Mode (Opm)
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 553: Encoder Interface Mode
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 188. Retriggerable one pulse mode 20.3.21 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’...
Page 554: Table 120. Counting Direction Versus Encoder Signals
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Table 120. Counting direction versus encoder signals Level on TI1FP1 signal TI2FP2 signal opposite signal (TI1FP1 Active edge for TI2, Rising Falling Rising Falling TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count...
Page 555: Uif Bit Remapping
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Figure 190 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 190. Example of encoder interface mode with TI1FP1 polarity inverted. The timer, when configured in Encoder Interface mode provides information on the sensor’s current position.
Page 556: Timer Input Xor Function
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 20.3.23 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of an XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 557 RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Example: you want to change the PWM configuration of your advanced-control timer TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers. • Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the TIMx_CR2 register to ‘1’, •...
Page 558: Figure 192. Example Of Hall Sensor Interface
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Figure 192. Example of Hall sensor interface 558/1141 DocID022558 Rev 8...
Page 559: Timer Synchronization
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) 20.3.25 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. They can be synchronized in several modes: Reset mode, Gated mode, and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 560: Figure 194. Control Circuit In Gated Mode
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 561: Figure 195. Control Circuit In Trigger Mode
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
Page 562: Figure 196. Control Circuit In External Clock Mode 2 + Trigger Mode
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: – ETF = 0000: no filter – ETPS=00: prescaler disabled – ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2.
Page 563: Adc Synchronization
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) 20.3.26 ADC synchronization The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events. It is also possible to generate a pulse issued by internal edge detectors, such as: –...
Page 564: Debug Mode
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 This is done in the following steps: Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers.
Page 565: Tim1/Tim8/Tim20 Registers
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) 20.4 TIM1/TIM8/TIM20 registers Refer to for a list of abbreviations used in register descriptions. 20.4.1 TIM1/TIM8/TIM20 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 UIFRE Res. Res. Res. Res. Res. CKD[1:0] ARPE CMS[1:0] UDIS Bits 15:12 Reserved, must be kept at reset value.
Page 566: Tim1/Tim8/Tim20 Control Register 2 (Timx_Cr2)
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled.
Page 567 RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 MMS2[3:0]: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: 0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2).
Page 568 Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Bit 11 OIS2N: Output Idle state 2 (OC2N output) Refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) Refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Page 569: Tim1/Tim8/Tim20 Slave Mode Control Register (Timx_Smcr)
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output.
Page 570 Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Bits 13:12 ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4...
Page 571: Tim1/Tim8/Tim20 Dma/Interrupt Enable Register (Timx_Dier)
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 572 Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bit 13 COMDE: COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled...
Page 573: Tim1/Tim8/Tim20 Status Register (Timx_Sr)
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 20.4.5...
Page 574 Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred. 1: An active level has been detected on the break input.
Page 575: Tim1/Tim8/Tim20 Event Generation Register (Timx_Egr)
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) 20.4.6 TIM1/TIM8/TIM20 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. COMG CC4G CC3G CC2G CC1G Bits 15:9 Reserved, must be kept at reset value. Bit 8 B2G: Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 576: Tim1/Tim8/Tim20 Capture/Compare Mode Register 1 (Timx_Ccmr1)
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Page 577 RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Bit 15 OC2CE: Output Compare 2 clear enable Bits 14:12 OC2M[2:0]: Output Compare 2 mode Bit 11 OC2PE: Output Compare 2 preload enable Bit 10 OC2FE: Output Compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input.
Page 578 Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 579: Input Capture Mode
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 580: Tim1/Tim8/Tim20 Capture/Compare Mode Register 2 (Timx_Ccmr2)
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 581 RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Output compare mode Bits 31:25 Reserved, must be kept at reset value. Bit 24 OC4M[3]: Output Compare 4 mode - bit 3 Bits 23:17 Reserved, must be kept at reset value. Bit 16 OC3M[3]: Output Compare 3 mode - bit 3 Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable...
Page 582: Tim1/Tim8/Tim20 Capture/Compare Enable Register (Timx_Ccer)
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Bits 7:4 IC3F: Input capture 3 filter Bits 3:2 IC3PSC: Input capture 3 prescaler Bits 1:0 CC3S: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC.
Page 583 RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Bit 9 CC3P: Capture/Compare 3 output polarity Refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable Refer to CC1E description Bit 7 CC2NP: Capture/Compare 2 complementary output polarity Refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 complementary output enable Refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output polarity Refer to CC1P description...
Page 584 Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. 00: non-inverted/rising edge.
Page 585: Table 122. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Table 122. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state Output disabled (not driven by the timer: Hi-Z) OCx=0, OCxN=0 Output disabled (not driven OCxREF + Polarity...
Page 586: Tim1/Tim8/Tim20 Counter (Timx_Cnt)
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 20.4.10 TIM1/TIM8/TIM20 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Re s. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bit 31 UIFCPY: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.
Page 587: Tim1/Tim8/Tim20 Repetition Counter Register (Timx_Rcr)
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) 20.4.13 TIM1/TIM8/TIM20 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 REP[15:0] Bits 15:0 REP[15:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 588: Tim1/Tim8/Tim20 Capture/Compare Register 2 (Timx_Ccr2)
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 20.4.15 TIM1/TIM8/TIM20 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
Page 589: Tim1/Tim8/Tim20 Capture/Compare Register 4 (Timx_Ccr4)
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) 20.4.17 TIM1/TIM8/TIM20 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
Page 590 Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Bit 24 BK2E: Break 2 enable 0: Break input BRK2 disabled 1; Break input BRK2 enabled Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 591 RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Bit 15 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.
Page 592: Tim1/Tim8/Tim20 Dma Control Register (Timx_Dcr)
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 20.4.9: TIM1/TIM8/TIM20 capture/compare enable register (TIMx_CCER)).
Page 593: Tim1/Tim8/Tim20 Dma Address For Full Transfer (Timx_Dmar)
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers.
Page 594: Tim1/Tim8/Tim20 Option Registers (Timx_Or)
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Bits 31:0 DMAB[31:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
Page 595: Tim1/Tim8/Tim20 Capture/Compare Mode Register 3 (Timx_Ccmr3)
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Bits 1:0 TIM1_ETR_ADC1_RMP[1:0]: TIM1_ETR_ADC1 remapping capability 00: TIM1_ETR is not connected to any AWD 01: TIM1_ETR is connected to ADC1 AWD1 10: TIM1_ETR is connected to ADC1 AWD2 11: TIM1_ETR is connected to ADC1 AWD3 Note: ADC1 AWD is ‘ORed’ with the other TIM1_ETR source signals. It is consequently necessary to disable by software other sources (input pins).
Page 596: Tim1/Tim8/Tim20 Capture/Compare Register 5 (Timx_Ccr5)
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Bits 9:8 Reserved, must be kept at reset value. Bit 7 OC5CE: Output compare 5 clear enable Bits 6:4 OC5M: Output compare 5 mode Bit 3 OC5PE: Output compare 5 preload enable Bit 2 OC5FE: Output compare 5 fast enable Bits 1:0 Reserved, must be kept at reset value.
Page 597: Tim1/Tim8/Tim20 Capture/Compare Register 6 (Timx_Ccr6)
RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Bit 29 GC5C1: Group Channel 5 and Channel 1 Distortion on Channel 1 output: 0: No effect of OC5REF on OC1REFC5 1: OC1REFC is the logical AND of OC1REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1).
Page 598: Tim1/Tim8/Tim20 Register Map
Advanced-control timers (TIM1/TIM8/TIM20) RM0316 20.4.25 TIM1/TIM8/TIM20 register map TIM1/TIM8/TIM20 registers are mapped as 16-bit addressable registers as described in the table below: Table 123. TIM1/TIM8/TIM20 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS2[3:0] [2:0] 0x04 Reset value...
Page 599 RM0316 Advanced-control timers (TIM1/TIM8/TIM20) Table 123. TIM1/TIM8/TIM20 register map and reset values (continued) Offset Register TIMx_PSC PSC[15:0] 0x28 Reset value TIMx_ARR ARR[15:0] 0x2C Reset value TIMx_RCR REP[15:0] 0x30 Reset value TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reset value TIMx_CCR3 CCR3[15:0] 0x3C...
Page 600 Advanced-control timers (TIM1/TIM8/TIM20) RM0316 Table 123. TIM1/TIM8/TIM20 register map and reset values (continued) Offset Register TIMx_CCMR3 OC6M OC5M Output [2:0] [2:0] 0x54 Compare mode Reset value TIMx_CCR5 CCR5[15:0] 0x58 Reset value TIMx_CCR6 CCR6[15:0] 0x5C Reset value Refer to Section 3.2.2: Memory map and register boundary addresses for the register boundary addresses.
Page 601: General-Purpose Timers (Tim2/Tim3/Tim4)
RM0316 General-purpose timers (TIM2/TIM3/TIM4) General-purpose timers (TIM2/TIM3/TIM4) 21.1 TIM2/TIM3/TIM4 introduction The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
Page 602: Figure 197. General-Purpose Timer Block Diagram
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Figure 197. General-purpose timer block diagram 602/1141 DocID022558 Rev 8...
Page 603: Tim2/Tim3/Tim4 Functional Description
RM0316 General-purpose timers (TIM2/TIM3/TIM4) 21.3 TIM2/TIM3/TIM4 functional description 21.3.1 Time-base unit The main block of the programmable timer is a 16-bit/32-bit counter with its related auto- reload register. The counter can count up, down or both up and down but also down or both up and down.
Page 604: Figure 198. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Figure 198. Counter timing diagram with prescaler division change from 1 to 2 Figure 199. Counter timing diagram with prescaler division change from 1 to 4 604/1141 DocID022558 Rev 8...
Page 605: Counter Modes
RM0316 General-purpose timers (TIM2/TIM3/TIM4) 21.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 606: Figure 201. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Figure 201. Counter timing diagram, internal clock divided by 2 Figure 202. Counter timing diagram, internal clock divided by 4 606/1141 DocID022558 Rev 8...
Page 607: Figure 203. Counter Timing Diagram, Internal Clock Divided By N
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Figure 203. Counter timing diagram, internal clock divided by N Figure 204. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) DocID022558 Rev 8 607/1141...
Page 608: Figure 205. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Figure 205. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.
Page 609: Figure 206. Counter Timing Diagram, Internal Clock Divided By 1
RM0316 General-purpose timers (TIM2/TIM3/TIM4) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 206. Counter timing diagram, internal clock divided by 1 Figure 207. Counter timing diagram, internal clock divided by 2 DocID022558 Rev 8 609/1141...
Page 610: Figure 208. Counter Timing Diagram, Internal Clock Divided By 4
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Figure 208. Counter timing diagram, internal clock divided by 4 Figure 209. Counter timing diagram, internal clock divided by N 610/1141 DocID022558 Rev 8...
Page 611: Figure 210. Counter Timing Diagram, Update Event When Repetition Counter
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Figure 210. Counter timing diagram, Update event when repetition counter is not used Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto- reload value down to 1 and generates a counter underflow event.
Page 612: Figure 211. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
General-purpose timers (TIM2/TIM3/TIM4) RM0316 DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 613: Figure 212. Counter Timing Diagram, Internal Clock Divided By 2
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Figure 212. Counter timing diagram, internal clock divided by 2 Figure 213. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. DocID022558 Rev 8 613/1141...
Page 614: Figure 214. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Figure 214. Counter timing diagram, internal clock divided by N Figure 215. Counter timing diagram, Update event with ARPE=1 (counter underflow) 614/1141 DocID022558 Rev 8...
Page 615: Clock Selection
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Figure 216. Counter timing diagram, Update event with ARPE=1 (counter overflow) 21.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (TIx) •...
Page 616: Figure 217. Control Circuit In Normal Mode, Internal Clock Divided By 1
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Figure 217. Control circuit in normal mode, internal clock divided by 1 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 218.
Page 617: Figure 219. Control Circuit In External Clock Mode 1
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the TIMx_CCMR1 register. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). Note: The capture prescaler is not used for triggering, so you don’t need to configure it.
Page 618: Figure 220. External Trigger Input Block
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Figure 220. External trigger input block For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register...
Page 619: Capture/Compare Channels
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Figure 221. Control circuit in external clock mode 2 21.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Page 620: Figure 222. Capture/Compare Channel (Example: Channel 1 Input Stage)
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Figure 222. Capture/compare channel (example: channel 1 input stage) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 223. Capture/compare channel 1 main circuit 620/1141 DocID022558 Rev 8...
Page 621: Input Capture Mode
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Figure 224. Output stage of capture/compare channel (channel 1) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 622: Pwm Input Mode
General-purpose timers (TIM2/TIM3/TIM4) RM0316 detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP and CC1NP bits to 000 in the TIMx_CCER register (rising edge in this case). Program the input prescaler.
Page 623: Forced Output Mode
RM0316 General-purpose timers (TIM2/TIM3/TIM4) For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).
Page 624: Output Compare Mode
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. 21.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has...
Page 625: Pwm Mode
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Figure 226. Output compare mode, toggle on OC1 21.3.9 PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 626: Figure 227. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM2/TIM3/TIM4) RM0316 The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode on page 605.
Page 627: Figure 228. Center-Aligned Pwm Waveforms (Arr=8)
RM0316 General-purpose timers (TIM2/TIM3/TIM4) compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting) on page 611.
Page 628: Asymmetric Pwm Mode
General-purpose timers (TIM2/TIM3/TIM4) RM0316 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 629: Combined Pwm Mode
RM0316 General-purpose timers (TIM2/TIM3/TIM4) 21.3.11 Combined PWM mode Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers.
Page 630: Clearing The Ocxref Signal On An External Event
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Figure 230. Combined PWM mode on channels 1 and 3 21.3.12 Clearing the OCxREF signal on an external event The OCxREF signal of a given channel can be cleared when a high level is applied on the ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1).
Page 631: Figure 231. Clearing Timx Ocxref
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Figure 231 shows the behavior of the OCxREF signal when the ETRF input becomes high, for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in PWM mode. Figure 231. Clearing TIMx OCxREF Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter overflow.
Page 632: One-Pulse Mode
General-purpose timers (TIM2/TIM3/TIM4) RM0316 21.3.13 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 633: Retriggerable One Pulse Mode (Opm)
RM0316 General-purpose timers (TIM2/TIM3/TIM4) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 634: Encoder Interface Mode
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Figure 233. Retriggerable one pulse mode 21.3.15 Encoder interface mode To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges.
Page 635: Table 124. Counting Direction Versus Encoder Signals
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Table 124. Counting direction versus encoder signals Level on opposite TI1FP1 signal TI2FP2 signal Active edge signal (TI1FP1 for Rising Falling Rising Falling TI2, TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count...
Page 636: Uif Bit Remapping
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Figure 235. Example of encoder interface mode with TI1FP1 polarity inverted The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode.
Page 637: Timers And External Trigger Synchronization
RM0316 General-purpose timers (TIM2/TIM3/TIM4) 21.3.18 Timers and external trigger synchronization The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 638: Figure 237. Control Circuit In Gated Mode
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register.
Page 639: Figure 238. Control Circuit In Trigger Mode
RM0316 General-purpose timers (TIM2/TIM3/TIM4) CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
Page 640: Timer Synchronization
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: – ETF = 0000: no filter – ETPS=00: prescaler disabled – ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2.
Page 641 RM0316 General-purpose timers (TIM2/TIM3/TIM4) Figure 240. Master/Slave timer example Using one timer as prescaler for another timer For example, you can configure TIM3 to act as a prescaler for TIM2. Refer to Figure 240. To do this: Configure TIM3 in master mode so that it outputs a periodic trigger signal on each update event UEV.
Page 642: Figure 241. Gating Tim2 With Oc1Ref Of Tim3
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Figure 241. Gating TIM2 with OC1REF of TIM3 In the example in Figure 241, the TIM2 counter and prescaler are not initialized before being started. So they start counting from their current value. It is possible to start from a given value by resetting both timers before starting TIM3.
Page 643: Figure 242. Gating Tim2 With Enable Of Tim3
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Figure 242. Gating TIM2 with Enable of TIM3 Using one timer to start another timer In this example, we set the enable of Timer 2 with the update event of Timer 3. Refer to Figure 240 for connections.
Page 644: Figure 244. Triggering Tim2 With Enable Of Tim3
General-purpose timers (TIM2/TIM3/TIM4) RM0316 As in the previous example, you can initialize both counters before starting counting. Figure 244 shows the behavior with the same configuration as in Figure 243 but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register). Figure 244.
Page 645: Dma Burst Mode
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Figure 245. Triggering TIM3 and TIM2 with TIM3 TI1 input Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 21.3.20 DMA burst mode The TIMx timers have the capability to generate multiple DMA requests upon a single event.
Page 646: Debug Mode
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. –...
Page 647: Tim2/Tim3/Tim4 Registers
RM0316 General-purpose timers (TIM2/TIM3/TIM4) 21.4 TIM2/TIM3/TIM4 registers Refer to Section 2.1 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 21.4.1 TIMx control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 Res.
Page 648: Timx Control Register 2 (Timx_Cr2)
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled.
Page 649 RM0316 General-purpose timers (TIM2/TIM3/TIM4) Bits 6:4 MMS: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
Page 650: Timx Slave Mode Control Register (Timx_Smcr)
General-purpose timers (TIM2/TIM3/TIM4) RM0316 21.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMS[3] ETPS[1:0] ETF[3:0] TS[2:0] OCCS SMS[2:0] Bits 31:17 Reserved, must be kept at reset value. Bit 16 SMS[3]: Slave mode selection - bit 3 Refer to SMS description - bits 2:0 Bit 15 ETP: External trigger polarity...
Page 651 RM0316 General-purpose timers (TIM2/TIM3/TIM4) Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 652: Table 125. Timx Internal Trigger Connection
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Bits 6:4 TS: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0). reserved 001: Internal Trigger 1 (ITR1). 010: Internal Trigger 2 (ITR2). 011: Internal Trigger 3 (ITR3). reserved 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2)
Page 653: Timx Dma/Interrupt Enable Register (Timx_Dier)
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Table 125. TIMx internal trigger connection (continued) Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM3 TIM1 TIM2 TIM5 TIM4 TIM4 TIM1 TIM2 TIM3 TIM8 21.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000...
Page 654: Timx Status Register (Timx_Sr)
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled.
Page 655: Timx Event Generation Register (Timx_Egr)
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Bit 2 CC2IF: Capture/Compare 2 interrupt flag Refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description) and in retriggerable one pulse mode.
Page 656: Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Bit 2 CC2G: Capture/compare 2 generation Refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Page 657 RM0316 General-purpose timers (TIM2/TIM3/TIM4) Bits 14:12 OC2M[2:0]: Output compare 2 mode refer to OC1M description on bits 6:4 Bit 11 OC2PE: Output compare 2 preload enable Bit 10 OC2FE: Output compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input.
Page 658 General-purpose timers (TIM2/TIM3/TIM4) RM0316 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 659: Input Capture Mode
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 660: Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 661 RM0316 General-purpose timers (TIM2/TIM3/TIM4) Output compare mode Bits 31:25 Reserved, always read as 0. Bit 24 OC4M[3]: Output Compare 2 mode - bit 3 Bits 23:17 Reserved, always read as 0. Bit 16 OC3M[3]: Output Compare 1 mode - bit 3 Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register)
Page 663: Timx Counter (Timx_Cnt)
RM0316 General-purpose timers (TIM2/TIM3/TIM4) Bit 2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
Page 664: Timx Prescaler (Timx_Psc)
General-purpose timers (TIM2/TIM3/TIM4) RM0316 Bit 31 Value depends on IUFREMAP in TIMx_CR1. If UIFREMAP = 0 CNT[31]: Most significant bit of counter value (on TIM2 ) Reserved on other timers If UIFREMAP = 1 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register Bits 30:16 CNT[30:16]: Most significant part counter value (on TIM2 ) Bits 15:0 CNT[15:0]: Least significant part of counter value 21.4.11...
Page 665: Timx Capture/Compare Register 1 (Timx_Ccr1)
RM0316 General-purpose timers (TIM2/TIM3/TIM4) 21.4.13 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[31:16] (depending on timers) rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r CCR1[15:0] rw/r rw/r rw/r rw/r rw/r rw/r...
Page 666: Timx Capture/Compare Register 3 (Timx_Ccr3)
General-purpose timers (TIM2/TIM3/TIM4) RM0316 21.4.15 TIMx capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 CCR3[31:16] (depending on timers) rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r CCR3[15:0] rw/r rw/r rw/r rw/r rw/r rw/r...
Page 667: Timx Dma Control Register (Timx_Dcr)
RM0316 General-purpose timers (TIM2/TIM3/TIM4) 21.4.17 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0] Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address).
Page 668: Timx Register Map
General-purpose timers (TIM2/TIM3/TIM4) RM0316 21.4.19 TIMx register map TIMx registers are mapped as described in the table below: Table 127. TIM2/TIM3/TIM4 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS TIMx_SMCR ETF[3:0] TS[2:0]...
Page 669 RM0316 General-purpose timers (TIM2/TIM3/TIM4) Table 127. TIM2/TIM3/TIM4 register map and reset values (continued) Offset Register CNT[30:16] TIMx_CNT CNT[15:0] (TIM2 only, reserved on the other timers) 0x24 Reset value TIMx_PSC PSC[15:0] 0x28 Reset value ARR[31:16] TIMx_ARR ARR[15:0] (TIM2 a only, reserved on the other timers) 0x2C Reset value 0x30...
Page 670: Basic Timers (Tim6/Tim7)
Basic timers (TIM6/TIM7) RM0316 Basic timers (TIM6/TIM7) 22.1 TIM6/TIM7 introduction The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used as generic timers for time-base generation but they are also specifically used to drive the digital-to-analog converter (DAC).
Page 671: Tim6/Tim7 Functional Description
RM0316 Basic timers (TIM6/TIM7) 22.3 TIM6/TIM7 functional description 22.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 672: Figure 247. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Basic timers (TIM6/TIM7) RM0316 Figure 247. Counter timing diagram with prescaler division change from 1 to 2 Figure 248. Counter timing diagram with prescaler division change from 1 to 4 672/1141 DocID022558 Rev 8...
Page 673: Counting Mode
RM0316 Basic timers (TIM6/TIM7) 22.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 674: Figure 250. Counter Timing Diagram, Internal Clock Divided By 2
Basic timers (TIM6/TIM7) RM0316 Figure 250. Counter timing diagram, internal clock divided by 2 Figure 251. Counter timing diagram, internal clock divided by 4 674/1141 DocID022558 Rev 8...
Page 675: Figure 252. Counter Timing Diagram, Internal Clock Divided By N
RM0316 Basic timers (TIM6/TIM7) Figure 252. Counter timing diagram, internal clock divided by N Figure 253. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) DocID022558 Rev 8 675/1141...
Page 676: Uif Bit Remapping
Basic timers (TIM6/TIM7) RM0316 Figure 254. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) 22.3.3 UIF bit remapping The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into the timer counter register’s bit 31 (TIMxCNT[31]). This allows to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag.
Page 677: Debug Mode
RM0316 Basic timers (TIM6/TIM7) Figure 255. Control circuit in normal mode, internal clock divided by 1 22.3.5 Debug mode ® When the microcontroller enters the debug mode (Cortex-M4 F core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module.
Page 678 Basic timers (TIM6/TIM7) RM0316 Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the CEN bit).
Page 679: Tim6/Tim7 Control Register 2 (Timx_Cr2)
RM0316 Basic timers (TIM6/TIM7) 22.4.2 TIM6/TIM7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 MMS[2:0] Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 680: Tim6/Tim7 Status Register (Timx_Sr)
Basic timers (TIM6/TIM7) RM0316 22.4.4 TIM6/TIM7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred.
Page 681: Tim6/Tim7 Prescaler (Timx_Psc)
RM0316 Basic timers (TIM6/TIM7) Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. Bits 30:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value 22.4.7 TIM6/TIM7 prescaler (TIMx_PSC)
Page 682: Tim6/Tim7 Register Map
Basic timers (TIM6/TIM7) RM0316 22.4.9 TIM6/TIM7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 128. TIM6/TIM7 register map and reset values Offset Register TIMx_CR1 0x00 Reset value TIMx_CR2 [2:0] 0x04 Reset value 0x08 Reserved TIMx_DIER...
Page 683: General-Purpose Timers (Tim15/Tim16/Tim17)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) General-purpose timers (TIM15/TIM16/TIM17) 23.1 TIM15/TIM16/TIM17 introduction The TIM15/TIM16/TIM17 timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 684: Tim16/Tim17 Main Features
General-purpose timers (TIM15/TIM16/TIM17) RM0316 23.3 TIM16/TIM17 main features The TIM16/TIM17 timers include the following features: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535 •...
Page 685: Figure 256. Tim15 Block Diagram
RM0316 General-purpose timers (TIM15/TIM16/TIM17) Figure 256. TIM15 block diagram 1. The internal break event source can be: A clock failure event generated by CSS. For further information on the CSS, refer to Section 9.2.7: Clock security system (CSS) A PVD output SRAM parity error signal ®...
Page 686: Figure 257. Tim16/Tim17 Block Diagram
General-purpose timers (TIM15/TIM16/TIM17) RM0316 Figure 257. TIM16/TIM17 block diagram 1. The internal break event source can be: A clock failure event generated by CSS. For further information on the CSS, refer to Section 9.2.7: Clock security system (CSS) A PVD output SRAM parity error signal ®...
Page 687: Tim15/Tim16/Tim17 Functional Description
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.4 TIM15/TIM16/TIM17 functional description 23.4.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 688: Figure 258. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM15/TIM16/TIM17) RM0316 Figure 258. Counter timing diagram with prescaler division change from 1 to 2 Figure 259. Counter timing diagram with prescaler division change from 1 to 4 688/1141 DocID022558 Rev 8...
Page 689: Counter Modes
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.4.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR).
Page 690: Figure 260. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM15/TIM16/TIM17) RM0316 Figure 260. Counter timing diagram, internal clock divided by 1 Figure 261. Counter timing diagram, internal clock divided by 2 690/1141 DocID022558 Rev 8...
Page 691: Figure 262. Counter Timing Diagram, Internal Clock Divided By 4
RM0316 General-purpose timers (TIM15/TIM16/TIM17) Figure 262. Counter timing diagram, internal clock divided by 4 Figure 263. Counter timing diagram, internal clock divided by N DocID022558 Rev 8 691/1141...
Page 692 General-purpose timers (TIM15/TIM16/TIM17) RM0316 Figure 264. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) Figure 265. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) 692/1141 DocID022558 Rev 8...
Page 693: Repetition Counter
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.4.3 Repetition counter Section 23.4.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals. This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N counter overflows, where N is the...
Page 694: Clock Selection
General-purpose timers (TIM15/TIM16/TIM17) RM0316 Figure 266. Update rate examples depending on mode and TIMx_RCR register settings 23.4.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin •...
Page 695: Figure 267. Control Circuit In Normal Mode, Internal Clock Divided By 1
RM0316 General-purpose timers (TIM15/TIM16/TIM17) only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 267 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.
Page 696: Capture/Compare Channels
General-purpose timers (TIM15/TIM16/TIM17) RM0316 For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 697: Figure 270. Capture/Compare Channel (Example: Channel 1 Input Stage)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) Figure 270. Capture/compare channel (example: channel 1 input stage) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 271. Capture/compare channel 1 main circuit DocID022558 Rev 8 697/1141...
Page 698: Figure 272. Output Stage Of Capture/Compare Channel (Channel 1)
General-purpose timers (TIM15/TIM16/TIM17) RM0316 Figure 272. Output stage of capture/compare channel (channel 1) Figure 273. Output stage of capture/compare channel (channel 2 for TIM15) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 699: Input Capture Mode
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.4.6 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 700: Pwm Input Mode (Only For Tim15)
General-purpose timers (TIM15/TIM16/TIM17) RM0316 23.4.7 PWM input mode (only for TIM15) This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 701: Forced Output Mode
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.4.8 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register.
Page 702: Pwm Mode
General-purpose timers (TIM15/TIM16/TIM17) RM0316 Procedure Select the counter clock (internal, external, prescaler). Write the desired data in the TIMx_ARR and TIMx_CCRx registers. Set the CCxIE bit if an interrupt request is to be generated. Select the output mode. For example: –...
Page 703: Combined Pwm Mode (Tim15 Only)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register.
Page 704: Figure 277. Combined Pwm Mode On Channel 1 And 2
General-purpose timers (TIM15/TIM16/TIM17) RM0316 by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or AND logical combination of two reference PWMs: • OC1REFC (or OC2REFC) is controlled by the TIMx_CCR1 and TIMx_CCR2 registers Combined PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1100’...
Page 705: Complementary Outputs And Dead-Time Insertion
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.4.12 Complementary outputs and dead-time insertion The TIM15/TIM16/TIM17 general-purpose timers can output one complementary signal and manage the switching-off and switching-on of the outputs. This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of level- shifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN)
Page 706: Figure 279. Dead-Time Waveforms With Delay Greater Than The Negative Pulse
General-purpose timers (TIM15/TIM16/TIM17) RM0316 Figure 279. Dead-time waveforms with delay greater than the negative pulse. Figure 280. Dead-time waveforms with delay greater than the positive pulse. The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register.
Page 707: Using The Break Function
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.4.13 Using the break function The purpose of the break function is to protect power switches driven by PWM signals generated with the TIM15/TIM16/TIM17 timers. The break input is usually connected to fault outputs of power stages and 3-phase inverters. When activated, the break circuitry shuts down the PWM outputs and forces them to a predefined safe state.
Page 708 General-purpose timers (TIM15/TIM16/TIM17) RM0316 When a break occurs (selected level on the break input): • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the AFIO controller (selected by the OSSI bit). This feature functions even if the MCU oscillator is off.
Page 709: Figure 281. Output Behavior In Response To A Break
RM0316 General-purpose timers (TIM15/TIM16/TIM17) Figure 281. Output behavior in response to a break DocID022558 Rev 8 709/1141...
Page 710: One-Pulse Mode
General-purpose timers (TIM15/TIM16/TIM17) RM0316 23.4.14 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 711: Uif Bit Remapping
RM0316 General-purpose timers (TIM15/TIM16/TIM17) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 712: Timer Input Xor Function (Tim15 Only)
General-purpose timers (TIM15/TIM16/TIM17) RM0316 23.4.16 Timer input XOR function (TIM15 only) The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the two input pins TIMx_CH1 and TIMx_CH2. The XOR output can be used with all the timer input functions such as trigger or input capture.
Page 713: External Trigger Synchronization (Tim15 Only)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.4.17 External trigger synchronization (TIM15 only) The TIM timers are linked together internally for timer synchronization or chaining. The TIM15 timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Page 714: Figure 285. Control Circuit In Gated Mode
General-purpose timers (TIM15/TIM16/TIM17) RM0316 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 715: Slave Mode: Combined Reset + Trigger Mode (Tim15 Only)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000).
Page 716 General-purpose timers (TIM15/TIM16/TIM17) RM0316 The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers (either in half-words or in bytes). The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA transfers (when read/write access are done through the TIMx_DMAR address).
Page 717: Timer Synchronization (Tim15)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.4.20 Timer synchronization (TIM15) The TIMx timers are linked together internally for timer synchronization or chaining. Refer to Section 21.3.19: Timer synchronization for details. Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
Page 718: Tim15 Registers
General-purpose timers (TIM15/TIM16/TIM17) RM0316 23.5 TIM15 registers Refer to Section 2.1 for a list of abbreviations used in register descriptions. 23.5.1 TIM15 control register 1 (TIM15_CR1) Address offset: 0x00 Reset value: 0x0000 UIF RE- Res. Res. Res. Res. Res. CKD[1:0] ARPE Res.
Page 719: Tim15 Control Register 2 (Tim15_Cr2)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt if enabled. These events can be: –...
Page 720 General-purpose timers (TIM15/TIM16/TIM17) RM0316 Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS[1:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 721: Tim15 Slave Mode Control Register (Tim15_Smcr)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.5.3 TIM15 slave mode control register (TIM15_SMCR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMS[3] Res. Res. Res. Res. Res. Res. Res.
Page 722: Tim15 Dma/Interrupt Enable Register (Tim15_Dier)
General-purpose timers (TIM15/TIM16/TIM17) RM0316 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 723: Tim15 Status Register (Tim15_Sr)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled...
Page 724 General-purpose timers (TIM15/TIM16/TIM17) RM0316 Bit 8 Reserved, must be kept at reset value. Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred 1: An active level has been detected on the break input Bit 6 TIF: Trigger interrupt flag...
Page 725: Tim15 Event Generation Register (Tim15_Egr)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.5.6 TIM15 event generation register (TIM15_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. COMG Res. Res. CC2G CC1G Bits 15:8 Reserved, must be kept at reset value. Bit 7 BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 726: Tim15 Capture/Compare Mode Register 1 (Tim15_Ccmr1)
General-purpose timers (TIM15/TIM16/TIM17) RM0316 23.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) Address offset: 0x18 Reset value: 0x0000 0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 727 RM0316 General-purpose timers (TIM15/TIM16/TIM17) Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 728 General-purpose timers (TIM15/TIM16/TIM17) RM0316 Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 729: Tim15 Capture/Compare Enable Register (Tim15_Ccer)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 730 General-purpose timers (TIM15/TIM16/TIM17) RM0316 Bit 5 CC2P: Capture/Compare 2 output polarity Refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable Refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high 1: OC1N active low CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1.
Page 731: Table 130. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
RM0316 General-purpose timers (TIM15/TIM16/TIM17) Bit 0 CC1E: Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits.
Page 732: Tim15 Counter (Tim15_Cnt)
General-purpose timers (TIM15/TIM16/TIM17) RM0316 23.5.9 TIM15 counter (TIM15_CNT) Address offset: 0x24 Reset value: 0x0000 0000 CNT[15:0] Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit in the TIMx_ISR register. Bits 30:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value 23.5.10 TIM15 prescaler (TIM15_PSC)
Page 733: Tim15 Repetition Counter Register (Tim15_Rcr)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.5.12 TIM15 repetition counter register (TIM15_RCR) Address offset: 0x30 Reset value: 0x0000 REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 734: Tim15 Capture/Compare Register 2 (Tim15_Ccr2)
General-purpose timers (TIM15/TIM16/TIM17) RM0316 23.5.14 TIM15 capture/compare register 2 (TIM15_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 735 RM0316 General-purpose timers (TIM15/TIM16/TIM17) Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: 1: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 736: Tim15 Dma Control Register (Tim15_Dcr)
General-purpose timers (TIM15/TIM16/TIM17) RM0316 Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>...
Page 737: Tim15 Register Map
RM0316 General-purpose timers (TIM15/TIM16/TIM17) Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
Page 738 General-purpose timers (TIM15/TIM16/TIM17) RM0316 Table 131. TIM15 register map and reset values (continued) Offset Register TIM15_CCER 0x20 Reset value TIM15_CNT CNT[15:0] 0x24 Reset value TIM15_PSC PSC[15:0] 0x28 Reset value TIM15_ARR ARR[15:0] 0x2C Reset value TIM15_RCR REP[7:0] 0x30 Reset value TIM15_CCR1 CCR1[15:0] 0x34 Reset value...
Page 739: Tim16/Tim17 Registers
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.6 TIM16/TIM17 registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. 23.6.1 TIM16/TIM17 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 REM- CKD[1:0] ARPE UDIS Bits 15:12 Reserved, must be kept at reset value. Bit 11 UIFREMAP: UIF status bit remapping 0: No remapping.
Page 740: Tim16/Tim17 Control Register 2 (Timx_Cr2)
General-purpose timers (TIM15/TIM16/TIM17) RM0316 Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow –...
Page 741: Tim16/Tim17 Dma/Interrupt Enable Register (Timx_Dier)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output.
Page 742: Tim16/Tim17 Status Register (Timx_Sr)
General-purpose timers (TIM15/TIM16/TIM17) RM0316 23.6.4 TIM16/TIM17 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC1OF COMIF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:10 Reserved, must be kept at reset value. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode.
Page 743: Tim16/Tim17 Event Generation Register (Timx_Egr)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
Page 744: Tim16/Tim17 Capture/Compare Mode Register 1 (Timx_Ccmr1)
General-purpose timers (TIM15/TIM16/TIM17) RM0316 Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).
Page 745 RM0316 General-purpose timers (TIM15/TIM16/TIM17) Bits 6:4 OC1M[2:0]: Output Compare 1 mode (bits 2 to 0) These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 746: Input Capture Mode
General-purpose timers (TIM15/TIM16/TIM17) RM0316 Input capture mode Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1.
Page 747 RM0316 General-purpose timers (TIM15/TIM16/TIM17) Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high 1: OC1N active low CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P.
Page 748: Tim16/Tim17 Counter (Timx_Cnt)
General-purpose timers (TIM15/TIM16/TIM17) RM0316 Table 132. Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) Control bits Output states MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state Output Disabled (not driven by the timer: Hi-Z) OCx=0 OCxN=0, OCxN_EN=0 Output Disabled (not driven...
Page 749: Tim16/Tim17 Prescaler (Timx_Psc)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. Bits 30:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value 23.6.9 TIM16/TIM17 prescaler (TIMx_PSC)
Page 750: Tim16/Tim17 Repetition Counter Register (Timx_Rcr)
General-purpose timers (TIM15/TIM16/TIM17) RM0316 23.6.11 TIM16/TIM17 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 751: Tim16/Tim17 Break And Dead-Time Register (Timx_Bdtr)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.6.13 TIM16/TIM17 break and dead-time register (TIMx_BDTR) Address offset: 0x44 Reset value: 0x0000 0000 OSSR OSSI LOCK[1:0] DTG[7:0] Note: As the AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register.
Page 752 General-purpose timers (TIM15/TIM16/TIM17) RM0316 Bit 11 OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer.
Page 753: Tim16/Tim17 Dma Control Register (Timx_Dcr)
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.6.14 TIM16/TIM17 DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 DBL[4:0] DBA[4:0] Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e.
Page 754: Tim16 Option Register (Tim16_Or)
General-purpose timers (TIM15/TIM16/TIM17) RM0316 23.6.16 TIM16 option register (TIM16_OR) Address offset: 0x50 Reset value: 0x0000 0000 TI1RMP Bits 31:2 Reserved, must be kept at reset value. Bits1:0 TI1_RMP: Timer 16 input 1 connection. This bit is set and cleared by software. 00: TIM16 TI1 is connected to GPIO 01: TIM16 TI1 is connected to RTC_clock 10: TIM16 TI1 is connected to HSE/32...
Page 755: Tim16/Tim17 Register Map
RM0316 General-purpose timers (TIM15/TIM16/TIM17) 23.6.17 TIM16/TIM17 register map TIM16/TIM17 registers are mapped as 16-bit addressable registers as described in the table below: Table 133. TIM16/TIM17 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reset value TIMx_CR2 0x04 Reset value TIMx_DIER 0x0C Reset value...
Page 756 General-purpose timers (TIM15/TIM16/TIM17) RM0316 Table 133. TIM16/TIM17 register map and reset values (continued) Offset Register TIMx_RCR REP[7:0] 0x30 Reset value TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_BDTR DT[7:0] 0x44 [1:0] Reset value TIMx_DCR DBL[4:0] DBA[4:0] 0x48 Reset value TIMx_DMAR DMAB[15:0] 0x4C Reset value TI1_ TIM16_OR...
Page 757: Infrared Interface (Irtim)
RM0316 Infrared interface (IRTIM) Infrared interface (IRTIM) An infrared interface (IRTIM) for remote control is available on the device. It can be used with an infrared LED to perform remote control functions. It uses internal connections with TIM16 as shown in Figure 287.
Page 758: Independent Watchdog (Iwdg)
Independent watchdog (IWDG) RM0316 Independent watchdog (IWDG) 25.1 Introduction The devices feature an embedded watchdog peripheral that offers a combination of high safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral detects and solves malfunctions due to software failure, and triggers system reset when the counter reaches a given timeout value.
Page 759: Window Option
RM0316 Independent watchdog (IWDG) When the independent watchdog is started by writing the value 0x0000 CCCC in the Key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, the IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented.
Page 760: Hardware Watchdog
Independent watchdog (IWDG) RM0316 25.3.3 Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the Key register is written by the software before the counter reaches end of count or if the downcounter is reloaded inside the window.
Page 761: Iwdg Registers
RM0316 Independent watchdog (IWDG) 25.4 IWDG registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 25.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) Res.
Page 762: Prescaler Register (Iwdg_Pr)
Independent watchdog (IWDG) RM0316 25.4.2 Prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 763: Reload Register (Iwdg_Rlr)
RM0316 Independent watchdog (IWDG) 25.4.3 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RL[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 764: Status Register (Iwdg_Sr)
Independent watchdog (IWDG) RM0316 25.4.4 Status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 765: Window Register (Iwdg_Winr)
RM0316 Independent watchdog (IWDG) 25.4.5 Window register (IWDG_WINR) Address offset: 0x10 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WIN[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 766: Iwdg Register Map
Independent watchdog (IWDG) RM0316 25.4.6 IWDG register map The following table gives the IWDG register map and reset values. Table 134. IWDG register map and reset values Offset Register IWDG_KR KEY[15:0] 0x00 Reset value IWDG_PR PR[2:0] 0x04 Reset value IWDG_RLR RL[11:0] 0x08 Reset value...
Page 767: System Window Watchdog (Wwdg)
RM0316 System window watchdog (WWDG) System window watchdog (WWDG) 26.1 Introduction The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared.
Page 768: Enabling The Watchdog
System window watchdog (WWDG) RM0316 Figure 289. Watchdog block diagram 26.3.1 Enabling the watchdog The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. 26.3.2 Controlling the downcounter This downcounter is free-running, counting down even if the watchdog is disabled.
Page 769: How To Program The Watchdog Timeout
RM0316 System window watchdog (WWDG) The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register. Note: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task, the WWDG reset will eventually be generated.
Page 770: Debug Mode
System window watchdog (WWDG) RM0316 Refer to the datasheet for the minimum and maximum values of the t WWDG 26.3.5 Debug mode ® When the microcontroller enters debug mode (Cortex-M4 F core halted), the WWDG counter either continues to work normally or stops, depending on DBG_WWDG_STOP configuration bit in DBG module.
Page 771: Configuration Register (Wwdg_Cfr)
RM0316 System window watchdog (WWDG) 26.4.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WDGTB[1:0] W[6:0] Bits 31:10 Reserved, must be kept at reset value.
Page 772: Wwdg Register Map
System window watchdog (WWDG) RM0316 26.4.4 WWDG register map The following table gives the WWDG register map and reset values. Table 135. WWDG register map and reset values Offset Register WWDG_ T[6:0] 0x00 Reset value WWDG_ W[6:0] 0x04 Reset value WWDG_ 0x08 Reset value...
Page 773: Real-Time Clock (Rtc)
RM0316 Real-time clock (RTC) Real-time clock (RTC) 27.1 Introduction The RTC provides an automatic wakeup to manage all low-power modes. The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time- of-day clock/calendar with programmable alarm interrupts. The RTC includes also a periodic programmable wakeup flag with interrupt capability.
Page 774: Rtc Main Features
Real-time clock (RTC) RM0316 27.2 RTC main features The RTC unit main features are the following (see Figure 291: RTC block diagram): • Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year. •...
Page 775: Rtc Functional Description
RM0316 Real-time clock (RTC) 27.3 RTC functional description 27.3.1 RTC block diagram Figure 291. RTC block diagram 1. RTC_TAMP3 is not available on the STM32F303x6/8 and STM32F328 devices. DocID022558 Rev 8 775/1141...
Page 776: Gpios Controlled By The Rtc
Real-time clock (RTC) RM0316 The RTC includes: • Two alarms • Three tamper events from I/Os – Tamper detection erases the backup registers. • One timestamp event from I/O • Tamper event detection can generate a timestamp event • 16 x 32-bit backup registers on the STM32F303xB/C and 5 x 32 bit backup registers on the STM32F303x6/8 –...
Page 777: Table 136. Rtc Pin Pc13 Configuration
RM0316 Real-time clock (RTC) Table 136. RTC pin PC13 configuration RTC_ALARM RTC_CALIB RTC_TAMP1 RTC_TS PC13MODE PC13VALUE configuration output output input input and function enabled enabled enabled enabled RTC_ALARM Don’t care Don’t care Don’t care Don’t care output OD RTC_ALARM Don’t care Don’t care Don’t care Don’t care...
Page 778: Clock And Prescalers
Real-time clock (RTC) RM0316 27.3.3 Clock and prescalers The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to Section 9: Reset and clock control (RCC).
Page 779: Programmable Alarms
RM0316 Real-time clock (RTC) register (RTC_ISR)). The copy is not performed in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up to 2 RTCCLK periods. When the application reads the calendar registers, it accesses the content of the shadow registers.
Page 780: Rtc Initialization And Configuration
Real-time clock (RTC) RM0316 the RTC_ISR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value). The WUTF flag must then be cleared by software. When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR2 register, it can exit the device from low-power modes.
Page 781: Reading The Calendar
RM0316 Real-time clock (RTC) When the initialization sequence is complete, the calendar starts counting. Note: After a system reset, the application can read the INITS flag in the RTC_ISR register to check if the calendar has been initialized or not. If this flag equals 0, the calendar has not been initialized since the year field is set at its Backup domain reset default value (0x00).
Page 782: Resetting The Rtc
Real-time clock (RTC) RM0316 read access must be done. In any case the APB1 clock frequency must never be lower than the RTC clock frequency. The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the RTC_SSR, RTC_TR and RTC_DR shadow registers.
Page 783: Rtc Synchronization
RM0316 Real-time clock (RTC) (RTC_CALR), the RTC shift register (RTC_SHIFTR), the RTC timestamp registers (RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper and alternate function configuration register (RTC_TAFCR), the RTC backup registers (RTC_BKPxR), the wakeup timer register (RTC_WUTR), the Alarm A and Alarm B registers (RTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR).
Page 784: Rtc Smooth Digital Calibration
Real-time clock (RTC) RM0316 Each 1 Hz clock edge is compared to the nearest RTC_REFIN clock edge (if one is found within a given time window). In most cases, the two clock edges are properly aligned. When the 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts the 1 Hz clock a bit so that future 1 Hz clock edges are aligned.
Page 785 RM0316 Real-time clock (RTC) causes four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000); and so on up to CALM[8]=1 which causes 256 clocks to be masked (cal_cnt = 0xXX800). While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine resolution, the bit CALP can be used to increase the frequency by 488.5 ppm.
Page 786: Time-Stamp Function
Real-time clock (RTC) RM0316 Using this mode and measuring the accuracy of the 1 Hz output over exactly 32 seconds guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 seconds, due to the limitation of the calibration resolution). •...
Page 787: Tamper Detection
RM0316 Real-time clock (RTC) Optionally, a tamper event can cause a time-stamp to be recorded. See the description of the TAMPTS control bit in Section 27.6.16: RTC tamper and alternate function configuration register (RTC_TAFCR). 27.3.14 Tamper detection The RTC_TAMPx input events can be configured either for edge detection, or for level detection with filtering.
Page 788: Calibration Clock Output
Real-time clock (RTC) RM0316 Caution: To avoid losing tamper detection events, the signal used for edge detection is logically ANDed with the corresponding TAMPxE bit in order to detect a tamper detection event in case it occurs before the RTC_TAMPx pin is enabled. •...
Page 789: Alarm Output
RM0316 Real-time clock (RTC) Note: When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is automatically configured in output alternate function. When COSEL bit is cleared, the RTC_CALIB output is the output of the 6th stage of the asynchronous prescaler.
Page 790: Rtc Registers
Real-time clock (RTC) RM0316 To enable the RTC Tamper interrupt, the following sequence is required: Configure and enable the EXTI line corresponding to the RTC Tamper event in interrupt mode and select the rising edge sensitivity. Configure and Enable the RTC_TAMP_STAMP IRQ channel in the NVIC. Configure the RTC to detect the RTC tamper event.
Page 791: Rtc Date Register (Rtc_Dr)
Bits 14:12 MNT[2:0]: Minute tens in BCD format Bits 11:8 MNU[3:0]: Minute units in BCD format Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format 27.6.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register.
Page 792 Real-time clock (RTC) RM0316 Bits 31:24 Reserved, must be kept at reset value Bits 23:20 YT[3:0]: Year tens in BCD format Bits 19:16 YU[3:0]: Year units in BCD format Bits 15:13 WDU[2:0]: Week day units 000: forbidden 001: Monday 111: Sunday Bit 12 MT: Month tens in BCD format Bits 11:8 MU: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value.
Page 793: Rtc Control Register (Rtc_Cr)
RM0316 Real-time clock (RTC) 27.6.3 RTC control register (RTC_CR) Address offset: 0x08 Backup domain reset value: 0x0000 0000 System reset: not affected Res. Res. Res. Res. Res. Res. Res. Res. OSEL[1:0] COSEL SUB1H ADD1H BYPS TSIE WUTIE ALRBIE ALRAIE WUTE ALRBE ALRAE Res.
Page 794 Real-time clock (RTC) RM0316 Bit 16 ADD1H: Add 1 hour (summer time change) When this bit is set, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode.
Page 795 RM0316 Real-time clock (RTC) Bit 4 REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz) 0: RTC_REFIN detection disabled 1: RTC_REFIN detection enabled Note: PREDIV_S must be 0x00FF. Bit 3 TSEDGE: Time-stamp event active edge 0: RTC_TS input rising edge generates a time-stamp event 1: RTC_TS input falling edge generates a time-stamp event TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
Page 796: Rtc Initialization And Status Register (Rtc_Isr)
Real-time clock (RTC) RM0316 27.6.4 RTC initialization and status register (RTC_ISR) This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page 780. Address offset: 0x0C Backup domain reset value: 0x0000 0007 System reset: not affected except INIT, INITF, and RSF bits which are cleared to ‘0’...
Page 797 RM0316 Real-time clock (RTC) Bit 9 ALRBF: Alarm B flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR). This flag is cleared by software by writing 0. Bit 8 ALRAF: Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR).
Page 798 Real-time clock (RTC) RM0316 Bit 2 WUTWF: Wakeup timer write flag This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set.
Page 799: Rtc Prescaler Register (Rtc_Prer)
RM0316 Real-time clock (RTC) 27.6.5 RTC prescaler register (RTC_PRER) This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page 780. This register is write protected. The write access procedure is described in RTC register write protection on page 780.
Page 800: Rtc Wakeup Timer Register (Rtc_Wutr)
Real-time clock (RTC) RM0316 27.6.6 RTC wakeup timer register (RTC_WUTR) This register can be written only when WUTWF is set to 1 in RTC_ISR. This register is write protected. The write access procedure is described in RTC register write protection on page 780.
Page 801: Rtc Alarm A Register (Rtc_Alrmar)
Bit 7 MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don’t care in Alarm A comparison Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. DocID022558 Rev 8...
Page 802: Rtc Alarm B Register (Rtc_Alrmbr)
Bit 7 MSK1: Alarm B seconds mask 0: Alarm B set if the seconds match 1: Seconds don’t care in Alarm B comparison Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format 802/1141...
Page 803: Rtc Write Protection Register (Rtc_Wpr)
RM0316 Real-time clock (RTC) 27.6.9 RTC write protection register (RTC_WPR) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 804: Rtc Shift Control Register (Rtc_Shiftr)
Real-time clock (RTC) RM0316 27.6.11 RTC shift control register (RTC_SHIFTR) This register is write protected. The write access procedure is described in RTC register write protection on page 780. Address offset: 0x2C Backup domain reset value: 0x0000 0000 System reset: not affected ADD1S Res.
Page 805: Rtc Timestamp Time Register (Rtc_Tstr)
Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 Reserved, must be kept at reset value Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. DocID022558 Rev 8...
Page 806: Rtc Timestamp Date Register (Rtc_Tsdr)
Real-time clock (RTC) RM0316 27.6.13 RTC timestamp date register (RTC_TSDR) The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset. Address offset: 0x34 Backup domain reset value: 0x0000 0000 System reset: not affected Res.
Page 807: Rtc Time-Stamp Sub Second Register (Rtc_Tsssr)
RM0316 Real-time clock (RTC) 27.6.14 RTC time-stamp sub second register (RTC_TSSSR) The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset. Address offset: 0x38 Backup domain reset value: 0x0000 0000 System reset: not affected Res.
Page 808: Rtc Calibration Register (Rtc_Calr)
Real-time clock (RTC) RM0316 27.6.15 RTC calibration register (RTC_CALR) This register is write protected. The write access procedure is described in RTC register write protection on page 780. Address offset: 0x3C Backup domain reset value: 0x0000 0000 System reset: not affected Res.
Page 809: Rtc Tamper And Alternate Function Configuration Register
RM0316 Real-time clock (RTC) 27.6.16 RTC tamper and alternate function configuration register (RTC_TAFCR) Address offset: 0x40 Backup domain reset value: 0x0000 0000 System reset: not affected PC15 PC15 PC14 PC14 PC13 PC13 Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 810 Real-time clock (RTC) RM0316 Bits 14:13 TAMPPRCH[1:0]: RTC_TAMPx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs. 0x0: 1 RTCCLK cycle 0x1: 2 RTCCLK cycles 0x2: 4 RTCCLK cycles 0x3: 8 RTCCLK cycles Bits 12:11 TAMPFLT[1:0]: RTC_TAMPx filter count...
Page 811 RM0316 Real-time clock (RTC) Bit 3 TAMP2E: RTC_TAMP2 input detection enable 0: RTC_TAMP2 detection disabled 1: RTC_TAMP2 detection enabled Bit 2 TAMPIE: Tamper interrupt enable 0: Tamper interrupt disabled 1: Tamper interrupt enabled. Bit 1 TAMP1TRG: Active level for RTC_TAMP1 input If TAMPFLT != 00 0: RTC_TAMP1 input staying low triggers a tamper detection event.
Page 812: Rtc Alarm A Sub Second Register (Rtc_Alrmassr)
Real-time clock (RTC) RM0316 27.6.17 RTC alarm A sub second register (RTC_ALRMASSR) This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 780 Address offset: 0x44...
Page 813: Rtc Alarm B Sub Second Register (Rtc_Alrmbssr)
RM0316 Real-time clock (RTC) 27.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section : RTC register write protection.
Page 814: Real Time Clock (Rtc)
This register is reset on a tamper detection event, as long as TAMPxF=1. 27.6.20 RTC register map Table 141. RTC register map and reset values Offset Register RTC_TR HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] 0x00 Reset value RTC_DR YT[3:0] YU[3:0] WDU[2:0] MU[3:0]...
Page 815 RM0316 Real-time clock (RTC) Table 141. RTC register map and reset values (continued) Offset Register RTC_ALRMBR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] [1:0] 0x20 Reset value RTC_WPR 0x24 Reset value RTC_SSR SS[15:0] 0x28 Reset value RTC_SHIFTR SUBFS[14:0] 0x2C Reset value...
Page 816: Inter-Integrated Circuit (I2C) Interface
Inter-integrated circuit (I2C) interface RM0316 Inter-integrated circuit (I2C) interface 28.1 Introduction The I C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
Page 817: I2C Implementation
RM0316 Inter-integrated circuit (I2C) interface The following additional features are also available depending on the product implementation (see Section 28.3: I2C implementation): • SMBus specification rev 2.0 compatibility: – Hardware PEC (Packet Error Checking) generation and verification with ACK control –...
Page 818: I2C Block Diagram
Inter-integrated circuit (I2C) interface RM0316 This interface can also be connected to a SMBus with the data pin (SDA) and clock pin (SCL). If SMBus feature is supported: the additional optional SMBus Alert pin (SMBA) is also available. 28.4.1 I2C block diagram The block diagram of the I2C interface is shown in Figure 292.
Page 819: I2C Clock Requirements
RM0316 Inter-integrated circuit (I2C) interface Refer to Section 9: Reset and clock control (RCC) for more details. I2C I/Os support 20 mA output current drive for Fast-mode Plus operation. This is enabled by setting the driving capability control bits for SCL and SDA in Section 12.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1).
Page 820: Figure 293. I2C Bus Protocol
Inter-integrated circuit (I2C) interface RM0316 Figure 293. I C bus protocol Acknowledge can be enabled or disabled by software. The I2C interface addresses can be selected by software. 820/1141 DocID022558 Rev 8...
Page 821: I2C Initialization
RM0316 Inter-integrated circuit (I2C) interface 28.4.4 I2C initialization Enabling and disabling the peripheral The I2C peripheral clock must be configured and enabled in the clock controller (refer to Section 9: Reset and clock control (RCC)). Then the I2C can be enabled by setting the PE bit in the I2C_CR1 register. When the I2C is disabled (PE=0), the I C performs a software reset.
Page 822: Figure 294. Setup And Hold Timings
Inter-integrated circuit (I2C) interface RM0316 I2C timings The timings must be configured in order to guarantee a correct data hold and setup time, used in master and slave modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and SDADEL[3:0] bits in the I2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C configuration window Figure 294.
Page 823: Table 144. I2C-Smbus Specification Data Setup And Hold Times
RM0316 Inter-integrated circuit (I2C) interface • When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is where = SDADEL x t = (PRESC+1) SDADEL PRESC I2CCLK PRESC I2CCLK impacts the hold time SDADEL HD;DAT.
Page 824 Inter-integrated circuit (I2C) interface RM0316 Note: At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL low during at least [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x t , in both transmission I2CCLK and reception modes. In transmission mode, in case the data is not yet written in I2C_TXDR when SDADEL counter is finished, the I2C keeps on stretching SCL low until the next data is written.
Page 825: Software Reset
RM0316 Inter-integrated circuit (I2C) interface Figure 295. I2C initialization flowchart 28.4.5 Software reset A software reset can be performed by clearing the PE bit in the I2C_CR1 register. In that case I2C lines SCL and SDA are released. Internal states machines are reset and communication control bits, as well as status bits come back to their reset value.
Page 826: Data Transfer
Inter-integrated circuit (I2C) interface RM0316 28.4.6 Data transfer The data transfer is managed through transmit and receive data registers and a shift register. Reception The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is received), the shift register is copied into I2C_RXDR register if it is empty (RXNE=0).
Page 827: Figure 297. Data Transmission
RM0316 Inter-integrated circuit (I2C) interface Transmission If the I2C_TXDR register is not empty (TXE=0), its content is copied into the shift register after the 9th SCL pulse (the Acknowledge pulse). Then the shift register content is shifted out on SDA line. If TXE=1, meaning that no data is written yet in I2C_TXDR, SCL line is stretched low until I2C_TXDR is written.
Page 828: I2C Slave Mode
Inter-integrated circuit (I2C) interface RM0316 When RELOAD=0 in master mode, the counter can be used in 2 modes: • Automatic end mode (AUTOEND = ‘1’ in the I2C_CR2 register). In this mode, the master automatically sends a STOP condition once the number of bytes programmed in the NBYTES[7:0] bit field has been transferred.
Page 829 RM0316 Inter-integrated circuit (I2C) interface By default, the slave uses its clock stretching capability, which means that it stretches the SCL signal at low level when needed, in order to perform software actions. If the master does not support clock stretching, the I2C must be configured with NOSTRETCH=1 in the I2C_CR1 register.
Page 830 Inter-integrated circuit (I2C) interface RM0316 Slave Byte Control mode In order to allow byte ACK control in slave reception mode, Slave Byte Control mode must be enabled by setting the SBC bit in the I2C_CR1 register. This is required to be compliant with SMBus standards.
Page 831: Figure 298. Slave Initialization Flowchart
RM0316 Inter-integrated circuit (I2C) interface Figure 298. Slave initialization flowchart Slave transmitter A transmit interrupt status (TXIS) is generated when the I2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit is set in the I2C_CR1 register. The TXIS bit is cleared when the I2C_TXDR register is written with the next data byte to be transmitted.
Page 832: Figure 299. Transfer Sequence Flowchart For I2C Slave Transmitter, Nostretch=0
Inter-integrated circuit (I2C) interface RM0316 the number of TXIS events during the transfer corresponds to the value programmed in NBYTES. Caution: When NOSTRETCH=1, the SCL clock is not stretched while the ADDR flag is set, so the user cannot flush the I2C_TXDR register content in the ADDR subroutine, in order to program the first data byte.
Page 833: Figure 300. Transfer Sequence Flowchart For I2C Slave Transmitter, Nostretch=1
RM0316 Inter-integrated circuit (I2C) interface Figure 300. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1 DocID022558 Rev 8 833/1141...
Page 834: Figure 301. Transfer Bus Diagrams For I2C Slave Transmitter
Inter-integrated circuit (I2C) interface RM0316 Figure 301. Transfer bus diagrams for I2C slave transmitter 834/1141 DocID022558 Rev 8...
Page 835: Figure 302. Transfer Sequence Flowchart For Slave Receiver With Nostretch=0
RM0316 Inter-integrated circuit (I2C) interface Slave receiver RXNE is set in I2C_ISR when the I2C_RXDR is full, and generates an interrupt if RXIE is set in I2C_CR1. RXNE is cleared when I2C_RXDR is read. When a STOP is received and STOPIE is set in I2C_CR1, STOPF is set in I2C_ISR and an interrupt is generated.
Page 836: Figure 303. Transfer Sequence Flowchart For Slave Receiver With Nostretch=1
Inter-integrated circuit (I2C) interface RM0316 Figure 303. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 Figure 304. Transfer bus diagrams for I2C slave receiver 836/1141 DocID022558 Rev 8...
Page 837: I2C Master Mode
RM0316 Inter-integrated circuit (I2C) interface 28.4.8 I2C master mode I2C master initialization Before enabling the peripheral, the I2C master clock must be configured by setting the SCLH and SCLL bits in the I2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C Configuration window.
Page 838: Figure 305. Master Clock Generation
Inter-integrated circuit (I2C) interface RM0316 Figure 305. Master clock generation Caution: In order to be I C or SMBus compliant, the master clock must respect the timings given below: 838/1141 DocID022558 Rev 8...
Page 839: Table 146. I2C-Smbus Specification Clock Timings
RM0316 Inter-integrated circuit (I2C) interface Table 146. I C-SMBUS specification clock timings Standard- Fast-mode Fast-mode SMBUS mode (Sm) (Fm) Plus (Fm+) Symbol Parameter Unit SCL clock frequency 1000 Hold time (repeated) START 0.26 μs HD:STA condition Set-up time for a repeated 0.26 μs SU:STA...
Page 840: Figure 306. Master Initialization Flowchart
Inter-integrated circuit (I2C) interface RM0316 Note: The START bit is reset by hardware when the slave address has been sent on the bus, whatever the received acknowledge value. The START bit is also reset by hardware if an arbitration loss occurs. In 10-bit addressing mode, when the Slave Address first 7 bits is NACKed by the slave, the master will re-launch automatically the slave address transmission until ACK is received.
Page 841: Figure 308. 10-Bit Address Read Access With Head10R=1
RM0316 Inter-integrated circuit (I2C) interface • If the master addresses a 10-bit address slave, transmits data to this slave and then reads data from the same slave, a master transmission flow must be done first. Then a repeated start is set with the 10 bit slave address configured with HEAD10R=1. In this case the master sends this sequence: ReStart + Slave address 10-bit header Read.
Page 842: Figure 309. Transfer Sequence Flowchart For I2C Master Transmitter For N”255 Bytes
Inter-integrated circuit (I2C) interface RM0316 Figure 309. Transfer sequence flowchart for I2C master transmitter for N”255 bytes 842/1141 DocID022558 Rev 8...
Page 843: Figure 310. Transfer Sequence Flowchart For I2C Master Transmitter For N>255 Bytes
RM0316 Inter-integrated circuit (I2C) interface Figure 310. Transfer sequence flowchart for I2C master transmitter for N>255 bytes DocID022558 Rev 8 843/1141...
Page 844: Figure 311. Transfer Bus Diagrams For I2C Master Transmitter
Inter-integrated circuit (I2C) interface RM0316 Figure 311. Transfer bus diagrams for I2C master transmitter 844/1141 DocID022558 Rev 8...
Page 845 RM0316 Inter-integrated circuit (I2C) interface Master receiver In the case of a read transfer, the RXNE flag is set after each byte reception, after the 8th SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the I2C_CR1 register.
Page 846: Figure 312. Transfer Sequence Flowchart For I2C Master Receiver For N”255 Bytes
Inter-integrated circuit (I2C) interface RM0316 Figure 312. Transfer sequence flowchart for I2C master receiver for N”255 bytes 846/1141 DocID022558 Rev 8...
Page 847: Figure 313. Transfer Sequence Flowchart For I2C Master Receiver For N >255 Bytes
RM0316 Inter-integrated circuit (I2C) interface Figure 313. Transfer sequence flowchart for I2C master receiver for N >255 bytes DocID022558 Rev 8 847/1141...
Page 848: Figure 314. Transfer Bus Diagrams For I2C Master Receiver
Inter-integrated circuit (I2C) interface RM0316 Figure 314. Transfer bus diagrams for I2C master receiver 848/1141 DocID022558 Rev 8...
Page 849: I2C_Timingr Register Configuration Examples
RM0316 Inter-integrated circuit (I2C) interface 28.4.9 I2C_TIMINGR register configuration examples The tables below provide examples of how to program the I2C_TIMINGR to obtain timings compliant with the I C specification. In order to get more accurate configuration values, please refer to the application note: I C timing configuration tool (AN4235) and the associated software STSW-STM32126.
Page 850: Smbus Specific Features
Inter-integrated circuit (I2C) interface RM0316 1. The SCL period t is greater than t due to the SCL internal detection delay. Values provided for t are only SCLL SCLH examples. 2. t minimum value is 4x t = 83.3 ns. Example with t = 1000 ns SYNC1 + SYNC2...
Page 851 RM0316 Inter-integrated circuit (I2C) interface For more details of the SMBus Address Resolution Protocol, refer to SMBus specification version 2.0 (http://smbus.org). Received Command and Data acknowledge control A SMBus receiver must be able to NACK each received command or data. In order to allow the ACK control in slave mode, the Slave Byte Control mode must be enabled by setting SBC bit in I2C_CR1 register.
Page 852: Inter-Integrated Circuit (I2C) Interface
Inter-integrated circuit (I2C) interface RM0316 Timeouts This peripheral embeds hardware timers in order to be compliant with the 3 timeouts defined in SMBus specification version 2.0. Table 149. SMBus timeout specifications Limits Symbol Parameter Unit Detect clock low timeout TIMEOUT Cumulative clock low extend time (slave device) LOW:SEXT Cumulative clock low extend time (master device)
Page 853: Smbus Initialization
RM0316 Inter-integrated circuit (I2C) interface Bus idle detection A master can assume that the bus is free if it detects that the clock and data signals have been high for t greater than t . (refer to Table 146: I2C-SMBUS specification clock IDLE HIGH timings)
Page 854: Table 150. Smbus With Pec Configuration
Inter-integrated circuit (I2C) interface RM0316 Table 150. SMBUS with PEC configuration Mode SBC bit RELOAD bit AUTOEND bit PECBYTE bit Master Tx/Rx NBYTES + PEC+ STOP Master Tx/Rx NBYTES + PEC + ReSTART Slave Tx/Rx with PEC Timeout detection The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the I2C_TIMEOUTR register.
Page 855: Smbus: I2C_Timeoutr Register Configuration Examples
RM0316 Inter-integrated circuit (I2C) interface Caution: Changing the TIMEOUTA and TIDLE configuration is not allowed when the TIMEOUTEN is set. SMBus: 28.4.12 I2C_TIMEOUTR register configuration examples This section is relevant only when SMBus feature is supported. Please refer to Section 28.3: implementation.
Page 856: Smbus Slave Mode
Inter-integrated circuit (I2C) interface RM0316 28.4.13 SMBus slave mode This section is relevant only when SMBus feature is supported. Please refer to Section 28.3: implementation. In addition to 2C slave transfer management (refer to Section 28.4.7: I2C slave mode) some additional software flowcharts are provided to support SMBus.
Page 857: Figure 317. Transfer Bus Diagrams For Smbus Slave Transmitter (Sbc=1)
RM0316 Inter-integrated circuit (I2C) interface Figure 317. Transfer bus diagrams for SMBus slave transmitter (SBC=1) SMBus Slave receiver When the I2C is used in SMBus mode, SBC must be programmed to ‘1’ in order to allow the PEC checking at the end of the programmed number of data bytes. In order to allow the ACK control of each byte, the reload mode must be selected (RELOAD=1).
Page 858: Figure 318. Transfer Sequence Flowchart For Smbus Slave Receiver N Bytes + Pec
Inter-integrated circuit (I2C) interface RM0316 Figure 318. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC 858/1141 DocID022558 Rev 8...
Page 859: Figure 319. Bus Transfer Diagrams For Smbus Slave Receiver (Sbc=1)
RM0316 Inter-integrated circuit (I2C) interface Figure 319. Bus transfer diagrams for SMBus slave receiver (SBC=1) This section is relevant only when SMBus feature is supported. Please refer to Section 28.3: implementation. In addition to I2C master transfer management (refer to Section 28.4.8: I2C master mode) some additional software flowcharts are provided to support SMBus.
Page 860: Figure 320. Bus Transfer Diagrams For Smbus Master Transmitter
Inter-integrated circuit (I2C) interface RM0316 When the SMBus master wants to send a RESTART condition after the PEC, software mode must be selected (AUTOEND=0). In this case, once NBYTES-1 have been transmitted, the I2C_PECR register content is transmitted and the TC flag is set after the PEC transmission, stretching the SCL line low.
Page 861 RM0316 Inter-integrated circuit (I2C) interface SMBus Master receiver When the SMBus master wants to receive the PEC followed by a STOP at the end of the transfer, automatic end mode can be selected (AUTOEND=1). The PECBYTE bit must be set and the slave address must be programmed, before setting the START bit. In this case, after NBYTES-1 data have been received, the next received byte is automatically checked versus the I2C_PECR register content.
Page 862: Figure 321. Bus Transfer Diagrams For Smbus Master Receiver
Inter-integrated circuit (I2C) interface RM0316 Figure 321. Bus transfer diagrams for SMBus master receiver 862/1141 DocID022558 Rev 8...
Page 863: Wakeup From Stop Mode On Address Match
RM0316 Inter-integrated circuit (I2C) interface 28.4.14 Wakeup from Stop mode on address match This section is relevant only when Wakeup from Stop mode feature is supported. Please refer to Section 28.3: I2C implementation. The I2C is able to wakeup the MCU from Stop mode (APB clock is off), when it is addressed.
Page 864 Inter-integrated circuit (I2C) interface RM0316 Arbitration lost (ARLO) An arbitration loss is detected when a high level is sent on the SDA line, but a low level is sampled on the SCL rising edge. • In master mode, arbitration loss is detected during the address phase, data phase and data acknowledge phase.
Page 865: Dma Requests
RM0316 Inter-integrated circuit (I2C) interface When a timeout violation is detected in master mode, a STOP condition is automatically sent. When a timeout violation is detected in slave mode, SDA and SCL lines are automatically released. When a timeout error is detected, the TIMEOUT flag is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
Page 866: Debug Mode
Inter-integrated circuit (I2C) interface RM0316 DMA must be initialized before setting the START bit. The end of transfer is managed with the NBYTES counter. • In slave mode with NOSTRETCH=0, when all data are transferred using DMA, the DMA must be initialized before the address match event, or in the ADDR interrupt subroutine, before clearing the ADDR flag.
Page 867: Figure 322. I2C Interrupt Mapping Diagram
RM0316 Inter-integrated circuit (I2C) interface Table 155. I2C Interrupt requests (continued) Event flag/Interrupt Interrupt enable Interrupt event Event flag clearing method control bit Bus error BERR Write BERRCF=1 Arbitration loss ARLO Write ARLOCF=1 Overrun/Underrun Write OVRCF=1 ERRIE PEC error PECERR Write PECERRCF=1 Timeout/t error...
Page 868: I2C Registers
Inter-integrated circuit (I2C) interface RM0316 28.7 I2C registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers are accessed by words (32-bit). 28.7.1 Control register 1 (I2C_CR1) Address offset: 0x00 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing.
Page 869 RM0316 Inter-integrated circuit (I2C) interface Bit 20 SMBHEN: SMBus Host address enable 0: Host address disabled. Address 0b0001000x is NACKed. 1: Host address enabled. Address 0b0001000x is ACKed. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 28.3: I2C implementation.
Page 870 Inter-integrated circuit (I2C) interface RM0316 Bit 7 ERRIE: Error interrupts enable 0: Error detection interrupts disabled 1: Error detection interrupts enabled Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT) Bit 6 TCIE: Transfer Complete interrupt enable...
Page 871: Control Register 2 (I2C_Cr2)
RM0316 Inter-integrated circuit (I2C) interface 28.7.2 Control register 2 (I2C_CR2) Address offset: 0x04 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 872 Inter-integrated circuit (I2C) interface RM0316 Bit 15 NACK: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. 0: an ACK is sent after current received byte.
Page 873 RM0316 Inter-integrated circuit (I2C) interface Bits 9:8 SADD[9:8]: Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are don’t care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed.
Page 874: Own Address 1 Register (I2C_Oar1)
Inter-integrated circuit (I2C) interface RM0316 28.7.3 Own address 1 register (I2C_OAR1) Address offset: 0x08 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 875: Own Address 2 Register (I2C_Oar2)
RM0316 Inter-integrated circuit (I2C) interface 28.7.4 Own address 2 register (I2C_OAR2) Address offset: 0x0C Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 876: Timing Register (I2C_Timingr)
Inter-integrated circuit (I2C) interface RM0316 28.7.5 Timing register (I2C_TIMINGR) Address offset: 0x10 Reset value: 0x0000 0000 Access: No wait states PRESC[3:0] Res. Res. Res. Res. SCLDEL[3:0] SDADEL[3:0] SCLH[7:0] SCLL[7:0] Bits 31:28 PRESC[3:0]: Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period t used for data PRESC setup and hold counters (refer to...
Page 877: Timeout Register (I2C_Timeoutr)
RM0316 Inter-integrated circuit (I2C) interface 28.7.6 Timeout register (I2C_TIMEOUTR) Address offset: 0x14 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 878: Interrupt And Status Register (I2C_Isr)
Inter-integrated circuit (I2C) interface RM0316 28.7.7 Interrupt and status register (I2C_ISR) Address offset: 0x18 Reset value: 0x0000 0001 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. ADDCODE[6:0] TIME BUSY Res. ALERT ARLO BERR STOPF NACKF ADDR RXNE TXIS Bits 31:24 Reserved, must be kept at reset value.
Page 879 RM0316 Inter-integrated circuit (I2C) interface Bit 11 PECERR: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit.
Page 880: Interrupt Clear Register (I2C_Icr)
Inter-integrated circuit (I2C) interface RM0316 Bit 2 RXNE: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0.
Page 881: Pec Register (I2C_Pecr)
RM0316 Inter-integrated circuit (I2C) interface Bit 9 ARLOCF: Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. Bit 8 BERRCF: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. Bits 7:6 Reserved, must be kept at reset value.
Page 882: Receive Data Register (I2C_Rxdr)
Inter-integrated circuit (I2C) interface RM0316 28.7.10 Receive data register (I2C_RXDR) Address offset: 0x24 Reset value: 0x0000 0000 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 883: I2C Register Map
RM0316 Inter-integrated circuit (I2C) interface 28.7.12 I2C register map The table below provides the I2C register map and reset values. Table 156. I2C register map and reset values Offset Register I2C_CR1 DNF[3:0] Reset value I2C_CR2 NBYTES[7:0] SADD[9:0] Reset value I2C_OAR1 OA1[9:0] Reset value OA2MS...
Page 884 Inter-integrated circuit (I2C) interface RM0316 Table 156. I2C register map and reset values (continued) Offset Register I2C_TXDR TXDATA[7:0] 0x28 Reset value Refer to Section 3.2.2 on page 51 for the register boundary addresses. 884/1141 DocID022558 Rev 8...
Page 885: Universal Synchronous Asynchronous Receiver Transmitter (Usart)
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Universal synchronous asynchronous receiver transmitter (USART) 29.1 Introduction The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of Full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART offers a very wide range of baud rates using a programmable baud rate generator.
Page 886: Usart Extended Features
Universal synchronous asynchronous receiver transmitter (USART) RM0316 • Communication control/error detection flags • Parity control: – Transmits parity bit – Checks parity of received data byte • Fourteen interrupt sources with flags • Multiprocessor communications The USART enters mute mode if the address does not match. •...
Page 887: Usart Implementation
RM0316 Universal synchronous asynchronous receiver transmitter (USART) 29.4 USART implementation Table 157. STM32F3xx USART features STM32F303xB/C and STM32F303xD/E and STM32F303x6/8 and STM32F358xC STM32F398xE STM32F328x8 USART modes/features USART1/ USART1/ USART2/ USART2/ UART4 UART5 USART2/ UART4 UART5 USART1 USART3 USART3 USART3 Hardware flow control for modem Continuous communication using DMA...
Page 888: Usart Functional Description
Universal synchronous asynchronous receiver transmitter (USART) RM0316 29.5 USART functional description Any USART bidirectional communication requires a minimum of two pins: Receive data In (RX) and Transmit data Out (TX): • RX: Receive data Input. This is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.
Page 889: Figure 323. Usart Block Diagram
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Figure 323. USART block diagram 1. For details on coding USARTDIV in the USART_BRR register, please refer to Section 29.5.4: USART baud rate generation. 2. f can be f PCLK DocID022558 Rev 8 889/1141...
Page 890: Usart Character Description
Universal synchronous asynchronous receiver transmitter (USART) RM0316 29.5.1 USART character description The word length can be selected as being either 7 or 8 or 9 bits by programming the M[1:0] bits in the USART_CR1 register (see Figure 324). • 7-bit character length: M[1:0] = 10 •...
Page 891: Figure 324. Word Length Programming
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Figure 324. Word length programming DocID022558 Rev 8 891/1141...
Page 892: Usart Transmitter
Universal synchronous asynchronous receiver transmitter (USART) RM0316 29.5.2 USART transmitter The transmitter can send data words of either 7, 8 or 9 bits depending on the M bits status. The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the CK pin.
Page 893: Figure 325. Configurable Stop Bits
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Figure 325. Configurable stop bits Character transmission procedure Program the M bits in USART_CR1 to define the word length. Select the desired baud rate using the USART_BRR register. Program the number of stop bits in USART_CR2. Enable the USART by writing the UE bit in USART_CR1 register to 1.
Page 894: Usart Receiver
Universal synchronous asynchronous receiver transmitter (USART) RM0316 When no transmission is taking place, a write instruction to the USART_TDR register places the data in the shift register, the data transmission starts, and the TXE bit is set. If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An interrupt is generated if the TCIE bit is set in the USART_CR1 register.
Page 895: Figure 327. Start Bit Detection When Oversampling By 16 Or 8
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Start bit detection The start bit detection sequence is the same when oversampling by 16 or by 8. In the USART, the start bit is detected when a specific sequence of samples is recognized. This sequence is: 1 1 1 0 X 0 X 0X 0X 0 X 0X 0.
Page 896 Universal synchronous asynchronous receiver transmitter (USART) RM0316 Character reception During an USART reception, data shifts in least significant bit first (default configuration) through the RX pin. In this mode, the USART_RDR register consists of a buffer (RDR) between the internal bus and the receive shift register. Character reception procedure Program the M bits in USART_CR1 to define the word length.
Page 897 RM0316 Universal synchronous asynchronous receiver transmitter (USART) Overrun error An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared.
Page 898 Universal synchronous asynchronous receiver transmitter (USART) RM0316 The oversampling method can be selected by programming the OVER8 bit in the USART_CR1 register and can be either 16 or 8 times the baud rate clock (Figure 328 Figure 329). Depending on the application: •...
Page 899: Table 158. Noise Detection From Sampled Data
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Figure 328. Data sampling when oversampling by 16 Figure 329. Data sampling when oversampling by 8 Table 158. Noise detection from sampled data Sampled value NE status Received bit value DocID022558 Rev 8 899/1141...
Page 900 Universal synchronous asynchronous receiver transmitter (USART) RM0316 Framing error A framing error is detected when the stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. When the framing error is detected: •...
Page 901: Usart Baud Rate Generation
RM0316 Universal synchronous asynchronous receiver transmitter (USART) 29.5.4 USART baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in the USART_BRR register. Equation 1: Baud rate for standard USART (SPI mode included) (OVER8 = 0 or 1) In case of oversampling by 16, the equation is: -------------------------------- Tx/Rx baud...
Page 902 Universal synchronous asynchronous receiver transmitter (USART) RM0316 Example 2 To obtain 921.6 Kbaud with f = 48 MHz. • In case of oversampling by 16: USARTDIV = 48 000 000/921 600 BRR = USARTDIV = 52d = 34h • In case of oversampling by 8: USARTDIV = 2 * 48 000 000/921 600 USARTDIV = 104 (104d = 68h) BRR[3:0] = USARTDIV[3:0] >>...
Page 903: Tolerance Of The Usart Receiver To Clock Deviation
RM0316 Universal synchronous asynchronous receiver transmitter (USART) 29.5.5 Tolerance of the USART receiver to clock deviation The asynchronous receiver of the USART works correctly only if the total clock system deviation is less than the tolerance of the USART receiver. The causes which contribute to the total deviation are: •...
Page 904: Usart Auto Baud Rate Detection
Universal synchronous asynchronous receiver transmitter (USART) RM0316 Table 161. Tolerance of the USART receiver when BRR [3:0] is different from 0000 OVER8 bit = 0 OVER8 bit = 1 M bits ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1 3.33% 3.88% 3.03% 3.53% 1.82% 2.73% 3.7% 4.31%...
Page 905: Multiprocessor Communication Using Usart
RM0316 Universal synchronous asynchronous receiver transmitter (USART) at BRs, bit 1 to bit 6 are sampled at BR0, and further bits of the character are sampled at BR6. In parallel, another check is performed for each intermediate transition of RX line. An error is generated if the transitions on RX are not sufficiently synchronized with the receiver (the receiver being based on the baud rate calculated on bit 0).
Page 906: Figure 330. Mute Mode Using Idle Line Detection
Universal synchronous asynchronous receiver transmitter (USART) RM0316 The USART can enter or exit from mute mode using one of two methods, depending on the WAKE bit in the USART_CR1 register: • Idle Line detection if the WAKE bit is reset, •...
Page 907: Modbus Communication Using Usart
RM0316 Universal synchronous asynchronous receiver transmitter (USART) The USART exits from mute mode when an address character is received which matches the programmed address. Then the RWU bit is cleared and subsequent bytes are received normally. The RXNE bit is set for the address character since the RWU bit has been cleared.
Page 908: Usart Parity Control
Universal synchronous asynchronous receiver transmitter (USART) RM0316 29.5.9 USART parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame length defined by the M bits, the possible USART frame formats are as listed in Table 162.
Page 909: Usart Lin (Local Interconnection Network) Mode
RM0316 Universal synchronous asynchronous receiver transmitter (USART) 29.5.10 USART LIN (local interconnection network) mode This section is relevant only when LIN mode is supported. Please refer to Section 29.4: USART implementation on page 887. The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN mode, the following bits must be kept cleared: •...
Page 910: Figure 332. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
Universal synchronous asynchronous receiver transmitter (USART) RM0316 Figure 332. Break detection in LIN mode (11-bit break length - LBDL bit is set) 910/1141 DocID022558 Rev 8...
Page 911: Usart Synchronous Mode
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Figure 333. Break detection in LIN mode vs. Framing error detection 29.5.11 USART synchronous mode The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to 1. In synchronous mode, the following bits must be kept cleared: •...
Page 912: Figure 334. Usart Example Of Synchronous Transmission
Universal synchronous asynchronous receiver transmitter (USART) RM0316 Note: The CK pin works in conjunction with the TX pin. Thus, the clock is provided only if the transmitter is enabled (TE=1) and data is being transmitted (the data register USART_TDR written). This means that it is not possible to receive synchronous data without transmitting data.
Page 913: Figure 336. Usart Data Clock Timing Diagram (M Bits = 01)
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Figure 336. USART data clock timing diagram (M bits = 01) Figure 337. RX data setup/hold time Note: The function of CK is different in Smartcard mode. Refer to Section 29.5.13: USART Smartcard mode for more details.
Page 914: Usart Single-Wire Half-Duplex Communication
Universal synchronous asynchronous receiver transmitter (USART) RM0316 29.5.12 USART Single-wire Half-duplex communication Single-wire Half-duplex mode is selected by setting the HDSEL bit in the USART_CR3 register. In this mode, the following bits must be kept cleared: • LINEN and CLKEN bits in the USART_CR2 register, •...
Page 915: Figure 338. Iso 7816-3 Asynchronous Protocol
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Figure 338. ISO 7816-3 asynchronous protocol When connected to a smartcard, the TX output of the USART drives a bidirectional line that is also driven by the smartcard. The TX pin must be configured as open drain. Smartcard mode implements a single wire half duplex communication protocol.
Page 916: Figure 339. Parity Error Detection Using The 1.5 Stop Bits
Universal synchronous asynchronous receiver transmitter (USART) RM0316 • In transmission, the USART inserts the Guard Time (as programmed in the Guard Time register) between two successive characters. As the Guard Time is measured after the stop bit of the previous character, the GT[7:0] register must be programmed to the desired CGT (Character Guard Time, as defined by the 7816-3 specification) minus 12 (the duration of one character).
Page 917 RM0316 Universal synchronous asynchronous receiver transmitter (USART) Block mode (T=1) In T=1 (block) mode, the parity error transmission is deactivated, by clearing the NACK bit in the UART_CR3 register. When requesting a read from the smartcard, in block mode, the software must enable the receiver Timeout feature by setting the RTOEN bit in the USART_CR2 register and program the RTO bits field in the RTOR register to the BWT (block wait time) - 11 value.
Page 918 Universal synchronous asynchronous receiver transmitter (USART) RM0316 Note: The error checking code (LRC/CRC) must be computed/verified by software. Direct and inverse convention The Smartcard protocol defines two conventions: direct and inverse. The direct convention is defined as: LSB first, logical bit value of 1 corresponds to a H state of the line and parity is even.
Page 919: Usart Irda Sir Endec Block
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Method 2 The USART is programmed in 9-bit/no-parity mode, no bit inversion. In this mode it receives any of the two TS patterns as: (H) LHHL LLL LLH = 0x103 -> inverse convention to be chosen (H) LHHL HHH LLH = 0x13B ->...
Page 920: Figure 340. Irda Sir Endec- Block Diagram
Universal synchronous asynchronous receiver transmitter (USART) RM0316 • The IrDA specification requires the acceptance of pulses greater than 1.41 μs. The acceptable pulse width is programmable. Glitch detection logic on the receiver end filters out pulses of width less than 2 PSC periods (PSC is the prescaler value programmed in the USART_GTPR).
Page 921: Usart Continuous Communication In Dma Mode
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Figure 341. IrDA data modulation (3/16) -Normal Mode 29.5.15 USART continuous communication in DMA mode The USART is capable of performing continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Note: Please refer to Section 29.4: USART implementation on page 887...
Page 922: Figure 342. Transmission Using Dma
Universal synchronous asynchronous receiver transmitter (USART) RM0316 communication is complete. This is required to avoid corrupting the last transmission before disabling the USART or entering Stop mode. Software must wait until TC=1. The TC flag remains cleared during all data transfers and it is set by hardware at the end of transmission of the last frame.
Page 923: Rs232 Hardware Flow Control And Rs485 Driver Enable
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Figure 343. Reception using DMA Error flagging and interrupt generation in multibuffer communication In multibuffer communication if any error occurs during the transaction the error flag is asserted after the current byte. An interrupt is generated if the interrupt enable flag is set. For framing error, overrun error and noise flag which are asserted with RXNE in single byte reception, there is a separate error flag interrupt enable bit (EIE bit in the USART_CR3 register), which, if set, enables an interrupt after the current byte if any of these errors occur.
Page 924: Figure 345. Rs232 Rts Flow Control
Universal synchronous asynchronous receiver transmitter (USART) RM0316 RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and CTSE bits respectively to 1 (in the USART_CR3 register). RS232 RTS flow control If the RTS flow control is enabled (RTSE=1), then RTS is asserted (tied low) as long as the USART receiver is ready to receive a new data.
Page 925: Wakeup From Stop Mode Using Usart
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Figure 346. RS232 CTS flow control Note: For correct behavior, CTS must be asserted at least 3 USART clock source periods before the end of the current character. In addition it should be noted that the CTSCF flag may not be set for pulses shorter than 2 x PCLK periods.
Page 926 Universal synchronous asynchronous receiver transmitter (USART) RM0316 USART is not requesting it. The LSE clock is not OFF but there is a clock gating to avoid useless consumption. The MCU wakeup from Stop mode can be done using the standard RXNE interrupt. In this case, the RXNEIE bit must be set before entering Stop mode.
Page 927: Usart Low-Power Modes
RM0316 Universal synchronous asynchronous receiver transmitter (USART) If we consider an ideal case where the parameters DTRA, DQUANT, DREC and DTCL are at 0%, the DWU max is 4.86 %. In reality, we need to consider at least the HSI inaccuracy. Let us consider HSI inaccuracy = 1 %, t = 3.125 s (in case of wakeup from stop WUUSART...
Page 928: Figure 347. Usart Interrupt Mapping Diagram
Universal synchronous asynchronous receiver transmitter (USART) RM0316 1. The WUF interrupt is active only in Stop mode. The USART interrupt events are connected to the same interrupt vector (see Figure 347). • During transmission: Transmission Complete, Clear to Send, Transmit data Register empty or Framing error (in Smartcard mode) interrupt.
Page 929: Usart Registers
RM0316 Universal synchronous asynchronous receiver transmitter (USART) 29.8 USART registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. 29.8.1 Control register 1 (USART_CR1) Address offset: 0x00 Reset value: 0x0000 Res. Res. Res. EOBIE RTOIE DEAT[4:0]...
Page 930 Universal synchronous asynchronous receiver transmitter (USART) RM0316 Bits 20:16 DEDT[4:0]: Driver Enable de-assertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit duration, depending on the oversampling rate).
Page 931 RM0316 Universal synchronous asynchronous receiver transmitter (USART) Bit 8 PEIE: PE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A USART interrupt is generated whenever PE=1 in the USART_ISR register Bit 7 TXEIE: interrupt enable This bit is set and cleared by software.
Page 932: Control Register 2 (Usart_Cr2)
Universal synchronous asynchronous receiver transmitter (USART) RM0316 Bit 2 RE: Receiver enable This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit Bit 1 UESM: USART enable in Stop mode When this bit is cleared, the USART is not able to wake up the MCU from Stop mode.
Page 933 RM0316 Universal synchronous asynchronous receiver transmitter (USART) Bits 31:28 ADD[7:4]: Address of the USART node This bit-field gives the address of the USART node or a character code to be recognized. This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- bit address mark detection.
Page 934 Universal synchronous asynchronous receiver transmitter (USART) RM0316 Bit 18 DATAINV: Binary data inversion This bit is set and cleared by software. 0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) 1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.
Page 935 RM0316 Universal synchronous asynchronous receiver transmitter (USART) Note: In order to provide correctly the CK clock to the Smartcard when CK is always available When CLKEN = 1, regardless of the UE bit value, the steps below must be respected: - UE = 0 - SCEN = 1 - GTPR configuration (If PSC needs to be configured, it is recommended to configure PSC and...
Page 936: Control Register 3 (Usart_Cr3)
Universal synchronous asynchronous receiver transmitter (USART) RM0316 Bit 5 LBDL: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. 0: 10-bit break detection 1: 11-bit break detection This bit can only be written when the USART is disabled (UE=0). Note: If LIN mode is not supported, this bit is reserved and forced by hardware to ‘0’.
Page 937 RM0316 Universal synchronous asynchronous receiver transmitter (USART) Bits 21:20 WUS[1:0]: Wakeup from Stop mode interrupt flag selection This bit-field specify the event which activates the WUF (wakeup from Stop mode flag). 00: WUF active on address match (as defined by ADD[7:0] and ADDM7) 01:Reserved.
Page 938 Universal synchronous asynchronous receiver transmitter (USART) RM0316 Bit 12 OVRDIS: Overrun Disable This bit is used to disable the receive overrun detection. 0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. 1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register.
Page 939 RM0316 Universal synchronous asynchronous receiver transmitter (USART) Bit 5 SCEN: Smartcard mode enable This bit is used for enabling Smartcard mode. 0: Smartcard Mode disabled 1: Smartcard Mode enabled This bit field can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to ‘0’.
Page 940: Baud Rate Register (Usart_Brr)
Universal synchronous asynchronous receiver transmitter (USART) RM0316 29.8.4 Baud rate register (USART_BRR) This register can only be written when the USART is disabled (UE=0). It may be automatically updated by hardware in auto baud rate detection mode. Address offset: 0x0C Reset value: 0x0000 Res.
Page 941: Receiver Timeout Register (Usart_Rtor)
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Bits 31:16 Reserved, must be kept at reset value Bits 15:8 GT[7:0]: Guard time value This bit-field is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode.
Page 942: Request Register (Usart_Rqr)
Universal synchronous asynchronous receiver transmitter (USART) RM0316 Bits 31:24 BLEN[7:0]: Block Length This bit-field gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0 ->...
Page 943: Interrupt And Status Register (Usart_Isr)
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Bits 31:5 Reserved, must be kept at reset value Bit 4 TXFRQ: Transmit data flush request Writing 1 to this bit sets the TXE flag. This allows to discard the transmit data. This bit must be used only in Smartcard mode, when data has not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register.
Page 944 Universal synchronous asynchronous receiver transmitter (USART) RM0316 Bit 22 REACK: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. When the wakeup from Stop mode is supported, the REACK flag can be used to verify that the USART is ready for reception before entering Stop mode.
Page 945 RM0316 Universal synchronous asynchronous receiver transmitter (USART) Bit 15 ABRF: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE will also be set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register.
Page 946 Universal synchronous asynchronous receiver transmitter (USART) RM0316 Bit 9 CTSIF: CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register.
Page 947 RM0316 Universal synchronous asynchronous receiver transmitter (USART) Bit 4 IDLE: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register.
Page 948: Interrupt Flag Clear Register (Usart_Icr)
Universal synchronous asynchronous receiver transmitter (USART) RM0316 29.8.9 Interrupt flag clear register (USART_ICR) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WUCF Res. Res. CMCF Res. rc_w1 rc_w1 Res. Res. Res. EOBCF RTOCF Res.
Page 949: Receive Data Register (Usart_Rdr)
RM0316 Universal synchronous asynchronous receiver transmitter (USART) Bit 3 ORECF: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register. Bit 2 NCF: Noise detected clear flag Writing 1 to this bit clears the NF flag in the USART_ISR register. Bit 1 FECF: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.
Page 950: Usart Register Map
Universal synchronous asynchronous receiver transmitter (USART) RM0316 Bits 31:9 Reserved, must be kept at reset value. Bits 8:0 TDR[8:0]: Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 323).
Page 951 RM0316 Universal synchronous asynchronous receiver transmitter (USART) Table 165. USART register map and reset values (continued) Offset Register USART_ISR 0x1C Reset value USART_ICR 0x20 Reset value USART_RDR RDR[8:0] 0x24 Reset value X X X X X X X X X USART_TDR TDR[8:0] 0x28...
Page 952: Serial Peripheral Interface / Inter-Ic Sound (Spi/I2S)
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) 30.1 Introduction The SPI/I²S interface can be used to communicate with external devices using the SPI protocol or the I S audio protocol. SPI or I S mode is selectable by software.
Page 953: I2S Main Features
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) 30.3 I2S main features • Full-duplex communication • Half-duplex communication (only transmitter or receiver) • Master or slave operations • 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 192 kHz) •...
Page 954: Spi Functional Description
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Table 167. STM32F303xB/C/D/E, STM32F358xC and STM32F398xE SPI implementation Features SPI1 SPI2 SPI3 SPI4 Hardware CRC calculation Rx/Tx FIFO NSS pulse mode I2S mode TI mode 1. X = supported. 2. SPI4 is only in STM32F303xD/E. 30.5 SPI functional description 30.5.1...
Page 955: Communications Between One Master And One Slave
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Four I/O pins are dedicated to SPI communication with external devices. • MISO: Master In / Slave Out data. In the general case, this pin is used to transmit data in slave mode and receive data in master mode. •...
Page 956: Half-Duplex Communication
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Half-duplex communication The SPI can communicate in half-duplex mode by setting the BIDIMODE bit in the SPIx_CR1 register. In this configuration, one single cross connection line is used to link the shift registers of the master and slave together. During this communication, the data is synchronously shifted between the shift registers on the SCK clock edge in the transfer direction selected reciprocally by both master and slave with the BDIOE bit in their SPIx_CR1 registers.
Page 957: Standard Multi-Slave Communication
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Figure 351. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) 1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the pins can be left unused by the peripheral.
Page 958: Multi-Master Communication
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Figure 352. Master and three independent slaves 1. NSS pin is not used on master side at this configuration. It has to be managed internally (SSM=1, SSI=1) to prevent any MODF error. 2.
Page 959: Slave Select (Nss) Pin Management
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) completed, the active slave select signal is released and the node mastering the bus temporary returns back to passive slave mode waiting for next session start. If potentially both nodes raised their mastering request at the same time a bus conflict event appears (see mode fault MODF event).
Page 960: Communication Formats
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Figure 354. Hardware/software slave select management 30.5.6 Communication formats During SPI communication, receive and transmit operations are performed simultaneously. The serial clock (SCK) synchronizes the shifting and sampling of the information on the data lines.
Page 961: Figure 355. Data Clock Timing Diagram
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Figure 355, shows an SPI full-duplex transfer with the four combinations of the CPHA and CPOL bits. Note: Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit. The idle state of SCK must correspond to the polarity selected in the SPIx_CR1 register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
Page 962: Configuration Of Spi
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Figure 356. Data alignment when data length is not equal to 8-bit or 16-bit Note: The minimum data length is 4 bits. If a data length of less than 4 bits is selected, it is forced to an 8-bit data frame size.
Page 963: Procedure For Enabling Spi
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Note: (1) Step is not required in slave mode. (2) Step is not required in TI mode. (3) Step is not required in NSSP mode. (4) The step is not required in slave mode except slave working at TI mode 30.5.8 Procedure for enabling SPI It is recommended to enable the SPI slave before the master sends the clock.
Page 964 Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 TXFIFO. Both TXE and RXNE events can be polled or handled by interrupts. See Figure 358 through Figure 361. Another way to manage the data exchange is to use DMA (see Section 13.2: DMA main features).
Page 965 RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) transacted to prevent some dummy byte exchange (refer to Data packing section). Before the SPI is disabled in these modes, the user must follow standard disable procedure. When the SPI is disabled at the master transmitter while a frame transaction is ongoing or next data frame is stored in TXFIFO, the SPI behavior is not guaranteed.
Page 966: Figure 357. Packing Data In Fifo For Transmission And Reception
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 RXFIFO threshold is set to 16 bits (FRXTH=0). The receiver then has to access both data frames by a single 16-bit read of SPIx_DR as a response to this single RXNE event. The RxFIFO threshold setting and the following read access must be always kept aligned at the receiver side, as data can be lost if it is not in line.
Page 967 RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Enable DMA Rx buffer in the RXDMAEN bit in the SPI_CR2 register, if DMA Rx is used. Enable DMA streams for Tx and Rx in DMA registers, if the streams are used. Enable DMA Tx buffer in the TXDMAEN bit in the SPI_CR2 register, if DMA Tx is used.
Page 968 Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Communication diagrams Some typical timing schemes are explained in this section. These schemes are valid no matter if the SPI events are handled by polling, interrupts or DMA. For simplicity, the LSBFIRST=0, CPOL=0 and CPHA=1 setting is used as a common assumption here. No complete configuration of DMA streams is provided.
Page 969: Figure 358. Master Full-Duplex Communication
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Figure 358. Master full-duplex communication Assumptions for master full-duplex communication example: • Data size > 8 bit If DMA is used: • Number of Tx frames transacted by DMA is set to 3 •...
Page 970: Figure 359. Slave Full-Duplex Communication
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Figure 359. Slave full-duplex communication Assumptions for slave full-duplex communication example: • Data size > 8 bit If DMA is used: • Number of Tx frames transacted by DMA is set to 3 •...
Page 971: Figure 360. Master Full-Duplex Communication With Crc
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Figure 360. Master full-duplex communication with CRC Assumptions for master full-duplex communication with CRC example: • Data size = 16 bit • CRC enabled If DMA is used: • Number of Tx frames transacted by DMA is set to 2 •...
Page 972: Figure 361. Master Full-Duplex Communication In Packed Mode
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Figure 361. Master full-duplex communication in packed mode Assumptions for master full-duplex communication in packed mode example: • Data size = 5 bit • Read/write FIFO is performed mostly by 16-bit access •...
Page 973: Spi Status Flags
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) 30.5.10 SPI status flags Three status flags are provided for the application to completely monitor the state of the SPI bus. Tx buffer empty flag (TXE) The TXE flag is set when transmission TXFIFO has enough space to store data to send. TXE flag is linked to the TXFIFO level.
Page 974: Spi Error Flags
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 30.5.11 SPI error flags An SPI interrupt is generated if one of the following error flags is set and interrupt is enabled by setting the ERRIE bit. Overrun flag (OVR) An overrun condition occurs when data is received by a master or slave and the RXFIFO has not enough space to store this received data.
Page 975: Nss Pulse Mode
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) The FRE flag is cleared when SPIx_SR register is read. If the ERRIE bit is set, an interrupt is generated on the NSS error detection. In this case, the SPI should be disabled because data consistency is no longer guaranteed and communications should be reinitiated by the master when the slave SPI is enabled again.
Page 976: Crc Calculation
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 baud rate value set in through the BR[2:0] bits in the SPIx_CR1 register. It is given by the formula: baud_rate baud_rate --------------------- - --------------------- - × < < × pclk release pclk If the slave detects a misplaced NSS pulse during a data frame transaction the TIFRE flag is set.
Page 977 RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Note: The polynomial value should only be odd. No even values are supported. CRC transfer managed by CPU Communication starts and continues normally until the last data frame has to be sent or received in the SPIx_DR register.
Page 978: Spi Interrupts
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 If the SPI is disabled during a communication the following sequence must be followed: Disable the SPI Clear the CRCEN bit Enable the CRCEN bit Enable the SPI Note: When the SPI is in slave mode, the CRC calculator is sensitive to the SCK slave input clock as soon as the CRCEN bit is set, and this is the case whatever the value of the SPE bit.
Page 979: I 2 S Functional Description (Stm32F303Xb/C/D/E, Stm32F358Xc And Stm32F398Xe Only)
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) 30.7 S functional description (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE only) 30.7.1 S general description The block diagram of the I S is shown in Figure 364. Figure 364. I S block diagram 1. I2S2ext_SD and I2S3ext_SD are the extended SD pins that control the I2S full-duplex mode. DocID022558 Rev 8 979/1141 1010...
Page 980: I2S Full Duplex
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 The SPI can function as an audio I S interface when the I S capability is enabled (by setting the I2SMOD bit in the SPIx_I2SCFGR register). This interface mainly uses the same pins, flags and interrupts as the SPI.
Page 981: Supported Audio Protocols
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Figure 365. I2S full-duplex block diagram 1. Where x can be 2 or 3. I2Sx can operate in master mode. As a result: • Only I2Sx can output SCK and WS in half-duplex mode •...
Page 982: Figure 366. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy)
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 S Philips standard For this standard, the WS signal is used to indicate which channel is being transmitted. It is activated one CK clock cycle before the first bit (MSB) is available. Figure 366.
Page 983: Figure 368. Transmitting 0X8Eaa33
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Figure 368. Transmitting 0x8EAA33 • In reception mode: If data 0x8EAA33 is received: Figure 369. Receiving 0x8EAA33 Figure 370. I S Philips standard (16-bit extended to 32-bit packet frame) When 16-bit data frame extended to 32-bit channel frame is selected during the I configuration phase, only one access to the SPIx_DR register is required.
Page 984: Figure 372. Msb Justified 16-Bit Or 32-Bit Full-Accuracy Length
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 For transmission, each time an MSB is written to SPIx_DR, the TXE flag is set and its interrupt, if allowed, is generated to load the SPIx_DR register with the new value to send. This takes place even if 0x0000 have not yet been sent because it is done by hardware.
Page 985: Figure 374. Msb Justified 16-Bit Extended To 32-Bit Packet Frame
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Figure 374. MSB justified 16-bit extended to 32-bit packet frame LSB justified standard This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit full-accuracy frame formats). The sampling of the input and output signals is the same as for the I2S Philips standard.
Page 986: Figure 377. Operations Required To Transmit 0X3478Ae
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Figure 377. Operations required to transmit 0x3478AE • In reception mode: If data 0x3478AE are received, two successive read operations from the SPIx_DR register are required on each RXNE event. Figure 378. Operations required to receive 0x3478AE Figure 379.
Page 987: Figure 380. Example Of 16-Bit Data Frame Extended To 32-Bit Channel Frame
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Figure 380. Example of 16-bit data frame extended to 32-bit channel frame In transmission mode, when a TXE event occurs, the application has to write the data to be transmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit). The TXE flag is set again as soon as the effective data (0x76A3) is sent on SD.
Page 988: Start-Up Description
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Figure 382. PCM standard waveforms (16-bit extended to 32-bit packet frame) Note: For both modes (master and slave) and for both synchronizations (short and long), the number of bits between two consecutive pieces of data (and so two synchronization signals) needs to be specified (DATLEN and CHLEN bits in the SPIx_I2SCFGR register) even in slave mode.
Page 989: Figure 383. Start Sequence In Master Mode
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Figure 383. Start sequence in master mode In slave mode, the user has to enable the audio interface before the WS becomes active. This means that the I2SE bit must be set to 1 when WS = 1 for I2S Philips standard, or when WS = 0 for other standards.
Page 990: Clock Generator
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 30.7.5 Clock generator The I S bit rate determines the data flow on the I S data line and the I S clock signal frequency. S bit rate = number of bits per channel × number of channels × sampling audio frequency For a 16-bit audio, left and right channel, the I S bit rate is calculated as follows: S bit rate = 16 ×...
Page 991: I 2 S Master Mode
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) When the master clock is generated (MCKOE in the SPIx_I2SPR register is set): = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide When the master clock is disabled (MCKOE bit cleared): = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide...
Page 992 Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Procedure Select the I2SDIV[7:0] bits in the SPIx_I2SPR register to define the serial clock baud rate to reach the proper audio sample frequency. The ODD bit in the SPIx_I2SPR register also has to be defined. Select the CKPOL bit to define the steady level for the communication clock.
Page 993: I 2 S Slave Mode
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) if the RXNEIE bit is set in SPIx_CR2 register. Depending on the data and channel length configuration, the audio value received for a right or left channel may result from one or two receptions into the Rx buffer.
Page 994 Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Set the I2SMOD bit in the SPIx_I2SCFGR register to select I S mode and choose the S standard through the I2SSTD[1:0] bits, the data length through the DATLEN[1:0] bits and the number of bits per channel for the frame configuring the CHLEN bit. Select also the mode (transmission or reception) for the slave through the I2SCFG[1:0] bits in SPIx_I2SCFGR register.
Page 995: I 2 S Status Flags
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Reception sequence The operating mode is the same as for the transmission mode except for the point 1 (refer to the procedure described in Section 30.7.7: I2S slave mode), where the configuration should set the master reception mode using the I2SCFG[1:0] bits in the SPIx_I2SCFGR register.
Page 996: I 2 S Error Flags
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Note: Do not use the BSY flag to handle each data transmission or reception. It is better to use the TXE and RXNE flags instead. Tx buffer empty flag (TXE) When set, this flag indicates that the Tx buffer is empty and the next data to be transmitted can then be loaded into it.
Page 997: Dma Features
RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Frame error flag (FRE) This flag can be set by hardware only if the I S is configured in Slave mode. It is set if the external master is changing the WS line while the slave is not expecting this change. If the synchronization is lost, the following steps are required to recover from this state and resynchronize the external master device with the I S slave device:...
Page 998: Spi And I 2 S Registers
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 30.9 SPI and I S registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR in addition by can be accessed by 8-bit access. 30.9.1 SPI control register 1 (SPIx_CR1) Address offset: 0x00 Reset value: 0x0000 BIDI...
Page 999 RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Bit 10 RXONLY: Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted.
Page 1000: Spi Control Register 2 (Spix_Cr2)
Serial peripheral interface / inter-IC sound (SPI/I2S) RM0316 Bit 2 MSTR: Master selection 0: Slave configuration 1: Master configuration Note: This bit should not be changed when communication is ongoing. This bit is not used in I S mode. Bit1 CPOL: Clock polarity 0: CK to 0 when idle 1: CK to 1 when idle Note: This bit should not be changed when communication is ongoing.
Page 1001 RM0316 Serial peripheral interface / inter-IC sound (SPI/I2S) Bit 12 FRXTH: FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) Note: This bit is not used in I²S mode.

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