Icom IC-280E Instruction Manual page 16

15
VCO circuit
08 is an oscillator and Q9 is a buffer. In the transmitting mode, the VCO signal is frequency
modulated by the audio signals from the microphone through the varicap D8, and the output
frequency is the transmitting frequency.
In the receiving mode, the oscillating frequency is shifted down by the value of the IF frequency
by shorting C41 and C43 through D7.
Buffer and pre-driver circuit
09 is the VCO buffer, O10 the transmitting buffer, O11 the transmitting pre-driver, and Q14 the
receiving buffer. Since the VCO of the 1C-280E is used both for transmitting and receiving, the
operation frequency range is as wide as (approximately) 19MHz. Therefore, all the buffers for
theVCO are designed for very wide passband operation. The power of the buffers for transmitting
and receiving and the pre-driver circuits are turned OFF when not needed.
Other circuits
In the PLL unit, the microphone amplifier circuit, Q13, is included and the output of this circuit
is fed to the VCO.
When the PLL fails to lock, O4 controls O7 by used of a lock failure pulse signal in order to
prevent undesired radiation caused by the lock failure.
DRIVER UNIT
Up Down Detector Circuit
A signal 90 degrees out of phase is generated by the photo-interrupter of IC1 and IC2 and a photo
chopper disc. The flip-flop of IC4 and IC5 latches the signal temporarily. The output signal is
synchronized with the RO signal and controls the gates of IC6, from which the output signals are
fed to K1, K2 and K4 of the CPU.
The flip-flop of IC4 and IC5 functions as a quad counter and stores the data (0-3) according to the
dial rotating speed.
When the power is turned ON, the preset counter in the CPU provides operation at 145.00MHz
and the frequency is displayed on the frequency display LEDs. At the same time, the pulse signal
appears at R10 of the CPU and it clears IC4 and IC5. When the signal from the sensor generated
by the dial rotation is latched by IC4 and IC5, the gates of ICG are controlled, synchronizing
control signals with the pulse signal from the RO of the CPU, and the latched data (0-3) are fed to
K1, K2 and K8 of the CPU. K1 and K2 receive the quad counter data, K4 determines if the input
signals is from the dial or memory and K8 determines if it is an UP signal or a DOWN signal. K1
and K2 data are added to or subtracted from the preset frequency (145.00MHz) according to the
UP/DOWN signal.
In other words, addition or subtraction functions are made according to the data read from the
pulse interval of the RO and this operation is repeated after each clearance made by the pulse
signals from the R10.
Display Latch Circuit
The divide ratio (N) is fed from the CPU to the frequency display and the PLL divider provide
time-sharing operation.