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Precision Analog-to-Digital Converter (ADC)
and Digital-to-Analog Converter (DAC)
with 8051 Microcontroller and Flash Memory
FEATURES
ANALOG FEATURES
24-BITS NO MISSING CODES
22-BITS EFFECTIVE RESOLUTION AT 10Hz
Low Noise: 75nV
PGA FROM 1 TO 128
PRECISION ON-CHIP VOLTAGE REFERENCE
8 DIFFERENTIAL/SINGLE-ENDED CHANNELS
ON-CHIP OFFSET/GAIN CALIBRATION
OFFSET DRIFT: 0.02ppm/
GAIN DRIFT: 0.5ppm/
ON-CHIP TEMPERATURE SENSOR
SELECTABLE BUFFER INPUT
BURNOUT DETECT
8-BIT CURRENT DAC
DIGITAL FEATURES
Microcontroller Core
8051-COMPATIBLE
HIGH-SPEED CORE:
4 Clocks per Instruction Cycle
DC TO 33MHz
ON-CHIP OSCILLATOR
PLL WITH 32kHz CAPABILITY
SINGLE INSTRUCTION 121ns
DUAL DATA POINTER
Memory
4kB OR 8kB OF FLASH MEMORY
FLASH MEMORY PARTITIONING
ENDURANCE 1M ERASE/WRITE CYCLES,
100 YEAR DATA RETENTION
128 BYTES DATA SRAM
IN-SYSTEM SERIALLY PROGRAMMABLE
FLASH MEMORY SECURITY
1kB BOOT ROM
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
°
C
°
C
www.ti.com
SBAS289E – JUNE 2003 – REVISED NOVEMBER 2004
Peripheral Features
16 DIGITAL I/O PINS
ADDITIONAL 32-BIT ACCUMULATOR
TWO 16-BIT TIMER/COUNTERS
SYSTEM TIMERS
PROGRAMMABLE WATCHDOG TIMER
FULL DUPLEX USART
™
BASIC SPI
2
™
BASIC I
C
POWER MANAGEMENT CONTROL
INTERNAL CLOCK DIVIDER
IDLE MODE CURRENT < 200
STOP MODE CURRENT < 100nA
DIGITAL BROWNOUT RESET
ANALOG LOW VOLTAGE DETECT
20 INTERRUPT SOURCES
GENERAL FEATURES
PACKAGE: TQFP-48
LOW POWER: 3mW
INDUSTRIAL TEMPERATURE RANGE:
°
°
–40
C to +85
C
POWER SUPPLY: 2.7V to 5.25V
APPLICATIONS
INDUSTRIAL PROCESS CONTROL
INSTRUMENTATION
LIQUID/GAS CHROMATOGRAPHY
BLOOD ANALYSIS
SMART TRANSMITTERS
PORTABLE INSTRUMENTS
WEIGH SCALES
PRESSURE TRANSDUCERS
INTELLIGENT SENSORS
PORTABLE APPLICATIONS
DAS SYSTEMS
Copyright © 2003-2004, Texas Instruments Incorporated
MSC1200
µ
A
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Table of Contents
Related Manuals for Texas Instruments BB MSC1200 Series
Summary of Contents for Texas Instruments BB MSC1200 Series
- Page 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
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Page 2: Absolute Maximum Ratings
PACKAGE/ORDERING INFORMATION SPECIFIED FLASH PACKAGE TEMPERATURE PACKAGE PRODUCT MEMORY PACKAGE-LEAD DESIGNATOR RANGE MARKING MSC1200Y2 TQFP-48 –40°C to +85°C MSC1200Y2 " " " " MSC1200Y2 MSC1200Y3 TQFP-48 –40°C to +85°C MSC1200Y3 " " " " MSC1200Y3 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our web site at www.ti.com/msc. - Page 3 ELECTRICAL CHARACTERISTICS: AV = 5V (Cont.) ≡ (REF IN+) – (REF IN–) = +2.5V, All specifications from T to T , DV = +2.7V to 5.25V, f = 15.625kHz, PGA = 1, Buffer ON, f = 10Hz, Bipolar, and V DATA unless otherwise noted.
- Page 4 ELECTRICAL CHARACTERISTICS: AV = 3V ≡ (REF IN+) – (REF IN–) = +1.25V, All specifications from T to T , AV = +3V, DV = +2.7V to 5.25V, f = 15.625kHz, PGA = 1, Buffer ON, f = 10Hz, Bipolar, and V DATA unless otherwise noted.
- Page 5 DIGITAL CHARACTERISTICS: DV = 2.7V to 5.25V All specifications from T to T , unless otherwise specified. MSC1200Yx PARAMETER CONDITION UNITS POWER-SUPPLY REQUIREMENTS Digital Supply Current Normal Mode, f = 1MHz Normal Mode, f = 8MHz, All Peripherals ON Internal Oscillator LF Mode (12.8MHz nominal) Stop Mode, DBOR OFF 4.75 5.25...
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Page 6: Ac Electrical Characteristics
AC ELECTRICAL CHARACTERISTICS : DV = 2.7V to 5.25V MSC1200Yx PARAMETER CONDITION UNITS PHASE LOCK LOOP (PLL) Input Frequency Range External Crystal/Clock Frequency (f 32.768 PLL LF Mode PLLDIV = 449 (default) 14.7456 PLL HF Mode PLLDIV = 899 (must be set by user) 29.4912 PLL Lock Time Within 1%... -
Page 7: Pin Configuration
PIN CONFIGURATION Top View TQFP XOUT DGND DGND DGND P1.6/INT4 P1.5/INT3 MSC1200 P1.4/INT2/SS P1.3/DIN P1.2/DOUT AGND P1.1 AGND P1.0/PROG AINCOM MSC1200 SBAS289E www.ti.com... -
Page 8: Pin Descriptions
PIN DESCRIPTIONS PIN # NAME DESCRIPTION 1,6,7,16,25,47 No Connection The crystal oscillator pin XIN supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. XIN can also be an input if there is an external clock source instead of a crystal. XOUT The crystal oscillator pin XOUT supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. -
Page 9: Typical Characteristics
TYPICAL CHARACTERISTICS ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. = +5V, DV = +5V, f = 8MHz, PGA = 1, f = 15.625kHz, Bipolar, Buffer ON, and V EFFECTIVE NUMBER OF BITS EFFECTIVE NUMBER OF BITS vs DATA RATE vs DECIMATION RATIO PGA8 PGA2... - Page 10 TYPICAL CHARACTERISTICS (Cont.) ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. = +5V, DV = +5V, f = 8MHz, PGA = 1, f = 15.625kHz, Bipolar, Buffer ON, and V EFFECTIVE NUMBER OF BITS vs f FAST SETTLING FILTER (set with ACLK) EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO = 203kHz...
- Page 11 TYPICAL CHARACTERISTICS (Cont.) ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. = +5V, DV = +5V, f = 8MHz, PGA = 1, f = 15.625kHz, Bipolar, Buffer ON, and V INL ERROR vs PGA ADC INTEGRAL NONLINEARITY vs V = 5V Buffer OFF = 2.5V...
- Page 12 TYPICAL CHARACTERISTICS (Cont.) ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. = +5V, DV = +5V, f = 8MHz, PGA = 1, f = 15.625kHz, Bipolar, Buffer ON, and V DIGITAL SUPPLY CURRENT vs FREQUENCY OFFSET DAC: GAIN vs TEMPERATURE 1.00006 1.00004 1.00002...
- Page 13 TYPICAL CHARACTERISTICS (Cont.) ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. = +5V, DV = +5V, f = 8MHz, PGA = 1, f = 15.625kHz, Bipolar, Buffer ON, and V IO LF MODE vs TEMPERATURE IO HF MODE vs FREQUENCY = DV = DV 5.25V...
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Page 14: Enhanced 8051 Core
DESCRIPTION The MSC1200Yx allows the user to uniquely configure the Flash memory map to meet the needs of their application. The MSC1200Yx is a completely integrated family of mixed- The Flash is programmable down to 2.7V using serial pro- signal devices incorporating a high-resolution delta-sigma gramming. -
Page 15: Family Device Compatibility
standard 8051 core. This allows the user to run the device at The MSC1200 also provides dual data pointers (DPTRs). slower clock speeds, which reduces system noise and power Furthermore, improvements were made to peripheral fea- consumption, but provides greater throughput. This performance tures that off-load processing from the core and the user, to difference can be seen in Figure 3. - Page 16 OVERVIEW The MSC1200 ADC structure is shown in Figure 5. The figure lists the components that make up the ADC, along with the corresponding special function register (SFR) associated with each component. Burnout AIN0 REFIN+ Detect AIN1 AIN2 SAMP AIN3 Input AIN4 Multiplexer...
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Page 17: Input Buffer
INPUT MULTIPLEXER BURNOUT DETECT The input multiplexer provides for any combination of differential When the Burnout Detect (BOD) bit is set in the ADC control inputs to be selected as the input channel, as shown in Figure 6. configuration register (ADCON0 DC ), two current sources are If AIN0 is selected as the positive differential input channel, any enabled. -
Page 18: Offset Dac
requires a positive full-scale differential input signal. It then computes a gain value to nullify gain errors in the system. The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Each of these calibrations will take seven t periods to Using the PGA can actually improve the effective resolution DATA... -
Page 19: Voltage Reference
If the internal V is not used, then V should be disabled SINC FILTER RESPONSE in ADCON0. (–3dB = 0.262 • f If the external voltage reference is selected it can be used as DATA –20 either a single-ended input of differential input, for ratiometric measures. - Page 20 DIGITAL BROWNOUT RESET POWER-UP—SUPPLY VOLTAGE RAMP RATE The Digital Brownout Reset (DBOR) is enabled through The built-in (on-chip) power-on reset circuitry was designed Hardware Configuration Register 1 (HCR1). If the conditions to accommodate analog or digital supply ramp rates as slow for proper POR are not met or the device encounters a as 1V/10ms.
- Page 21 clock, or external oscillator. If an external clock is detected at startup, then the CPU will begin execution in ECM after startup. If an external clock is not detected at startup, then the device will revert to the mode shown in Table II. XOUT In Phase Lock Loop (PLL) mode (HCR2, CLKSEL = 101 or HCR2, CLKSEL = 100), the CPU can execute from an...
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Page 22: Power Down
The timing diagram for supported SPI data transfers is pin can be used to control the output of data on shown in Figure 16. DOUT when the MSC1200 is in slave mode. The function is enabled or disabled by the ESS bit of the SPICON SFR. The I/O pins needed for data transfer are Data In (DIN), Data When enabled, the input of a slave device must be... - Page 23 Slave Mode Application Flow transferred. I C mode also allows for interrupt generation on one bit of data transfer (I2CCON.CNTSEL). This can be used 1. Configure the ports pins. for ACK/NACK interrupt generation. For instance, the I 2. Enable (if applicable). interrupt can be configured for 8-bit interrupt detection, on the 3.
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Page 24: Memory Map
FLASH MEMORY CNTIF is generated and SCL is stretched by the MSC1200 until the I2CDATA register is written with a 0xFF . The The MSC1200 uses a memory addressing scheme that ACK/NACK from the master can then be read. separates Program Memory from Data Memory. The program Receive and data segments can overlap since they are accessed by different instructions. -
Page 25: Data Memory
It is important to note that the Flash Memory is readable and SFRs are accessed directly between 80 and FF (128 to writable (depending on the MXWS bit in the MWS SFR) by 255). Scratchpad RAM is available for general-purpose data the user through the MOVX instruction when configured as storage. -
Page 26: Working Registers
Working Registers last used value. Therefore, the next value placed on the Stack is put at SP + 1. Each PUSH or CALL will increment As part of the lower 128 bytes of RAM, there are four banks the SP by the appropriate value. Each POP or RET will of Working Registers, as shown in Figure 20. - Page 27 Serial Flash Programming Mode INTERRUPTS Two methods of programming are available: serial program- The MSC1200 uses a three-priority interrupt system. As ming mode and user application mode. Serial programming shown in Table VII, each interrupt source has an indepen- mode is initiated by holding the P1.0/PROG pin low during dent priority bit, flag, interrupt vector, and enable (except that...
- Page 28 Hardware Configuration Register 0 (HCR0)—Accessed Using SFR Registers CADDR and CDATA. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CADDR 3F EPMA EWDR DFSEL1 DFSEL0 To read this register during normal operation, refer to the register descriptions for CADDR and CDATA. EPMA Enable Programming Memory Access (Security Bit).
- Page 29 Hardware Configuration Register 1 (HCR1) CADDR 3E To read this register during normal operation, refer to the register descriptions for CADDR and CDATA. Disable Digital Brownout Detection bit 2 0: Enable Digital Brownout Detection (2.7V) 1: Disable Digital Brownout Detection (default) Hardware Configuration Register 2 (HCR2) CADDR 3D CLKSEL2...
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Page 30: Table Of Contents
SFR Definitions ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUES DPL0 DPH0 DPL1 DPH1 PCON SMOD STOP IDLE TCON TMOD |---------------------------Timer 1 --------------------------| |--------------------------Timer 0 ---------------------------| GATE GATE CKCON MXWS P1.7... -
Page 31: Sfr Definitions
SFR Definitions (Cont.) ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUES EWUWDT EWUEX1 EWUEX0 SYSCLK DIVMOD1 DIVMOD0 DIV2 DIV1 DIV0 ADMUX INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 EICON WDTI... -
Page 32: Bit 0
Stack Pointer (SP) Reset Value SFR 81 SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 SP.7-0 Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented before bits 7-0 every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07 after reset. -
Page 33: Bit 3
Power Control (PCON) Reset Value SFR 87 SMOD STOP IDLE SMOD Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0. bit 7 0: Serial Port 0 baud rate will be a standard baud rate. 1: Serial Port 0 baud rate will be double that defined by baud rate generation equation. -
Page 34: Timer 1
Timer Mode Control (TMOD) TIMER 1 TIMER 0 Reset Value SFR 89 GATE GATE GATE Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment. bit 7 0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1. 1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1. -
Page 35: T1M T0M
Timer 1 MSB (TH1) Reset Value SFR 8D TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 TH1.7-0 Timer 1 MSB. This register contains the most significant byte of Timer 1. bits 7-0 Clock Control (CKCON) Reset Value SFR 8E Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0 bit 4 maintains 8051 compatibility. - Page 36 External Interrupt Flag (EXIF) Reset Value SFR 91 External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be bit 7 cleared manually by software. Setting this bit in software will cause an interrupt if enabled. External Interrupt 4 Flag.
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Page 37: Sm1_0
Serial Port 0 Control (SCON0) Reset Value SFR 98 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 SM0-2 Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit bits 7-5 in addition to the 8 or 9 data bits. - Page 38 SPI Control (SPICON) (SERSEL bit determines SPICON control) Reset Value SBIT3 SBIT2 SBIT1 SBIT0 ORDER CPHA CPOL SFR 9A SBIT3-0 Serial Bit Count. Number of bits transferred (read only). bits 7-4 SBIT3:0 COUNT 0x00 0x01 0x03 0x02 0x06 0x07 0x05 0x04 0x0C ORDER...
- Page 39 Disable Serial Clock Stretch. bit 1 0: Enable SCL Stretch (cleared by firmware or START condition) 1: Disable SCL Stretch CNTSEL Counter Select. bit 0 0: Counter IRQ Set for Bit Counter = 8 (default) 1: Counter IRQ Set for Bit Counter = 1 SPI Data Register (SPIDATA) / I C Data Register (I2CDATA) Reset Value...
- Page 40 Pending Auxiliary Interrupt (PAI) Reset Value SFR A5 PAI3 PAI2 PAI1 PAI0 Pending Auxiliary Interrupt Register. The results of this register can be used as an index to vector to the appropriate bits 3-0 interrupt routine. All of these interrupts vector through address 0033 PAI3 PAI2 PAI1...
- Page 41 Auxiliary Interrupt Status Register (AISTAT) Reset Value SFR A7 MSEC ALVD Second System Timer Interrupt Status Flag (lowest priority AI). bit 7 0: SEC Interrupt cleared or masked. 1: SEC Interrupt active (it is cleared by reading SECINT, SFR F9 Summation Register Interrupt Status Flag.
- Page 42 Port 1 Data Direction Low Register (P1DDRL) Reset Value SFR AE P13H P13L P12H P12L P11H P11L P10H P10L P1.3 Port 1 bit 3 control. bits 7-6 P13H P13L Standard 8051 CMOS Output Open Drain Output Input P1.2 Port 1 bit 2 control. bits 5-4 P12H P12L...
- Page 43 Port 3 (P3) Reset Value SFR B0 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 INT1 INT0 SCK/SCL/CLKS TXD0 RXD0 P3.7-0 General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have bits 7-0 an alternative function listed below.
- Page 44 Port 3 Data Direction High Register (P3DDRH) Reset Value SFR B4 P37H P37L P36H P36L P35H P35L P34H P34L P3.7 Port 3 bit 7 control. bits 7-6 P37H P37L Standard 8051 CMOS Output Open Drain Output Input NOTE: Port 3.7 also controlled by and Memory Access Control HCR1.1.
- Page 45 Enable Wake Up (EWU) Waking Up from IDLE Mode Reset Value SFR C6 — — — — — EWUWDT EWUEX1 EWUEX0 Auxiliary interrupts will wake up from IDLE. They are enabled with EAI (EICON.5). EWUWDT Enable Wake Up Watchdog Timer. Wake up using watchdog timer interrupt. bit 2 0 = Don’t wake up on watchdog timer interrupt.
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Page 46: Program Status Word (Psw)
Program Status Word (PSW) Reset Value SFR D0 Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow bit 7 (during subtraction). Otherwise it is cleared to 0 by all arithmetic operations. Auxiliary Carry Flag. - Page 47 ADC Gain Calibration Register Low Byte (GCL) Reset Value SFR D4 ADC Gain Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC bits 7-0 gain calibration. A value which is written to this location will set the ADC gain calibration value. ADC Gain Calibration Register Middle Byte (GCM) Reset Value SFR D5...
- Page 48 Enable Interrupt Control (EICON) Reset Value SFR D8 WDTI Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and bit 5 identified by SFR registers PAI (SFR A5 ), AIE (SFR A6 ), and AISTAT (SFR A7 0 = Auxiliary Interrupt disabled (default).
- Page 49 ADC Control Register 0 (ADCON0) Reset Value SFR DC — EVREF VREFH EBUF PGA2 PGA1 PGA0 Burnout Detect. When enabled this connects a positive current source to the positive channel and a negative current bit 6 source to the negative channel. If the channel is open circuit then the ADC results will be full-scale (buffer must be enabled). 0 = Burnout Current Sources Off (default).
- Page 50 ADC Control Register 1 (ADCON1) Reset Value SFR DD OF_UF — CAL2 CAL1 CAL0 x000 0000 OF_UF Overflow/Underflow. If this bit is set, the data in the summation register is invalid. Either an overflow or an bit 7 underflow occurred. The bit is cleared by writing a 0 to it. Polarity.
- Page 51 SSCON1-0 Summation/Shift Control. bits 7-6 SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 DESCRIPTION Clear Summation Register CPU Summation on Write to SUMR0 CPU Subtraction on Write to SUMR0 Note (1) Note (1) Note (1) CPU Shift Only Note (1) Note (1) Note (1) ADC Summation Only...
- Page 52 Offset DAC Register (ODAC) Reset Value SFR E6 ODAC Offset DAC Register. This register will shift the input by up to half of the ADC full-scale input range. The offset bit7-0 DAC value is summed with the ADC input prior to conversion. Writing 00 or 80 to ODAC turns off the Offset DAC.
- Page 53 Hardware Product Code Register 0 (HWPC0) Reset Value SFR E9 MEMORY 0000_000x HWPC0.7-0 Hardware Product Code LSB. Read only. MEMORY SIZE MODEL FLASH MEMORY bits 7-0 MSC1200Y2 MSC1200Y3 Hardware Product Code Register 1 (HWPC1) Reset Value SFR EA HWPC1.7-0 Hardware Product Code MSB. Read only. bits 7-0 Hardware Version Register (HWVER) Reset Value...
- Page 54 Power-Down Control Register (PDCON) Reset Value SFR F1 PDICLK PDIDAC PDI2C PDADC PDWDT PDSPI PDSPI Turning peripheral modules off puts the MSC1200 in the lowest power mode. PDICLK Internal Clock Control. bit 7 0 = Internal Oscillator and PLL On (Internal Oscillator or PLL mode) 1 = Internal Oscillator and PLL Power Down (External Clock mode) PDIDAC IDAC Control.
- Page 55 Phase Lock Loop Low Register (PLLL) Reset Value SFR F4 PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0 PLL7-0 PLL Counter Value Least Significant Bit. bits 7-0 PLL Frequency = External Crystal Frequency • PLL9:0 Phase Lock Loop High Register (PLLH) Reset Value SFR F5 CLKSTAT2...
- Page 56 Extended Interrupt Priority (EIP) Reset Value SFR F8 PWDI PWDI Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt. bit 4 0 = The watchdog interrupt is low priority. 1 = The watchdog interrupt is high priority. External Interrupt 5 Priority.
- Page 57 One Microsecond Register (USEC) Reset Value SFR FB FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 FREQ5-0 Clock Frequency – 1. This value + 1 divides the system clock to create a 1µs Clock. bits 5-0 USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EF One Millisecond Low Register (MSECL) Reset Value SFR FC...
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Page 58: Packaging Information
PACKAGE OPTION ADDENDUM www.ti.com 25-Nov-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY MSC1200Y2PFBR ACTIVE TQFP 2000 MSC1200Y2PFBT ACTIVE TQFP MSC1200Y3PFBR ACTIVE TQFP 2000 MSC1200Y3PFBT ACTIVE TQFP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. -
Page 59: Mechanical Data
MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 0,17 0,13 NOM 5,50 TYP 7,20 Gage Plane 6,80 9,20 8,80 0,25 0,05 MIN 0 – 7 1,05 0,95 0,75 Seating Plane 0,45 0,08 1,20 MAX... - Page 60 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...
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