Page 1 MSC1210 Analog-to-Digital Converter with 8051 Microcontroller and Flash Memory User’s Guide December 2002 SBAU077...
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Page 3: Table Of Contents
Introduction to the MSC1210 ........... . .
Page 4 Contents Addressing Modes ............. . Description .
Page 5 12.13.3 Manual Shift (Divide) Mode 12.13.4 ADC Summation with Shift (Divide) Mode 12.14 Interrupt-Driven ADC Sampling 12.15 Syncronizing Multiple MSC1210 Devices 12.16 Ratiometric Measurements 12.16.1 Differential Vref ........... .
Page 6 ............15.5 Flash Memory as Data Memory 15.6 Advanced Topics and Other Information 15.6.1 Serial and Parallel Programming of the MSC1210 15.6.2 Debugging Using the MSC1210 Boot ROM Routines 15.6.3 Using MSC1210 with Raisonance Development Tools 15.6.4 Using the MSC1210 Evaluation Module (EVM)
Page 7 16 8052 Assembly Language ............16.1 Description .
Page 8 Contents Additional Features in the MSC1210 Compared to the 8052 Additional Features in the MSC1210 Compared to 8052 Clock Timing Diagram ............
Page 9 1−2. Pin Configuration of the MSC1210 1−3. MSC1210 Timing Compared to Standard 8051 Timing 2−1. MSC1210 Memory Map ............
Page 10 ............B−1. MSC1210 Timing Chain and Clock Control viii .
Page 11 1−1. Pin Descriptions of the MSC1210 2−1. Program and Data Memory Size. 2−2. Program and Data Memory Addresses. 3−1. SFR Names and Addresses. 5−1. MSC1210 Addressing Modes. 7−1. Signal Definitions for Reset Timing Diagrams 8−1. Timer Conrol SFRs............
Page 12 Contents 14−1. Typical Sub-Circuit Current Consumption 14−2. Comparator Specification ........... . . 14−3.
Page 13 This chapter describes the basic function of the MSC1210 analog-to-digital converter (ADC). Topic MSC1210 Description .........
Page 14: Msc1210 Description
8052 core. This MIPS capability allows you to optimize speed, power, and noise tradeoffs based on specific requirements. A block diagram of the MSC1210 ADC is shown in Figure 1−1. Figure 1−1. MSC1210 Block Diagram...
Page 15: Msc1210 Pin-Out
1.2 MSC1210 Pin-Out The names and functions of these pins are similar to those found on a traditional 8052 core, but the MSC1210 includes additional pin assignments to support the additional functions specific to the part. Figure 1−2. Pin Configuration of the MSC1210...
Page 16: Pin Descriptions Of The Msc1210
MSC1210 Pin-Out Table 1−1. Pin Descriptions of the MSC1210 Pin # Name Description XOUT The crystal oscillator pin XOUT supports parallel resonant AT cut crys- tals and ceramic resonators. XOUT serves as the output of the crystal amplifier. The crystal oscillator pin XIN supports parallel resonant AT cut crystals and ceramic resonators.
Page 17 Table 1−1 Pin Descriptions of the MSC1210 (Continued) Pin # Name Description 34-40, 43 P2.0-P2.7 Port 2 is a bidirectional I/O port. The alternate functions for Port 2 are listed below. Port 2—Alternate Functions: 34-40, 43 P2.0-P2.7 PORT P2.0 P2.1 P2.2...
Page 18: I/O Ports (P0, P1, P2, And P3)
1.2.1 I/O Ports (P0, P1, P2, and P3) Of the 64 pins on the MSC1210, 32 of them are dedicated to I/O lines that have a one-to-one relation with SFRs P0, P1, P2, and P3. The developer may raise and lower these lines by writing 1s or 0s to the corresponding bits in the SFRs.
Page 19 Port 1 is commonly used to interface to external hardware such as LCDs, key- pads, and other devices. As opposed to a standard 8052 core, all I/O lines of the MSC1210 serve optional alternate functions, as described below. These lines can still be used for the developing purposes, if the functions described below are not needed.
Page 20 MSC1210 Pin-Out 1.2.1.3 Port 2 Like port 0, port 2 is dual-function. In some circuit designs, it is available for access- ing external devices, while in others it is used to address external RAM or external code memory. When more than 256 bytes of external RAM are used, port 2 is used to output the high byte of the address that is to be accessed in a MOVX operation.
Page 21: Oscillator Inputs (Xtal1 And Xtal2)
1.2.2 Oscillator Inputs (XTAL1 and XTAL2) The MSC1210 is typically driven by a crystal connected to pins 1 (XOUT) and 2 (XIN). Common crystal frequencies are 11.0592MHz as well as 12MHz, al- though the MSC1210 is capable of accepting frequencies as high as 33MHz.
Page 22: Reset Line (Rst)
IC (such as the 74HC573), and then placing the 8 data bits on port 0. In this way, the MSC1210 is able to output a 16-bit address and an 8-bit data word with 16 I/O lines instead of 24.
Page 23: External Access (Ea)
External Access (EA) The external access (EA) line at pin 48 is used to determine whether the MSC1210 will execute your program from external code memory or from inter- nal code memory. If EA is tied high (connected to supply), the microcontroller will execute the program it finds in internal/on-chip code memory.
Page 24: Enhanced 8051 Core
Figure 1−3. MSC1210 Timing Compared to Standard 8051 Timing The timing of software loops is faster with the MSC1210 than with the standard 8052. However, the timer/counter operation of the MSC1210 may be maintained at 12 clocks per increment or optionally run at 4 clocks per increment.
Page 25: Family Device Compatibility
Code written for the 4K bytes program memory version of the MSC1210 can be exe- cuted directly on the 8K, 16K, or 32K versions. This allows you to add or delete software functions and to freely migrate between family members.
Page 26: High-Performance Peripherals
High-Performance Peripherals 1.7 High-Performance Peripherals High-performance peripherals are included on-chip, which offload CPU proc- essing and control functions from the core to further improve the overall device efficiency and throughput. On-chip peripherals include additional SRAM, a 32-bit accumulator, an SPI-compatible serial port with a FIFO buffer, dual USARTs, on-chip power-on reset, brownout reset, low-voltage detect, multiple digital ports with configurable I/O, a 16-bit pulse width modulator (PWM), a watchdog timer, and three timer/counters.
Page 27: Msc1210 Memory Organization
This chapter defines the Memory Organization of MSC1210 ADC. Topic Description ...........
Page 28: Description
The MSC1210 family offers a maximum of 32k of on-chip flash program memory. The exact amount of on-chip program memory depends on the spe- cific MSC1210 version selected and how the flash memory of that chip has been partitioned between program and data memory. Figure 2−1 illustrates how the flash memory may be distributed between these two types of memory.
Page 29: Program And Data Memory Size
For example, in the Y5 model there is 32k flash memory available. This 32k may be configured as either program memory, data memory, or both. This con- figuration is set at the moment the firmware is loaded onto the MSC1210 by setting hardware configuration register HCR0 as per Table 2−1. This table in- dicates the total amount of program and data memory available for each part revision given a specific HCR0 setting.
Page 30: On-Chip Extended Static Ram (Sram)
64k due to limitations of the 8052 architecture. Note: MSC1210 programs are limited to 64k because code memory is restricted to 64k. Some compilers offer ways to get around this limit when used with specially wired hardware. However, without such special compilers and hardware, pro- grams are limited to 64k.
Page 31: On-Chip Flash Data Memory
All of the parts in the MSC1210 family come with some amount of on-chip flash memory, ranging from 4k for the MSC1210Y2 all the way up to 32k for the MSC1210Y5.
Page 32: Internal Ram
Figure 2−2. MSC1210 Memory Map Register Bank. 2.4 Internal RAM As shown in Figure 2−2, the MSC1210 has a bank of 256 bytes of internal RAM. This internal RAM is found on-chip within the IC, so it is the fastest RAM available and is also the most flexible in terms of reading, writing, and modify- ing its contents.
Page 33: Register Banks
The stack is a “last in, first out” (LIFO) storage area that exists in internal RAM. It is used by the MSC1210 to store values that the user program manually pushes onto the stack, as well as to store the return addresses for CALLs and interrupt service routines (ISRs)—more on these topics later.
Page 34: Bit Memory
Internal RAM But watch out! As the memory map shows, the MSC1210 has four distinct register banks. When the MSC1210 is first reset, register bank 0 (addresses 00 ) is used by default. However, the MSC1210 may be instructed to use one of the alternate register banks (i.e., register banks 1, 2, or 3).
Page 35 As shown, bit memory is not really a new type of memory, it is just a subset of internal RAM. However, because the MSC1210 provides special instructions to access these 16 bytes of memory on a bit-by-bit basis, it is useful to think of it as a separate type of memory.
Page 36: Special Function Register (Sfr) Memory
For example, four SFRs permit access to the 32 input/output lines (eight lines per SFR) of the MSC1210. Another SFR allows a program to read or write to the MSC1210 serial port. Other SFRs allow the user to set the serial baud rate, control and access timers, and configure the MSC1210 interrupt system.
Page 37: Special Function Registers (Sfrs)
Chapter 3 defines the MSC1210 SFRs. Topic Description ...........
Page 38: Description
Description 3.1 Description The MSC1210 is a flexible microcontroller with a relatively large number of modes of operation. Your program may inspect and/or change the operating mode of the MSC1210 by manipulating the values of its SFRs. SFRs are accessed as if they were normal internal RAM. The only difference...
Page 39: Referencing Bits Of Sfrs
SFRs sup- ported by the MSC1210. Failing to do so may result in the assembler or com- piler reporting compile errors. Please refer to the documentation for the com- piler or assembler to discover how new SFRs of the MSC1210 must be de- fined in the development platform to be used.
Page 40: Bit−Addressable Sfrs
SETB or CLR. 3.4 SFR Types Four of the SFRs are related to the I/O ports. The MSC1210 has four I/O ports of eight bits, for a total of 32 I/O lines. Whether a given I/O line is high or low, and the value read from the line, is controlled by these SFRs.
Page 41: Sfr Definitions
Note: Even though the MSC1210 has four I/O ports (P0, P1, P2, and P3), if the hardware uses external RAM or external code memory (i.e., if the program is stored in an external ROM or EPROM chip, or if external RAM chips are being used), P0 or P2 may not be used.
Page 42 These modes of operation are controlled through PCON. Additionally, one of the bits in PCON is used to double the effective baud rate of the MSC1210 primary serial port. Do not confuse it with PDCON, which controls peripheral power-down.
Page 43 8052 timing, or to fully exploit the high-speed nature of the MSC1210. This SFR allows timers 0, 1, and 2 to be clocked at a rate of 1/12th the crystal frequency (just like an 8052), or to be clocked at the rate of 1/4th the crystal frequency such that the clocks will be incremented once every in- struction cycle.
Page 44 MPAGE (Memory Page, Address 92 the address to access when using the MOVX @Ri instructions. A normal 8052 requires the high byte of the address be written to P2; the MSC1210, however, requires that the byte be written to the MPAGE SFR.
Page 45 0 will bring it to a low level. Note: Even though the MSC1210 has four I/O ports (P0, P1, P2, and P3), if the hardware uses external RAM or external code memory (i.e., the program is stored in an external ROM or EPROM chip, or if external RAM chips are being used), P0, P2, P3.6, or P3.7 may not used.
Page 46 (0) priority or high (1) priority. An interrupt may only interrupt interrupts of lower priority. For example, if we configure the MSC1210 so that all interrupts are of low priority except the serial interrupt, the serial interrupt will always be able to interrupt the system, even if another interrupt is currently executing.
Page 47 Any value written to SBUF1 will be sent out the serial port TXD1 pin. Likewise, any value that the MSC1210 receives via the serial port RXD1 pin will be delivered to the user program via SBUF1.
Page 48 FRCM controls power saving for flash memory read operations when the MSC1210 is running at a low clock frequency. It also includes a bit that indi- cates whether or not flash memory is currently idle or busy with a prior memory access operation.
Page 49 FTCON (Flash Memory Timing Control, Address EF the timing and period of flash memory, specifically for writing and erasing flash memory. The period of writing to flash memeory is determined by USEC and the low four bits of FTCON, and should produce a write period of 30 s to 40 s. Meanwhile, the period of erasing flash memory is determined by MSECH/MSECL and the high four bits of FTCON, and should produce an erase period of 4ms to 11ms.
Page 50 SFR Definitions MSINT (Milliseconds Interrupt, Address FA cause an interrupt to occur after the specified number of milliseconds. This as- sumes that the millisecond registers FC every millisecond. The precise frequency at which MSINT will cause an inter- rupt depends on the system clock and the value of the MSECH, MSECL, and MSINT SFRs.
Page 51: Basic Registers
Chapter 4 describes the basic register functions of the MSC1210 ADC. Topic Description ...........
Page 52: Description
It can hold an 8-bit (1-byte) value and is the most versatile register of the MSC1210, due to the shear num- ber of instructions that make use of the accumulator. More than half of the 255 opcodes of the MSC1210 manipulate or use the accumulator in some way.
Page 53: B Register
2, R4 is synonymous with 14 3, it is synonymous with address 1C The concept of register banks adds a great level of flexibility to the MSC1210, es- pecially when dealing with interrupts (see Chapter 10, Interrupts, for details).
Page 54: Data Pointer (Dptr0/Dptr1)
SP and then stores the value at the resulting memory location. When a value is popped off the stack, the MSC1210 returns the value from the memory location indicated by the SP, and then decrements the value of the SP.
Page 55: Addressing Modes
Chapter 5 describes the various addressing modes of the MSC1210. Topic Description ...........
Page 56: Msc1210 Addressing Modes
Description 5.1 Description As is the case with all microcomputers from the PDP-8 onwards, the MSC1210 uses several memory addressing modes. An addressing mode refers to how you are accessing (addressing) a given memory location or data value. In summary, the addressing modes are listed in Table 5−1 with an example of each.
Page 57: Direct Addressing
The obvious question that may arise is “if direct addressing an address from through FF nal RAM that are available with the MSC1210?” The answer is: it cannot be accessed using direct addressing. As stated, if an address of 80 is directly referred to, it refers to an SFR.
Page 58: Indirect Addressing
RAM that is found at the address indicated by R0. For example, suppose R0 holds the value 40 holds the value 67 the value of R0. The MSC1210 gets the value out of internal RAM address 40 (which holds 67 Thus, the accumulator ends up holding 67 Indirect addressing always refers to internal RAM;...
Page 59: External Direct Addressing
5.5 External Direct Addressing External memory is accessed using a suite of instructions that use external direct addressing. It is referred to as external direct because it appears to be direct addressing, but it is used to access external memory rather than internal memory.
Page 60: External Indirect Addressing
External Indirect Addressing 5.6 External Indirect Addressing External memory can also be accessed using a form of indirect addressing called external indirect. This form of addressing is usually only used in relative- ly small projects that have a very small amount of external RAM. An example of this addressing mode is: MOVX @R0,A Once again, the value of R0 is first read and the value of the accumulator is...
Page 61: Program Flow
Chapter 6 describes the program flow of the MSC1210 ADC. Topic Description ...........
Page 62: Description
6.2 Conditional Branching The MSC1210 contains a suite of instructions that, as a group, are referred to as “conditional branching” instructions. These instructions cause the program execution to follow a non-sequential path if a certain condition is true.
Page 63 NEW_ADDRESS: ... The LJMP instruction in this example means “Long Jump.” When the MSC1210 executes this instruction, the PC is loaded with the address of NEW_ADDRESS and program execution continues sequentially from there. The obvious difference between the Direct Jump and Call instructions and conditional branching is that with Direct Jumps and Calls, program flow always changes;...
Page 64: Interrupts
6.6 Interrupts An interrupt is a special feature that allows the MSC1210 to break from its nor- mal program flow to execute an immediate task, providing the illusion of multi- tasking. The word interrupt can often be substituted with the word event.
Page 65: System Timing
Chapter 7 describes the system timing of the MSC1210 ADC. Topic Description ...........
Page 66: Description
In order to understand—and better make use of—the MSC1210, it is neces- sary to understand some underlying information concerning timing. The MSC1210 operates with timing derived from an external crystal or a clock signal generated by some other system. A crystal is a mechanical oscillator that allows an electronic oscillator to run at a very precisely known frequency.
Page 67 Using the maximum crystal frequency of 33MHz, the crystal oscillates 33 000 000 times per second. Due to one instruction cycle being four clock cycles, the MSC1210 can execute the following number of in- struction cycles per second:...
Page 68: System Timers
The MSC1210 timers are illustrated in Figure 7−2. The SYS Clock is the signal that comes from the oscillator or other timing input. This signal is used as the input for all of the part’s timing logic, including the following timing circuits:...
Page 69: Spi/Pwm/Flash Write Timing
System Timers Figure 7−2. MSC1210 Timing Chain and Clock Control Figure 7−3. SPI/PWM/Flash Write Timing System Timing...
Page 70: Microseconds Timer
7.2.1 Microseconds Timer The microseconds timer is used by the MSC1210 in order to establish a 1 s clock. This clock, in turn, is used by flash memory to establish timing for flash writes, as well as by the PWM module.
Page 71: System Timing Interrupt Control
Figure 7−4. System Timing Interrupt Control The MSECH (FD the system clock divided by the value of these SFRs, plus one, generates a 1ms clock. For example, given a system clock of 12.000MHz, MSECH/MSECL should be set to 12 000 000 / 1000 = 12 000 – 1 = 11 999. Thus, for a 12.000MHz system clock, MSECH/MSECL should be set to 11 999 to generate a 1ms clock.
Page 72 The one hundred millisecond clock is used by the MSC1210 in order to estab- lish a 10Hz clock. This clock is not directly outputted by the MSC1210; it is used as the input into the seconds auxiliary interrupt and also is used by the watch- dog timer.
Page 73: Flash Programming Mode Power-On Reset Timing
7.3 Startup Timing When power is turned on, or a reset is initiated, a power-on delay circuit is im- plemented with a 17-bit counter to guarantee that the power supply has reached a certain level, and the oscillator is stable. The delay introduced by this counter is: 24MHz System clock: (2 1MHz System clock: (2...
Page 74: Serial Flash Programming Power-On Timing (Ea Is Ignored)
Startup Timing Figure 7−7. Serial Flash Programming Power-On Timing (EA is ignored) Table 7−1. Signal Definitions for Reset Timing Diagrams Symbol Parameter RST Width RST rise to PSEN ALE internal pull high RST falling to PSEN and ALE start Input signal to RST falling setup time RST falling to input signal hold time Notes: 1) t CLK is the Xtal clock period.
Page 75: Timers
Chapter 8 describes the timers of the MSC1210 ADC. Topic Description ...........
Page 76: How Long Does A Timer Take To Count?
33 000 000 / 4 = 8 250 000 times per second However, to maintain compatibility with existing 8052 code, the default mode for the MSC1210 timers is to increment by one every three instruction cycles (i.e., operate as if the timer increments every 12 clocks). Thus, a running timer...
Page 77 The individual bits of TMOD have the following functions: SFR 8E H T2M (bit 5)—Timer 2 Clock Select. This bit controls the division of the system clock that drives Timer 2. This bit has no effect when the timer is in baud rate generator or clock output modes.
Page 78: Timer Sfrs
8.3.2 Timer SFRs As mentioned before, the MSC1210 has three standard timers. Two of these timers work in essentially the same way. One timer is Timer 0 and the other is Timer 1. The two timers share two SFRs (TMOD and TCON) which control the timers, and each timer also has two SFRs dedicated solely to maintaining the value of the timer itself (TH0/TL0 and TH1/TL1).
Page 79: Tmod Sfr
It is apparent that the maximum value a timer may have is 65,535 because there are only two bytes devoted to the value of each timer. If a timer contains the value 65,535 and is subsequently incremented, it will reset—or overflow—back to 0. 8.3.3 TMOD SFR The TMOD SFR is used to control the mode of operation of both timers.
Page 80: Timer 0/1 Block Diagram For Modes 0 And 1
Timer mode 0 is a 13-bit timer. This is a relic that was kept around in the 8052 (and subsequently MSC1210) to maintain compatibility with its predecessor, the 8048. The 13-bit timer mode is not normally used in new development.
Page 81: Example Of 8-Bit Auto-Reload
When the timer is in 13-bit mode, TLx will count from 0 to 31. When TLx is in- cremented from 31, it will roll over to 0 and overflow into THx, thus increment- ing it. Therfore, only 13 bits of the two timer bytes are being used: bits 0 to 4 of TLx, and bits 0 to 7 of THx.
Page 82: Tcon Sfr
Using Timers to Measure Time As shown, the value of TH0 never changed. In fact, when mode 2 is used, THx is almost always set to a known value and TLx is the SFR that is constantly incremented. THx is initialized once, and then left unchanged. The benefit of auto-reload mode is that, perhaps, the timer may need to always have a value from 200 to 255.
Page 83: Initializing A Timer
So far, only four of the eight bits have been defined. That is because the other four bits of the SFR do not have anything to do with timers—they have to do with interrupts and they will be discussed in Chapter 10, Interrupts. Table 8−4 contains the bit address column because this SFR is bit-address- able.
Page 84 Using Timers to Measure Time However, when dealing with a 13-bit or 16-bit timer, the chore is a little more complicated. Consider what happens when the low byte of the timer is read as 255, then the high byte of the timer is read as 15. In this case, what actually happens is that the timer value is 14/255 (high byte 14, low byte 255) but the readout is 15/255.
Page 85: Timing The Length Of Events
It can. Simply connect the light switch to pin INT0 (P3.2) on the MSC1210 and set the bit GATE0. When GATE0 is set, Timer 0 will only run if P3.2 is high. When P3.2 is low (i.e., the light switch is off) the timer will automatically be stopped.
Page 86: Using Timers As Event Counters
8.4 Using Timers as Event Counters We have discussed how a timer can be used for the obvious purpose of keep- ing track of time. However, the MSC1210 also allows the use of timers to count events. This can be useful in many applications. For example, a sensor is placed across a road that would send a pulse every time a car passes over it.
Page 87: T2Con Sfr
(4 clock cycles). This means that if P3.4 is low, goes high, and goes back low in 3 clock cycles, it will probably not be detected by the MSC1210. This also means the MSC1210 event counter is only capable of counting events that occur at a maximum of 1/8th the rate of the crystal frequency.
Page 88: Timer 2 In Auto-Reload Mode
Using Timer 2 TR2 (bit 2)—Timer 1 Run Control. This bit enables/disables the operation of Timer 2. Halting this timer will preserve the current count in TH2, TL2. 0 = Timer 2 is halted. 1 = Timer 2 is enabled. C/T (bit 1)—Counter/Timer Select.
Page 89: Timer 2 In Capture Mode
8.5.3 Timer 2 in Capture Mode A new mode, specific to Timer 2, is called capture mode. As the name implies, this mode captures the value of Timer 2 (TH2 and TL2) into the capture SFRs (RCAP2H and RCAP2L). To put Timer 2 in capture mode, CP/RL2 (T2CON.0) and EXEN2 (T2CON.3) must be set.
Page 90: Timer 2 As A Baud Rate Generator
Using Timer 2 8.5.4 Timer 2 as a Baud Rate Generator Timer 2 can be used as a baud rate generator. This is accomplished by setting either RCLK (T2CON.5) or TCLK (T2CON.4). With Timer 1, the receive and transmit baud rate must be the same. With Timer 2, however, the user can configure the serial port to receive at one baud rate and transmit at another.
Page 91: Serial Communication
Chapter 9 describes serial communication using the MSC1210 ADC. Topic Description ...........
Page 92: Description
Description 9.1 Description The MSC1210 family has three serial port interfaces: two UARTs and one SPI. This chapter will cover the UARTs, while the SPI will be covered Chapter 13, Seri- al Peripheral Interface (SPI). One of the many powerful features of the MSC1210 is its integrated UARTs, otherwise known as universal synchronous/asynchronous receiver/transmit- ters.
Page 93: Setting The Serial Port Mode
9.2 Setting the Serial Port Mode The first thing to be done when using the MSC1210 integrated serial port is, ob- viously, to configure it. This lets you tell the MSC1210 how many data bits are needed, the baud rate to be used, and how the baud rate will be determined.
Page 94: Sm0 And Sm1 Function Definitions
Therefore, the MSC1210 lets the program know that it has shifted out the last byte by set- ting the TI bit. When the TI bit is set, the program assumes that the serial port is free and ready to send the next byte.
Page 95: Serial Mode 0: Synchronous Half-Duplex
3, the SM2 bit is a flag for multiprocessor communication. Generally, whenever a byte has been received, the MSC1210 will set the RI flag. This lets the program know that a byte has been received and that it needs to be processed.
Page 96: Serial Port 0 Mode 0 Transmit Timing—High Speed Operation
Setting the Serial Port Mode Figure 9−1. Serial Port 0 Mode 0 Transmit Timing—High Speed Operation. Figure 9−2. Serial Port Mode 0 Receive Timing—High Speed Operation. 9.2.2 Serial Mode 1: Asynchronous Full-Duplex In mode 1, serial data transfers are 10 bits long, full-duplex, and asynchronous. The transfer begins with a start bit, followed by eight bits of data (LSB first), then a stop bit.
Page 97: Serial Port Mode 1 Transmit Timing
Figure 9−3. Serial Port Mode 1 Transmit Timing. Figure 9−4. Serial Port 0 Mode 1 Receive Timing. Reception is enabled by configuring SCON0.RBN = 1. Reception of the data begins at the falling edge of start-bit detection. The RXDx pin is sampled 16 times-per-bit for any baud rate setting.
Page 98: Common Baud Rates Using Timer 1
Setting the Serial Port Mode The baud rate is adjustable and is based on either Timer 1 or Timer 2. Serial Port 0 can use either Timer 1 or Timer 2, while Serial Port 1 can use only Timer 1. On an overflow from the timer, a clock is sent to the baud clock.
Page 99: Serial Mode 2: Asynchronous Full-Duplex
The divide-by-32 is a result of the f T2CON.TCLK and T2CON.RCLK) and the Timer 2 overflow being divided by To determine the RCAP2H:RCAP2L value from a given baud rate use the equation below: RCAP2H : RCAP2L + (65536 * Table 9−3. Common Baud Rates Using Timer 2 Baud Rate 57.6k 19.2k...
Page 100: Serial Port 0 Mode 2 Receive Timing
Setting the Serial Port Mode Figure 9−6. Serial Port 0 Mode 2 Receive Timing. Transmission is initiated by any instruction that writes to SBUF. The transmis- sion begins after the first rollover of the divide-by-16 counter after the write. The SCONx.Ti_x interrupt flag is set when the stop bit has been placed on the TXDx pin.
Page 101: Serial Mode 3: Asynchronous Full-Duplex
9.2.4 Serial Mode 3: Asynchronous Full-Duplex In mode 3, serial data transfers are 11 bits, full-duplex, and asynchronous. Mode 3 is identical to mode 2, with the exception of the baud rate. The transfer begins with a start bit, followed by eight bits of data (LSB first), an additional bit of data (ninth bit), and then a stop bit.
Page 102 Setting the Serial Port Mode Reception is enabled by configuring SCON0.RBN = 1. Reception of the data begins at the falling edge of start-bit detection. The RXDx pin is sampled 16 times per bit for any baud rate setting. When the falling edge of the start bit is detected, the divide-by-16 counter used to generate the receive clock is reset to align the counter rollover with the bit boundaries.
Page 103: Setting The Serial Port Baud Rate
9.3 Setting the Serial Port Baud Rate Once the serial port mode has been configured, as explained above, the pro- gram must configure the serial port baud rate. In mode 0, the baud rate is either the clock frequency divided by 12 or the clock frequency divided by 4, depend- ing on the SM2 bit in the SCONx register.
Page 104: Baud Rate Settings For Timer 1
Setting the Serial Port Baud Rate For example, with an 11.059MHz crystal, to configure the serial port to 19 200 baud, try plugging it in the first equation: TH1 = 256 − ((Crystal / 384) / Baud) TH1 = 256 − ((11 059 000 / 384) / 19 200) TH1 = 256 −...
Page 105: Writing To The Serial Port
MSC1210 does not have a serial output buffer, you need to be sure that a char- acter is completely transmitted before trying to transmit the next character.
Page 106: Reading The Serial Port
JNB RI,$ MOV A,SBUF The first line of the above code segment waits for the MSC1210 to set the RI flag; again, the MSC1210 sets the RI flag automatically when it receives a character via the serial port. So as long as the bit is not set, the program re- peats the JNB instruction continuously.
Page 107: Interrupts
Chapter 10 describes the interrupts of the MSC1210 ADC. Topic 10.1 Description ..........
Page 108: Description
The event may be one of 21 interrupt sources such as the timers overflowing, receiving a character via the serial port, transmitting a character via the serial port, or external events. The MSC1210 may be configured so that when any of these events occur, the main program is temporarily suspended and control passed to a special section of code, which presumably would exe- cute some function related to the event that occurred.
Page 109: Events That Can Trigger Interrupts
MSC1210 will execute the code whenever it is necessary. 10.2 Events That Can Trigger Interrupts The MSC1210 can be configured so that any of the events in Table 10−1 will cause an interrupt. Table 10−1.Interrupt Sources...
Page 110 Events That Can Trigger Interrupts In other words, the MSC1210 can be configured so that any of the events in Table 10−1, ranging from a simple Timer 0 overflow to a watchdog or ADC conver- sion event, will trigger an interrupt calling the appropriate interrupt handler routines.
Page 111: Enabling Interrupts
By default, at power-up all interrupts are disabled. This means that even if, for example, the TF0 bit is set, the MSC1210 will not execute the Timer 0 interrupt. You must specify in code which interrupts you want the MSC1210 to enable.
Page 112: Polling Sequence
Polling Sequence Each of the MSC1210 interrupts has its own enable bit in one of these three SFRs. Enable a given interrupt by setting the corresponding bit. For example, to enable the Timer 1 Interrupt, execute either: MOV IE,#08h SETB ET1 Both of the previous instructions set bit 3 of IE, thus enabling the Timer 1 Inter- rupt.
Page 113: Interrupt Priorities
10.5 Interrupt Priorities The MSC1210 offers three levels of interrupt priority: highest, high, and low. By using interrupt priorities, higher priority may be assigned to certain interrupt conditions. The highest priority is reserved for the auxiliary interrupt that vec- tors through address 0033 ity and no other interrupt may be assigned that priority.
Page 114: Interrupt Triggering
Interrupt Triggering When considering interrupt priorities, the following rules apply: 1) Nothing can interrupt the highest-priority auxiliary interrupt, not even another auxiliary interrupt. 2) Only an auxiliary interrupt (highest priority) can interrupt a high-priority in- terrupt. 3) A high-priority interrupt may interrupt a low-priority interrupt. 4) A low-priority interrupt may only occur if no other interrupt is currently execut- ing.
Page 115: External Interrupts
RI flag was set, the TI flag was set, or both flags were set. Thus, your routine must check the status of these flags to determine what ac- tion is appropriate. Additionally, because the MSC1210 does not automatically clear the RI and TI flags, you must clear these bits in the interrupt handler.
Page 116 Types of Interrupts Note: Level-sensitive interrupts are not latched. If the interrupt is level-sensitive, the condition must be present until the processor can respond to it. This is most important if other interrupts are being used with a higher or equal prior- ity.
Page 117: Auxiliary Interrupts
10.8.5 Auxiliary Interrupts The auxiliary interrupt allows the MSC1210 to offer additional interrupts without requiring additional ISR vectors. A number of distinct interrupts, when enabled, all provoke the auxiliary interrupt. The ISR then examines the flags to determine which auxiliary interrupt was the source of the interrupt.
Page 118: Clearing Auxiliary Interrupts
Breakpoint interrupt To enable Auxiliary interrupts, the EICON.5 (EAI) bit must be set, which en- ables auxiliary interrupts. When so configured, the MSC1210 will be config- ured to respond to those auxiliary interrupts that are enabled in the AIE (A6 SFR.
Page 119 EICON.4 (AI) flag, but which auxiliary interrupt will be triggered in software cannot be specified. When an Auxiliary interrupt occurs, the MSC1210 will vector to the ISR at 0033 . The code of the ISR may use the Pending Auxiliary Interrupt (PAI, A5 SFR to determine which of the auxiliary interrupts provoked the actual inter- rupt.
Page 120: Ppi Bits Of Pai Sfr
SPIRCON have been received, or the number of bytes indicated by SPITCON have been transmitted. 10.8.5.3 Milliseconds/Seconds Interrupts The MSC1210 includes two additional timer interrupts that may trigger an in- terrupt at regular intervals. The milliseconds interrupt is triggered every n milliseconds, where n is the...
Page 121: Waking Up From Idle Mode
Table 10−13. EWU (C6 ) SFR Setting each of the bits in this SFR will allow the MSC1210 to wake up from idle mode when the corresponding interrupt occurs. If the corresponding bit is clear, the specified interrupt will not cause the MSC1210 to wake up from idle mode.
Page 122: Register Protection
Register Protection 10.10 Register Protection One very important rule applies to all interrupt handlers: interrupts must leave the processor in the same state as it was in when the interrupt initiated. Re- member, the idea behind interrupts is that the main program is not aware that they are executing in the background.
Page 123 PUSH R0. For example, instead of PUSH R0, execute: PUSH Reg0 ;Requires use of definition file MSC1210.INC If the MSC1210.INC definition file has not been included in the project, the reg- ister must be protected with: PUSH 00h ;Pushes R0 onto stack, if using register bank 0...
Page 124: Common Problems With Interrupts
The main program must then handle the process of interpreting the data that was stored in the temporary buffer. By minimizing the amount of time spent in an interrupt, the MSC1210 spends more time in the main program, which means additional interrupts can be handled faster when they occur.
Page 125: Pulse Width Modulator/Tone Generator
Chapter 11 describes the pulse width modulator/tone generator of the MSC1210 ADC. Topic 11.1 Description ..........
Page 126: Description
Description 11.1 Description The pulse width modulator (PWM) has two modes: one mode functions as a tone generator and the the other mode functions as a pulse width modulator. Figure 11−1. Block Diagram The PWM/tone generator is controlled and configured by a number of SFRs, the primary being the PWM Configuration (PWMCON, A1 The individual bits of PWMCON have the following functions: SFR A1 H...
Page 127: Tone Generator
The three bits that together make up TPCNTL, control the function of the PWM/ tone generator. The function of the generator is determined according to the table above. TPCNTL.0 enables or disables the PWM/tone generator. If set to ‘1’, the block will act as either a PWM or tone generator depending on the setting of TPCNTL.1.
Page 128: Tone Generator Waveforms
Tone Generator 11.2.1 Tone Generator Waveforms When TPCNTL[1:0] = 11, the output of the tone generator may be either a stair- case waveform or a square waveform depending on the configuration of TPCNTL.2. When TPCNTL.2 is 1, a staircase waveform is generated that will have three levels: DGND, tristate, and V When the TPCNTL.2 is 0, a square waveform of 50% duty cycle is generated that will have two levels: DGND and V...
Page 129: Pwm Generator
11.3 PWM Generator The PWM generator is activated when TPCNTL[1:0] = 01. This setting allows a PWM waveform to be generated automatically by the MSC1210 with charac- teristics defined by the user program. The PWM is configured based on the PWMCON SFR, the PWM Period and PWM Duty settings, and the USEC SFR setting.
Page 130: Timing Diagram Of A Pwm Waveform
PWM Generator Figure 11−5. Timing Diagram of a PWM Waveform In the timing diagram of a PWM waveform in Figure 11−5, the waveform is low for 2 ticks and high for 4 ticks. Thus, the value of PWM Period = 5 (6 ticks minus 1) and PWM Duty = 1 (2 ticks minus 1).
Page 131 This can be expressed in code as: PWMCON = 0x10; // Sel PWM Duty Register PWM = 128−1; // PWM toggle at a count of 128 PWMCON = 0x09; // Sel PWM Period access, SysClk rate, PWM mode PWM = 5 12−1; // 11.0592MHz/512=21.6KHz PWM Freq, Period=512 counts Note: The port pin used for PWM (P3.3) must be configured as either standard 8051 or CMOS output for the tone generator/PWM to function.
Page 132: Example Of Pwm Tone Generation
PWM Generator 11.3.1 Example of PWM Tone Generation Table 11−2 illustrates configuring the PWM for tone generation, and Table 11−3 explains selected statements. Table 11−2. Configuring the PWM for Tone Generation Stmt ‘C’ Source Code // PWM #include <reg1210.h> #define OneUsConst (2−1) sbit p33=p3^3;...
Page 133: Example Of Pwm Tone Generation Idling
11.3.2 Example of PWM Tone Generation Idling When PWM is idling, system requirements for the PWM output varies (idle at low or high voltage). The output of P3.3 (Tone/PWM) is internal pull-high upon power-on reset—idle high. If idle low is needed, many methods can be used to initialize P3.3 to low.
Page 134: Configuring The Pwm For Tone Generation With Pwm Idling
PWM Generator Table 11−4. Configuring the PWM for Tone Generation with PWM Idling Stmt ‘C’ Source Code // PWM #include <reg1210.h> #define OneUsConst (2−1) sbit p33=p3^3; void main(void) PDCON &= 0xED; // turn on tone gen & sys timer USEC = OneUsConst; P33 = 1;...
Page 135: Example Of Updating Pwm
11.3.3 Example of Updating PWM Both PWM Period and PWM Duty, set via the PWMHI and PWMLOW SFRs, are double-buffered. Their values are loaded to the 16-bit down counter and 16-bit PWMTemp register, respectively, when the counter expires. PWM Period and PWM Duty may be renewed anytime during a PWM cycle. The newly updated values are effective on the next PWM cycle.
Page 136 PWM Generator // PWM #include <REG1210.H> #define OneUsConst (2−1) #define CLEAR 0 #define SET sbit p33=P3^3; sbit p14=P1^4; unsigned char p,d; void pwm_isr( void) interrupt 2 //External Interrupt 1 p14=!p14; // debug PWMCON &= 0xef; // select PWMPeriod PWM=p; // Set PWMPeriod PWMCON |=0x10;...
Page 137: Analog-To-Digital Converter
Chapter 12 describes the ADC of the MSC1210. Topic 12.1 Description ..........
Page 138: Description
Description 12.1 Description The MSC1210 includes an ADC with 24-bit resolution. The ADC consists of an input multiplexer (MUX), an optional buffer, a programmable gain amplifier (PGA), and a digital filter. The architecture is described diagram in Figure 12−1. Figure 12−1. MSC1210 Architecture...
Page 139: Input Multiplexer
12.2 Input Multiplexer The MSC1210 multiplexer is more flexible than a typical ADC in that each input pin can be configured as either a positive or negative input for a given mea- surement. While other ADC parts often define input pairs, the MSC1210 defi- nes one pin as the negative input and the other as the positive input, thus pro- viding complete design freedom in this respect.
Page 140 Input Multiplexer The positive input channel and the negative input channel are selected in the ADC Multiplexer register (ADMUX, SFR D7h). The high four bits of ADMUX (bits 4 through 7) select the positive channel, while the low four bits (bits 0 through 3) select the negative channel.
Page 141: Temperature Sensor
Fahrenheit or Kelvin using stan- dard conversion formulas. One value of The value of data. The following program is a simple example that returns the current tempera- ture as detected by the MSC1210: #include <REG1210.H> #include <stdio.h> #include <stdlib.h> #include <math.h>...
Page 142 Temperature Sensor ADCON3 =(decimation>>8) & 0x07; // MSB of decimation ADCON1 = 0x01; // bipolar, auto, self calibration, offset, gain printf (”Calibrating. . .\n”); for (k=0; k<4; k++) // Wait for Four conversions for filter to settle // after calibration while(!(AIE &...
Page 143: Burnout Current Sources
12.4 Burnout Current Sources When the Burnout bit (BOD) is set in the ADC control register (ADCON0.6), two current sources are enabled that source approximately 2 A. This allows for the detection of an open circuit (full-scale reading) or short-cir- cuit (0V differential reading) on the selected input differential pair.
Page 144: Input Buffer
1.5V below the positive rail voltage. The input impedance of the MSC1210 without the buffer is 5M /PGA. With the buffer enabled, the impedance is typically 10G , the input voltage range is re- duced, and the analog power-supply current is higher.
Page 145: Programmable Gain Amplifier (Pga)
12.7 Programmable Gain Amplifier (PGA) The Programmable Gain Amplifier (PGA) can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can actually improve the effective resolution of the ADC. For example, with a PGA of 1 on a 5V full-scale range, the ADC can resolve to 1 V.
Page 146: Offset Dac
The rate at which samples are made available to the user program running on the MSC1210 is less than that of the analog sample rate. The data output rate is determined by dividing the analog sample rate by the decimation value in the ADCON2 (low byte, SFR address: 0xDE) and ADCON3 (high byte, SFR address: 0xDF) registers.
Page 147: Calibration
12.10 Calibration The offset and gain errors in the MSC1210 ADC, or a complete measurement system, can be reduced with calibration. The calibration mode control bits in the ADCON1 register (SFR address: 0xDD) can select 5 different calibration processes. These include: internal (self) calibration of offset, gain, or both, and system calibration of offset or gain.
Page 148: Digital Filter
Digital Filter 12.11 Digital Filter The digital filter can use either the fast settling, sinc in Figure 12−4. In addition, the auto mode changes the sinc filter to the best available option after the input channel or PGA is changed. When switching to a new channel, it will use the fast settling filter for the next two conversions, the first of which should be discarded.
Page 149: Filter Frequency Responses
Digital Filter Figure 12−5. Filter Frequency Responses Analog-to-Digital Converter 12-13...
Page 150: Multiplexing Channels
Digital Filter 12.11.1 Multiplexing Channels When the input changes suddenly, it will take a certain amount of time for the output to correctly represent that new input. The amount of time required to correctly represent the new input depends on the type of filter being used. The filters are designed to settle in 1, 2 or 3 data output intervals.
Page 151: Voltage Reference
Fast Settling (dec = 1800) 12.12 Voltage Reference The voltage reference used for the MSC1210 can either be internal or external. The power-up configuration for the voltage reference is 2.5V internal. The selection for the voltage reference is made through the ADCON0 register, bits 5 (internal/external selection) and 4 (1.25V/2.5V internal reference voltage).
Page 152: Summation/Shifter Register
Summation/Shifter Register 12.13 Summation/Shifter Register The MSC1210 includes a summation/shifter register that facilitates and in- creases the efficiency of certain common summation and shifting/division func- tions, especially those related to ADC conversions. The summation register is only active when the ADC is powered up. It is a 32-bit value that is broken into four 8-bit SFRs named SUMR0 (LSB), SUMR1, SUMR2, and SUMR3 (MSB).
Page 153 SSCON1 and SSCON0 (SSCON.7 and SSCON.6, respectively) control which of the four modes the summation register will operate in. SCNT0, SCNT1, and SCNT2 (SSCON.3 through SSCON.5) are used to indi- cate how many ADC samples should be obtained and summed to the summa- tion register.
Page 154: Manual Summation Mode
In assembly language, the above solution requires just four MOV instructions for each summation, whereas the simple addition approach (which does not take advantage of the MSC1210 summation register) takes at least 8 MOV instructions and 4 ADD instructions.
Page 155: Adc Summation With Shift (Divide) Mode
12.13.3 Manual Shift (Divide) Mode The manual shift/divide mode provides a quick method of dividing the 32-bit number in the summation register by the value indicated by the SHF bits in SSCON. In assembly language terminology, this performs a 32-bit rotate right, dropping any bits shifted out of the least significant bit position.
Page 156: Interrupt-Driven Adc Sampling
12.14 Interrupt-Driven ADC Sampling A useful, power-saving technique for obtaining ADC samples includes using the power-down mode of the MSC1210 between the time that a sample is re- quested and the time that a sample is made available to the MCU. During this time, the MSC1210 may be put into power-down mode by setting PCON.1...
Page 157 ADCON2 = decimation & 0xFF; // LSB of decimation ADCON3 =(decimation>>8) & 0x07; // MSB of decimation ADCON1 = 0x01; // bipolar, auto, self calibration, offset, gain printf (”Calibrating. . .\n”); for (k=0; k<4; k++) // Wait for Four conversions for filter to settle // after calibration.
Page 158: Syncronizing Multiple Msc1210 Devices
For this explanation, we assume that one of the input port pins is defined to be the sync pin. A master device will raise the signal high when the MSC1210 should prepare for synchronization. When the MSC1210 senses the high sig- nal on the sync input, it waits for the next ADC conversion to be completed.
Page 159 == 1); // As long as Sync is high, wait. // When sync goes low, turn on ADC and continue PDCON = ~0x08; // At this point ADC is on and multiple MSC1210’s using the // same Sync signal will be in syncronization. } //main...
Page 160: Ratiometric Measurements
Ratiometric Measurements 12.16 Ratiometric Measurements Ratiometric measurements may be used to eliminate potential inaccuracy from the ADC process. Ratiometric measurements are obtained in a circuit similar to the one shown in Figure 12−6, where the same source used to drive the reference voltage (V measurements to be taken without the accuracy of the voltage of V a factor in the measurement or in potential errors because the ratio between...
Page 161: Differential Vref
Ratiometric Measurements 12.16.1 Differential V One application would be a system where the measurement and the ADC are on different grounds. Normally, you might have a voltage source that connects to a sensor, and the bottom of the sensor connects to the reference resistor. However, with two grounds, that can be different by more than 0.3V—that does not work.
Page 162 12-26...
Page 163: Serial Peripheral Interface (Spi)
Chapter 13 describes the serial peripheral interface (SPI) of the MSC1210 ADC. Topic 13.1 Description ..........
Page 164: Functional Description
Description 13.1 Description The MSC1210 includes a serial peripheral interface (SPI) module that allows simple and efficient access to SPI-compatible devices via a number of SFRs provided for that purpose. The SPI is an independent serial communications subsystem that allows the MSC1210 to communicate synchronously with SPI peripheral devices and other microprocessors.
Page 165: Spi Clock/Data Timing
Functional Description Figure 13−2. SPI Clock/Data Timing During an SPI transfer, data is simultaneously transmitted and received. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave-select line allows individual selection of a slave SPI device; slave de- vices that are not selected do not interfere with SPI bus activities.
Page 166: Clock Phase And Polarity Controls
Clock Phase and Polarity Controls 13.3 Clock Phase and Polarity Controls Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI control register (SPICON 9A specified by the CPOL control bit, which selects an active high or active low clock, and has no significant effect on the transfer format.
Page 167: Master In Slave Out
13.4 SPI Signals The following paragraphs contain descriptions of the four SPI signals: master in slave out (MISO), master out slave in (MOSI), serial clock (SCK), and slave select (SS). The port register for P1.4, P1.5, P1.6 and P1.7 must be set (P1 = Fx the SPI functions.
Page 168: Spi System Errors
For push-pull CMOS drivers, this contention can cause permanent damage. Care should be observed to protect against excessive currents in a multi- master system because the MSC1210 does not detect a mode fault. 13-6...
Page 169: Data Transfers
13.6 Data Transfers The transmitted and received data for SPI transfers are both double-buffered. This means that a second byte can be written for transmit before the first byte has been sent. Data that is received does not have to be read from the SPIDAT register until just before the next byte is received.
Page 170 Data Transfers The SPI Receive control register, SPIRCON (9C operation. The receive buffer can be flushed with the write only RXFLUSH bit. A flush operation changes the SPI receive pointer so that it points to the same address as the FIFO IN pointer, and clears the receive counter. The receive counter indicates the number of bytes that have been received.
Page 171: Fifo Operation
13.7 FIFO Operation Data transmitted by the SPI interface is written to the SPIDATA register. If the FIFO is enabled, it is stored in the FIFO memory. The first two bytes are immediately written to the transmit buffer, and the SPI transmit pointer is incremented.
Page 172: Spi Master Transfer In Double-Buffer Mode Using Interrupt Polling
Code Examples 13.8 Code Examples 13.8.1 SPI Master Transfer in Double-Buffer Mode using Interrupt Polling Example 13−1. SPI Master Transfer in Double-Buffer Mode using Interrupt Polling #include ”MSC1210.H” #include <Stdlib.h> char spi_tx_rx ( char tx_data ) { while((AIE&0x08)!=0x08){ } SPIDATA=tx_data;...
Page 173: Spi Master Transfer In Fifo Mode Using Interrupts
13.8.2 SPI Master Transfer in FIFO Mode using Interrupts Example 13−2. SPI Master Transfer in FIFO Mode using Interrupts #include ”MSC1210.H” void main(void) P1DDRH = 0x75; // P1.7,P1.5,P1.4=output P1.6=input PDCON &= 0xFE; // Turn on SPI power SPIRCON=0x83; // Flush RxBuf, RXlevel=4 or more SPITCON=0xAA;...
Page 174 SPI Master Transfer in FIFO Mode using Interrupts Line 11 enables the SPIRX and SPITX interrupts, after which the AI flag is cleared and the EAI flag is enabled. There is no data to transmit, so SPITXIRQ goes up and we go to the monitor_isr() routine. The SPITX IRQ went up, so the subroutine send_4_bytes is called, where the program writes to the SPIDATA register 4 times.
Page 175: Additional Msc1210 Hardware
Chapter 14 describes addtional hardware on the MSC1210 ADC. Topic 14.1 Description ..........
Page 176: Description
Description 14.1 Description The MSC1210 includes a number of special hardware features above and beyond those of a typical MCS−51 part. 14.2 Low-Voltage Detect The MSC1210 includes low voltage and brownout detection circuits for both the analog and digital supply voltages. The voltage levels at which these cir- cuits are tripped is programmable.
Page 177: Power Supply
40 A Comparator Parameters Hysteresis at 2.5V Hysteresis at 4.7V Hysteresis at Each Terminal Response Time for Slow Input Band Gap Parameters (min) 1.00V (typ) 1.22V (max) 1.50V (typ) < 16 S Additional MSC1210 Hardware Low-Voltage Detect ) 1.50V 14-3...
Page 178: Watchdog Timer
EWDR bit in the HCR0 register indicates what the watchdog will do when it is triggered: reset the MSC1210 or cause an interrupt. It does not, by itself, enable or disable the watchdog; that is done in software at execution time.
Page 179: Enabling Watchdog Timer
CSEG AT 0807EH DB 0FCH ; Value for HCR0 DB 0FFH ; Value for HCR1 When the MSC1210 is in programming/download mode, code address 807E refers to the HCR0 register and 807F This allows the values that are needed for HCR0/HCR1 to be hardcoded in the source code rather than having to set the registers manually via the downloader program.
Page 180 Watchdog Timer Although the watchdog timeout value (0x07 in the previous example) may be set at the same time as the EWDT bit is cleared, it may be changed after the fact. If the timeout value is changed after the watchdog has been enabled, the new timeout will take effect the next time the watchdog times out, or the next time the watchdog is reset (see next section).
Page 181: Resetting The Watchdog Timer
(WDTCON.5). This notifies the watchdog that your program is still operating correctly and that the watchdog timer should be reset. The following code will reset the watchdog timer and notify the MSC1210 that your program is still executing correctly: WDTCON |= 0x20;...
Page 182: Watchdog Timeout/Activation
HCR0 hardware configuration register. 14.3.5.1 Watchdog Reset In the case of a watchdog reset, the MSC1210 is reset. SFRs will assume their default values, the stack is reset, and the program starts executing again at address 0000 14.3.5.2 Watchdog Interrupt...
Page 183: Advanced Topics
Chapter 15 describes advanced topics associated with the MSC1210 ADC. Topic 15.1 Hardware Configuration ........
Page 184: Hardware Configuration Registers
MSC1210. When loading a program on the MSC1210, the HCR0 register is at code ad- dress 807E sembly language program, the HCR0 and HCR1 registers could be set by add- ing the following code to the program: CSEG AT 0807EH ;Address of HCR0...
Page 185 This bit functions the same as the PML bit, but applies to only the first 4k of flash program memory. If the MSC1210 is configured such that only 4k is assigned to flash program memory, this bit has the same effect as setting PML.
Page 186 Hardware Configuration 15.1.1.2 Hardware Configuration Register 1 (HCR1) Hardware configuration register 1 (HCR1) is used primarily to configure the brownout detection for both the digital and analog power supplies. It is also used to configure whether ports 0, 2, and 3 are used as general I/O ports, or take part in external memory access.
Page 187: Accessing Configuration Memory In A User Program
You may not write to the CADDR SFR if the code is executing from flash memory. This is because that would imply that the MSC1210 fetch the flash configuration memory at the same time as it is fetching instructions from flash memory.
Page 188: Updating Interrupts With Reset Sector Lock
Advanced Flash Memory 15.2 Advanced Flash Memory Flash memory may be configured as data memory, program memory, or both. 15.2.1 Write Protecting Flash Program Memory Flash program memory may be protected against your program overwriting it by writing to flash memory during program execution. This provides a safeguard to the integrity of the code against intentional or accidental manipulation by your program.
Page 189: Configuring Breakpoints
15.3 Breakpoint Generator The purpose of the breakpoint block is to generate an interrupt whenever the desired program or data memory address is accessed. There are two kinds of memory accesses it can detect: Accesses to program memory (read or write) Accesses to data memory (read or write) The interrupt is handled by the interrupt controller (for details, see Chapter 10, Interrupts).
Page 190: Breakpoint Auxiliary Interrupt
When using breakpoints, notice that the actual breakpoint occurs after the se- lected address. That is because of interrupt latency on the MSC1210. It takes a few cycles for the interrupt to be recognized and serviced. During that time the processor continues for two or three more instructions, which means that the program counter will be offset from the address in the breakpoint.
Page 191: Power Optimization
Power Optimization 15.4 Power Optimization The MSC1210, like a standard 8052, has the ability to operate in a power-saving mode, known as idle mode. As the name implies, idle mode shuts down most of the energy-consuming functions of the microcontroller and idles.
Page 192: Flash Memory As Data Memory
Flash Memory as Data Memory 15.5 Flash Memory as Data Memory If so configured in HCR0, some portion of flash memory can be accessed by your application program as flash data memory. The amount of flash memory that is partitioned as flash data memory is controlled by the low 3 bits of HCR0. Please see Section 15.1.1.1, Hardware Configuration Register 0, for details.
Page 193 unsigned char i; // synchronize baud rate autobaud(); // Set the pointer to the beginning of the page to modify pFlashPage = (char xdata * ) PAGE_START; // before writing the flash, we have to initialize // the usec and msec SFRs because the flash programming // routines rely on these SFRs USEC = 12−1;...
Page 194: Using Msc1210 With Raisonance Development Tools
15.6.3 Using MSC1210 with Raisonance Development Tools In addition to the Keil toolset, which is included with he MSC1210 EVM kit, Raiso- nance provides a development toolset that may be used to develop software for the MSC1210. Further details on using the Raisonance tools with the MSC1210 are provided at http://www−s.ti.com/sc/psheets/sbaa080/sbaa080.pdf.
Page 195 Chapter 16 describes the 8052 Assembly Language. Topic 16.1 Description ............16.2 Syntax .
Page 196: Description
Description 16.1 Description Assembly language is a low-level, pseudo-English representation of the mi- crocontroller’s machine language. Each assembly language instruction has a one-to-one relation to one of the microcontroller machine-level instructions. High-level languages, such as C, Basic, Visual Basic, etc. are one or more steps above assembly language, in that no significant knowledge of the under- lying architecture is necessary.
Page 197 In summary, a typical 8052 assembly language line might appear as: MYLABEL: MOV A,#25h ;This is just a sample comment In this line, the label is MYLABEL. This means that if subsequent instructions in the program need to make reference to this instruction, they may do so by referring to MYLABEL, rather than the memory address of the instruction.
Page 198: Number Bases
Number Bases 16.3 Number Bases Most assemblers are capable of accepting numeric data in a variety of number bases. Commonly supported are decimal, hexadecimal, binary, and octal. Decimal: To express a decimal number in assembly language, simply enter the number normally. Hexadecimal: To express a hexadecimal number, enter the number as a hex- adecimal value, and terminate the number with the suffix “h”.
Page 199: Order Of Precedence For Mathematical Operators
16.5 Operator Precedence Mathematical operators within an expression are subject to the following order of precedence. Operators at the same “level” are evaluated left to right. Table 16−1.Order of Precedence for Mathematical Operators Order 1 (Highest) 7 (Lowest) Note: If you have any doubts about operator precedence, it is useful to use paren- theses to force the order of evaluation that you have contemplated.
Page 200: Changing Program Flow (Ljmp, Sjmp, Ajmp)
Changing Program Flow (LJMP, SJMP, AJMP) 16.7 Changing Program Flow (LJMP, SJMP, AJMP) LJMP, SJMP and AJMP are used as a go to in assembly language. They cause program execution to continue at the address or label they specify. For exam- ple: LJMP LABEL3 LJMP 2400h...
Page 201: Subroutines (Lcall, Acall, Ret)
16.8 Subroutines (LCALL, ACALL, RET) As in other languages, 8052 assembly language permits the use of subrou- tines. A subroutine is a section of code that is called by a program, does a task, and then returns to the instruction immediately following that of the instruction that made the call.
Page 202: Register Assignment (Mov)
Register Assignment (MOV) Note: Recursive subroutines (subroutines that call themselves) are a very popular method of solving some common programming problems. However, unless you know for certain that the subroutine will call itself a certain number of times, it is generally not possible to use subroutine recursion in 8052 assem- bly language.
Page 203 As already mentioned, the MOV instruction is one of the most common and vital instructions that an 8052 assembly language programmer uses. The pro- spective assembly language programmer must fully master the MOV instruc- tion. This may seem simple, but it requires knowing all of the permutations of the MOV instruction and knowing when to use them.
Page 204 Register Assignment (MOV) With this knowledge of the MOV instruction, some simple memory assignment tasks can be performed: 1) Clear the contents of Internal RAM address FF MOV A,#00h MOV R0,#0FFh ;Move the value FFh to R0 (R0=0FFh) MOV @R0,A 2) Clear the contents of Internal RAM address FF MOV R0,#0FFh ;Move the value FFh to R0 (R0=0FFh) MOV @R0,#00h ;Move 00h to @R0 (FFh), clearing contents of FFh...
Page 205: Incrementingand Decrementing Registers (Inc, Dec)
16.10 Incrementing and Decrementing Registers (INC, DEC) Two instructions, INC and DEC, can be used to increment or decrement the value of a register, internal RAM, or SFR by 1. These instructions are rather self-explanatory. The INC instruction will add 1 to the current value of the specified register. If the current value is 255, it will overflow back to 0.
Page 206: Program Loops (Djnz)
Program Loops (DJNZ) 16.11 Program Loops (DJNZ) Many operations are conducted within finite loops. That is, a given code seg- ment is executed repeatedly until a given condition is met. A common type of loop is a simple counter loop. This is a code segment that is executed a certain number of times and then finishes.
Page 207: Setting, Clearing And Moving Bits (Setb, Clr, Cpl, Mov)
16.12 Setting, Clearing, and Moving Bits (SETB, CLR, CPL, MOV) One very powerful feature of the 8052 architecture is its ability to manipulate in- dividual bits on a bit-by-bit basis. As mentioned earlier in this document, there are 128 numbered bits (00 gram as bit variables.
Page 208 Setting, Clearing, and Moving Bits (SETB, CLR, CPL, MOV) Finally, the SETB TR1 example shows a typical use of SETB to set an individu- al bit of an SFR. In this case, TR1 is TCON.6 (bit 6 of TCON SFR, SFR address ).
Page 209: Bit-Based Decisions And Branching (Jb, Jbc, Jnb, Jc, Jnc)
16.13 Bit-Based Decisions and Branching (JB, JBC, JNB, JC, JNC) It is often useful, especially in microcontroller applications, to execute different code based on whether or not a given bit is set or cleared. The 8052 instruction set offers five instructions that do precisely that. JB means jump if bit set.
Page 210: Value Comparison (Cjne)
Value Comparison (CJNE) 16.14 Value Comparison (CJNE) CJNE (compare, jump if not equal) is a very important instruction. It is used to compare the value of a register to another value and branch to a label based on whether or not the values are the same. This is a very common way of building a switch case decision structure or an IF THEN ELSE structure in assembly language.
Page 211: Less Than And Greater Than Comparison (Cjne)
Code structures similar to the one shown previously are very common in 8052 assembly language programs to execute certain code or subroutines based on the value of some register, in this case the accumulator. 16.15 Less Than and Greater Than Comparison (CJNE) Often it is necessary not to check whether a register is or is not certain value, but rather to determine whether a register is greater than or less than another register or value.
Page 212: Zero And Nonzero Decisions (Jz, Jnz)
Zero and Non-Zero Decisions (JZ/JNZ) 16.16 Zero and Non-Zero Decisions (JZ/JNZ) Sometimes, it is useful to be able to simply determine if the accumulator holds a zero or not. This could be done with a CJNE instruction, but because these types of tests are so common in software, the 8052 instruction set provides two instructions for this purpose: JZ and JNZ.
Page 213 This code assumes that a 16-bit number is in Internal RAM address 30 byte) and address 31 (low byte). The code will add 1045 ing the result in addresses 32 (high byte) and 33 MOV A,31h ;Move value from IRAM address 31h (low byte) to ;accumulator ADD A,#45h ;Add 45h to the accumulator (45h is low...
Page 214: Performing Subtractions (Subb)
Performing Subtractions (SUBB) 16.18 Performing Subtractions (SUBB) The SUBB instruction provides a way to perform 8-bit subtraction. All subtrac- tion involves subtracting some number or register from the accumulator and leaving the result in the accumulator. The original value in the accumulator is always overwritten with the result of the subtraction.
Page 215: Performing Multiplication (Mul)
16.19 Performing Multiplication (MUL) In addition to addition and subtraction, the 8052 also offers the MUL AB in- struction to multiply two 8-bit values. Unlike addition and subtraction, the MUL AB instruction always multiplies the contents of the accumulator by the con- tents of the B register (SFR F0 and B, placing the low byte of the result in the accumulator and the high byte of the result in B.
Page 216: Performing Division (Div)
Performing Division (DIV) 16.20 Performing Division (DIV) The last of the basic mathematics functions offered by the 8052 is the DIV AB instruction. This instruction, as the name implies, divides the accumulator by the value held in the B register. Like the MUL instruction, this instruction always uses the accumulator and B registers.
Page 217: Rotate Operations
16.21 Shifting Bits (RR, RRC, RL, RLC) The 8052 offers four instructions that are used to shift the bits in the accumulator to the left or right by one bit: RR A, RRC A, RL A, RLC A. There are two instruc- tions that shift bits to the right, RR A and RRC A, and two that shift bits to the left, RL A and RLC A.
Page 218: Results Of Anl
Bit-Wise Logical Instructions (ANL, ORL, XRL) 16.22 Bit-Wise Logical Instructions (ANL, ORL, XRL) The 8052 instruction set offers three instructions to perform the three most common types of bit-level logic: logical AND (ANL), logical OR (ORL), and log- ical exclusive OR (XRL). These instructions are capable of operating on the accumulator or an internal RAM address.
Page 219 Bit-Wise Logical Instructions (ANL, ORL, XRL) Most of the logical bit-wise instructions affect entire 8-bit memory registers. However, the following instructions are available to perform logical operations on the carry bit. The result of these instructions is always left in the carry bit and the other bit is left unchanged.
Page 220: Exchanging Register Values (Xch)
Exchanging Register Values (XCH) 16.23 Exchanging Register Values (XCH) Very often, the value of the accumulator will need to be swapped with the value of another SFR or internal RAM address. The XCH instruction allows this to be done quickly and without using additional temporary holding variables. XCH will take the value of the accumulator and write it to the specified SFR or internal RAM address, while at the same time writing the original value of that SFR or internal RAM address to the accumulator.
Page 221: Adjusting Accumulator For Bcd Addition (Da)
Adjusting Accumulator for BCD Addition (DA) 16.26 Adjusting Accumulator for BCD Addition (DA) DA A is a very useful instruction if you are doing BCD-encoded addition. BCD stands for binary coded decimal, and is a form of expressing two decimal digits in a single 8-bit byte.
Page 222: Using The Stack (Push/Pop)
Using the Stack (PUSH/POP) 16.27 Using the Stack (PUSH/POP) The stack, as with any processor, is an area of memory that can be used to store information temporarily, including the return address for returning from subroutines that are called by ACALL or LCALL. The 8052 automatically handles the stack when making an ACALL or LCALL, as well as when returning with the RET instruc- tion.
Page 223 The stack itself resides in internal RAM and is managed by the SP (stack point- er) SFR. SP will always point to the internal RAM address from which the next POP instruction should obtain the data. POP will return the value of the internal RAM address pointed to by SP, then decrement SP by 1.
Page 224: Setting The Data Pointer Dptr (Mov Dptr)
Setting the Data Pointer DPTR (MOV DPTR) 16.28 Setting the Data Pointer DPTR (MOV DPTR) The next few instructions use the data pointer (DPTR), the only 16-bit register in the 8052. DPTR is used to point to a RAM or ROM address when used with the following instructions that are explained.
Page 225: Reading And Writing External Ram/Data Memory (Movx)
16.29 Reading and Writing External RAM/Data Memory (MOVX) The 8052 generally has 128 or 256 bytes of internal RAM that is accessed with the MOV instruction, as described previously. However, many projects will re- quire more than 256 bytes of RAM. The 8052 has the ability of addressing up to 64k of external RAM in the form of additional, off-chip ICs.
Page 226: Reading Code Memory/Tables (Movc)
Reading Code Memory/Tables (MOVC) 16.30 Reading Code Memory/Tables (MOVC) It is often useful to be able to read code memory itself from within a program. This allows for the placement of data or tables in code memory to be read at run time by the program itself.
Page 227 For example, if the data in the previous example are located right after the rou- tine that read it, instead of being located at code memory 2000 tine could be changed to: SUB: INC A ;Increment accumulator to account for ;RET instruction MOVC A,@A+PC ;Get the data from the table ;Return from subroutine...
Page 228: Using Jump Tables (Jmp @A+Dptr)
Using Jump Tables (JMP @A+DPTR) 16.31 Using Jump Tables (JMP @A+DPTR) A frequent method for quickly branching to many different areas in a program is by using jump tables. For example, branching to different subroutines based on the value of the accumulator could be accomplished with the CJNE instruc- tion (which has already been covered): CJNE A,#00h,CHECK1 ;If it’s not zero, jump to CHECK1 AJMP SUB0...
Page 229: Keil Simulator
Chapter 17 describes the Keil simulator and its functions. Topic 17.1 Description ..........17.2 Timers .
Page 230: Description
MSC1210 peripherals. Some of the pe- ripherals available on the simulator are common to the standard 8051 device, whereas the others are specific to the MSC1210. Following is a list of the MSC1210 simulated peripherals:...
Page 231 3) There are also some labeled check boxes whose statuses, checked or cleared, directly affect the associated bit within the respective bit pattern of the SFR. A checked status on a check box item represents a logic 1, while a cleared status on a check box item represents a logic 0. Converse- ly, the current status of the corresponding bit within the associated bit pat- tern of the SFR is reflected in the pertinent check box.
Page 232: Timer/Counter 0 − Mode 2
Timers 17.2 Timers The simulator peripheral timer has three timer/counter modules: Timers 0, 1, and 2; a system timer module; and a watchdog module. The Timer/Counter 0 module is identical to the Timer/Counter 1, so we shall only describe the opera- tions of Timer/Counter 0.
Page 233: Timer 0 & 1 Example
Due to the MSC1210 peripherals being modular and relatively independent, even if they share registers, each peripheral has it own unique set of bits that are associ- ated and affiliated with it. For instance, referring to the Chapter 8, Timers, the status and setup bits for both Timer/Counter 0 and Timer/Counter 1 occupy separate bit positions within the same TCON SFR.
Page 234: Timer/Counter 1 Mode 1
Timers Figure 17−4. Timer/Counter 1 Mode 1 Figure 17−5. Interrupt System 17-6...
Page 235 C pro- gram. There are four routines including the main ( ) program that are needed to run this program. They are described in the following paragraphs. #include ”MSC1210.h” #include <math.h> #include <stdio.h>...
Page 236 Timers void interrupt_timer0 ( ) interrupt 1 using 1 /*This ISR is called when a type 1 interrupt causes the processor to vector into the code segment address 0x0006. Register Bank 1 is used, as opposed to the default Register Bank 0.*/ IE &= 0x7f;...
Page 237 Every time the idle loop is interrupted, the MSC1210 vectors to the ISR of the interrupting signal. If the interrupt source is the Timer 0 overflow, the processor vectors to the interrupt_timer 0 ( ) ISR, where the timer_0_overflow_count vari- able is updated, and the TH0:TL0 register pair is replenished with a value of 0x0200.
Page 238 Timers end_test = 0; //Timer 0 TH0:TL0 will always count up from 0x0200 until overflow, //and will be replenished with 0x0200 indefinitely count_start = 0x200; /*Timer 0 and Timer 1 in Mode 1, timer mode, Gate 0 is closed and Gate 1 is opened.
Page 239: Timer 2
P1.T2EX, T2CON.T2, T2CON.TF2 and T2CON.EXF2 pins respectively, as discussed earlier. The values and the implications of the contents of the editable text windows T2 and RCAP2 are consistent with those of the actual device registers in the MSC1210 system. Register Bit Toggle Box Name T2CON.TR2 T2CON.C/T2...
Page 240: Watchdog Timer
1, followed by a logic 0 for their respective setting and reset- ting in the actual MSC1210 device, so do the check boxes in this simulator pe- ripheral. Please see section 14.3, Watchdog Timer, of this manual for the de- scription of the special access programming.
Page 241: Watchdog Reset Facility Example
WDRESET bit of HCR0. 17.4.1 Watchdog Reset Facility Example #include ”MSC1210.H” //unsigned char data irqen_init _at_ 0x7f ; // image of PAI #define FWVer 0x04...
Page 242 Watchdog Timer //For the actual device, the a logical AND of the content of the FRC0 SFR register with 0xF7 must be performed to Disable the Watchdog Reset so that the watchdog system can be controlled through the watchdog interrupt facility.
Page 243 /*start short loop to test DWDT*/ for (i = 0; i < 4000; i ++) {//idle delay j = (i *13) % 4000; //Disable watchdog timer before timer expires WDTIMER |= 0x40; WDTIMER &= ~0x40; //Reinitialize watchdog, sinice it has just been disabled init_watchdog ( );...
Page 244: Clock Control
System Timer 17.5 System Timer The MSC1210 device has many time ticks and an additional clock generator (1MHz) that are derived, and, therefore, synchronized to the system clock. Each time tick and clock generator has a set of registers that specify the value of system clock divisions required to generate it.
Page 245: Analog-To-Digital Converter
ADRESH, ADRESM and ADRESL, respectively, is displayed in the text display window marked ADRESH/M/L. The MSC1210 device has an input multiplexer which facilitates the selection of any combination of any pair of differential inputs. If you select any of the input channels for the positive input of the differential input pair, any other input could be selected for the negative input.
Page 246: Analog−To−Digital Converter Peripheral
Analog-to-Digital Converter Figure 17−8. Analog−to−Digital Converter Peripheral For each analog input source whose editable text windows are displayed un- der the Analog Input Channels title, one could specify the desired analog volt- ages to be converted. The Vision2 simulator also provides an alternate way for entering analog voltage values by writing a script program that runs in paral- lel with the program being executed.
Page 247: Error Message
SIGNAL void a_to_d_sim (void) inti; /*Data written into the variable ain0 is automatically entered into the editable text window labeled AIN0 in the ADC peripheral dialog.*/ ain0 = 0.5; //specify start value for ain0 //debug program idles for 196000 clock cycles, while simulation continues running in parallel*/ twatch (196000);...
Page 248: Accumulator/Shifter Peripheral
Accumulate Registers editable text window sets marked ACCR3, ACCR2 ACCR1, and ACCR0. These display windows reflect the values of the contents of the ACCR3, ACCR2, ACCR1, and ACCR0 registers in the MSC1210 device. 17-20...
Page 249: Adc/Summation/Shifter Example
Summation/Shifter The non-editable text window across from the acc count shows the current number of data samples accumulated into the summation registers for the cur- rent accumulate & shift cycle. The summation/shifter module depicted in Figure 17−10 shows that five samples had been accumulated, and the con- catenated result of the summation registers for the freeze−framed accumulate &...
Page 250 3-bit position arithmetic right shift. In other words, it com- putes the average value of eight consecutive samples. The following is the C code for the sample exercise described above: #include ”MSC1210.H” //unsigned char data irqen_init _at_ 0x7f ; // image of PAI #define CONVERT 0 char converting, averaging;...
Page 251 to a LONG integer*/ long j; j = ACR3; j <<= 8; j += ACR2; j <<= 8; j += ACR1; j <<= 8; j += ACR0; return (j); long read_a_to_d_result () long j; /*Convert A/D Conversion results from the ADRESH:ADRESM:ADRESL register string to a LONG integer ith sign extension*/ j = ADRESH;...
Page 252 Summation/Shifter while(!(AISTAT & 0x20)); j = ADRESL; for (i = 0; i < 20; i++) { // dump 20 conversions /*wait for DRBY bit*/ while(!(AISTAT & 0x20)); /*set up Summation / Shifter*/ /*Select Summation / Shifter option, Acc Count = 8, Shift Count = 8 init_accumulator ();...
Page 253 char accum_count; long l; float voltage_value, vref, max_range; char convert_accumulate; convert_accumulate = 1; //Select data averaging option. CKCON &= 0xf8; // 0 MOVX cycle stretch //set Serial # 1 indow up for output display setport (); printf (”\nMSC1210 Ver:”); printf (”\nA/D Res H/M/L\t”); printf (”Acc Reg 3/2/1/0\n”);...
Page 254 Summation/Shifter switch (convert_accumulate) case CONVERT: //straight A/D conversion results, no averaging PAI = 0x20; for (i = 0; i < 0x40; i++) converting = 1; /*straight conversion idle loop. Value of ”converting” is changed in the a_to_d_accumulate () ISR which is called at the end of each conversion.*/ while (converting);...
Page 255 In order to demonstrate how the summation/shifter handles the incremental accumulation of sampled data, we have opted to enable both the ADC conversion interrupt enable, EADC, and the summation interrupt enable, ESUM, by assigning a value of 0x60 to the PIREG SFR. This implies that the power fail interrupt, AI, is pulsed each time the ADC completes a sample conversion on ADC, and each time the number of accumulation matches the acc_count value on SUM.
Page 256: The Adc Peripheral Mid-Stride A Typical 8-Sample Averaging Block
Summation/Shifter Figure 17−11. summation/Shifter Peripheral Figure 17−12. The ADC Peripheral Mid-Stride a Typical 8-Sample Averaging Block 17-28...
Page 257 In addition to the previous sample code, a sample driving code for the debugging is included below. This is a special feature of the Vision2 Simulator system that allows you to send input voltage values to the editable analog text fields in the ADC peripheral module.
Page 258: List Box For The Interrupt Peripheral
Interrupts 17.9 Interrupts The list box for the interrupt peripheral is shown in Figure 17−13. The figure shows a list of interrupt sources along with their associated vector addresses that the processor automatically vectors to in the event that an enabled inter- rupt is triggered, there are no pending interrupt requests of higher priority, and there is no ISR being executed pertaining to an interrupt source of higher prior- ity.
Page 259: Parallel Port 0 Contents Display Window
17.10 Ports There are four parallel I/O ports on this device, Port 0, Port 1, Port 2 and Port 3, and as such, there are four separate parallel port displays. We shall discuss the operation of just one I/O port display because all four of them are similar. The Parallel Port 0 shown in Figure 17−14 depicts the value and the bit pattern of the contents on the Port 0 register (P0), the Port 0 Data Direction High register P0DDRH, and the Port 0 Data Direction Low register P0DDRL.
Page 260: Spi Peripheral Window
The serial peripheral interface (SPI) implemented in this simulator package mimics the behavior and characteristics of a data memory access (DMA) SPI module, integrated into the MSC1210. The MSC1210 SPI module is an en- hanced version of the popular SPI modules implemented by other manufactur- ers.
Page 261 Serial Peripheral Interface (SPI) data displayed in the SPICON window, on the basis of the bit position of the corresponding configuration bit within the SFR bit pattern. Likewise, changing the clock rate divide by value changes the SPICON entry accordingly. The re- sult of the oscillator frequency divided by the selected divide by factor is dis- played in the non-editable master clock window.
Page 262: Spi Sample Code
Serial Peripheral Interface (SPI) and the TXIRQ window determine the check/clear status of the SPIT check box. As data is being received from the external device, the value of the re- ceived data will be momentarily displayed in the SPIDATA window, and the content of SPIRCON window is properly updated.
Page 263 #include ”MSC1210.H” //unsigned char data irqen_init _at_ 0x7f ; // image of PAI #define FWVer 0x04 #define CONVERT 0 char received_data[50]; void init_spi (); void transmit_receive ();// interrupt 6; void test_spi (); void test_spi () SPIDATA = 55; while (1);...
Page 264 Serial Peripheral Interface (SPI) SPIEND = 0x0b0; /*Master mode: set MISO for input, and MOSI, SS & SCK for strong outputs*/ P1DDRH = 0x75; P1 |= 0xF0; /*enable SPI interrupt*/ PIREG |= 0x0c; IE |= 0x80; EPFI = 1; void transmit_receive () interrupt 6 using 1 /*This is a type 6 interrupt (AI).
Page 265 if (AISTAT & 0x04) {/*Receiver*/ i = SPIRCON & 0x7F; //extract the count for the number of AISTAT &= ~0x04; //deactivate SPI receive flag if (l >= 50) /*do not exceed the 50 received_data[] array limit*/ for (l = 0; l < 5; l++) printf (”\n”);...
Page 266: Mvision 2 Debug Program Example
mVision 2 Debug Program Example 17.12 Vision 2 Debug Program Example SIGNAL void spi_sim (void) /*This program runs in parallel with the main program. It sends out a character byte whose value is post incremented at the end of each associated time lapse. SPI_IN is the portal through which the byte data is sent to the main program.
Page 267: Keil Debugger
Figure 17−17. Keil Debugger The window labeled Serial #1 shows the printed ASCII character representation of the data bytes received by the main SPI program from the debugging pro- gram. Note that the first character printer is an ! mark which has a numerical val- ue of 0x21.
Page 268: Serial Port I/O
Serial Port I/O 17.13 Serial Port I/O In addition to the SPI communication protocol that was presented earlier in this manual, the more basic serial port I/O was also implemented in this simulator. Serial Ports 0 and 1 are simulated in this package. An example of this commu- nication protocol has been used a couple of times in this section of the manual.
Page 269: Serial Channel 0 Communication Peripheral
A snapshot of the Serial Channel 0 communication peripheral after at typical show_baud_gen ( ) subroutines execution is shown in Figure 17−18. Figure 17−18. Serial Channel 0 Communication Peripheral The statuses of the transmit and/or receive flags are also reflected in the conditions of the TI_0 and RI_0 check boxes.
Page 270: Serial Port 0 Operation Mode 1 Example
Serial Port I/O 17.13.1 Serial Port 0 Operation Mode 1 Example void show_baud_gen (void) P3DDRL &= 0xf0; P3DDRL |= 0x07; //P30 input, P31 output TF2 = CLEAR; T2 = CLEAR; CKCON |= 0x30; // Set timer 2 to clk/4 RCAP2 = 0xFF16; //37500 bps THL2=0xFFFF;...
Page 271: Transmit Block Baud Rate Computation
17.13.2 Transmit Block Baud Rate Computation In this example, two different baud rate sources have been used, one for re- ceive, Timer 1 overflow, and the other for transmit, Timer 2 overflow. Of course, there is no good reason for this, except to show that it could be done, and to show how to use different timer modes for baud rate generation.
Page 272: Receive Block Baud Rate Computation
Serial Port I/O 17.13.3 Receive Block Baud Rate Computation Timer 1 is set for a mode 2 timer operation in an 8-bit auto-reload capacity. This is achieved by assigning a 0x20 value to the TMOD SFR. Recall that the SMOD0 bit of PCON has been set in an earlier section of this program. This effectively doubles the communication baud rate.
Page 273: Clock Control Peripheral
Serial Port I/O Figure 17−19. Clock Control Peripheral Figure 17−20. USART0 Preipheral Keil Simulator 17-45...
Page 274: Additional Resource
Additional Resource 17.14 Additional Resource It is highly recommended that you review the Keil Compiler tutorial integrated into this package for an animated demonstration of some useful IDE facilities. 17-46...
Page 275 Appendix A Appendix A deals with additional features found in the MSC1210 as compared to the 8052. Topic Page Addtional Features in the MSC1210 Compared to the 8052 ..Additional Features in the MSC1210 Compared to the 8052...
Page 276 Additional Features in the MSC1210 Compared to 8052 A.1 Additional Features in the MSC1210 Compared to 8052 The MSC1210 includes the following features in addition to those that are in- cluded in a standard 8052 microcontroller. Flash memory, up to 32k partitionable as program and/or data memory.
Page 277: B.1 Msc1210 Timing Chain And Clock Control Diagram
Appendix B Appendix B diagrams the MSC1210 ADC timing chain and clock control. Topic Page MSC1210 Timing Chain and Clock Control Diagram ....Clock Timing Diagram...
Page 278 MSC1210 Timing Chain and Clock Control Diagram B.1 MSC1210 Timing Chain and Clock Control Diagram Figure B−1.MSC1210 Timing Chain and Clock Control...
Page 279: C Boot Rom Routines
Appendix C Appendix C defines the MSC1210 ADC boot ROM routines. Topic Page Description ...........
Page 280: C−1. Boot Rom Routines
Description C.1 Description The MSC1210 has a 2K ROM. This code provides the interaction for serial and parallel programming. There are also several routines that are useful and nec- essary for use with user applications. For example, when writing to flash memory, the code cannot execute out of flash memory.
Page 281: C.1.1 Note Regarding The Put_String Function
C parameters are passed to the subroutine code such that the first parameter is passed in R7, whereas additional parameters use lower R registers (R7 first, then R6, R5, etc.). In the case of multibyte parameters, the low byte uses the next available R register while the high byte uses the lower R register.
Page 283: D.1 8052 Instruction-Set Quick-Reference Guide
Appendix D Appendix D gives a list of the 8052 instruction set. Topic Page 8052 Instruction-Set Quick-Reference Guide ....8052 Instruction-Set Quick-Reference Guide...
Page 284 8052 Instruction-Set Quick-Reference Guide D.1 8052 Instruction-Set Quick-Reference Guide JC relAddr AJMP pg0Addr AJMP pg2Addr LJMP addr16 ORL direct,A RR A ORL direct,#data8 INC A ORL A,#data8 INC direct ORL A,direct INC @R0 ORL A,@R0 INC @R1 ORL A,@R1 INC R0 ORL A,R0 INC R1 ORL A,R1...
Page 285: E 8052 Instruction Set
Appendix E lists the 8052 instruction set. Topic Description ........... 8052 Instruction Set .
Page 286: E.1 Description
Description E.1 Description This appendix is a reference for all instructions in the 8052 instruction set. For each instruction, the following information is provided: Instruction—indicates the correct syntax for the given opcode. OpCode—the operation code, in the range of 0x00 through 0xFF, that rep- resents the given instruction in machine code.
Page 287: E.2 8052 Instruction Set
E.2 8052 Instruction Set ACALL Absolute Call within 2k Block Syntax ACALL codeAddress Instructions ACALL pg0Addr ACALL pg1Addr ACALL pg2Addr ACALL pg3Addr ACALL pg4Addr ACALL pg5Addr ACALL pg6Addr ACALL pg7Addr ACALL unconditionally calls a subroutine at the indicated code address. ACALL pushes the address of the instruction that follows ACALL onto the stack, least significant byte first, and most significant byte second.
Page 288 8052 Instruction Set ADD, ADDC Add Value, Add Value with Carry Syntax ADD A,operand ADDC A,operand Instructions ADD A,#data8 ADD A,direct ADD A,@R0 ADD A,@R1 ADD A,R0 ADD A,R1 ADD A,R2 ADD A,R3 ADD A,R4 ADD A,R5 ADD A,R6 ADD A,R7 ADDC A,#data8 ADDC A,direct ADDC A,@R0...
Page 289 The auxillary carry (AC) bit is set if there is a carry-out of bit 3. In other words, if the unsigned summed value of the low nibble of the accumulator, operand, and (in the case of ADDC) the carry flag exceeds 15, the auxillary carry flag is set.
Page 290 8052 Instruction Set Bitwise AND Syntax ANL operand1,operand2 Instructions ANL direct,A ANL direct,#data8 ANL A,#data8 ANL A,direct ANL A,@R0 ANL A,@R1 ANL A,R0 ANL A,R1 ANL A,R2 ANL A,R3 ANL A,R4 ANL A,R5 ANL A,R6 ANL A,R7 ANL C,bitAddr ANL C,/bitAddr ANL does a bitwise AND operation between operand1 and operand2, leaving the resulting value in operand1.
Page 291 CJNE Compare and Jump if Not Equal Syntax CJNE operand1,operand2,reladdr Instructions CJNE A,#data8,reladdr CJNE A,direct,reladdr CJNE @R0,#data8,reladdr CJNE @R1,#data8,reladdr CJNE R0,#data8,reladdr CJNE R1,#data8,reladdr CJNE R2,#data8,reladdr CJNE R3,#data8,reladdr CJNE R4,#data8,reladdr CJNE R5,#data8,reladdr CJNE R6,#data8,reladdr CJNE R7,#data8,reladdr CJNE compares the value of operand1 and operand2 and branches to the indicated relative address if the two operands are not equal.
Page 292 8052 Instruction Set Complement Register Syntax CPL operand Instructions CPL A CPL C CPL bitAddr CPL complements operand, leaving the result in operand. If operand is a single bit, the state of the bit is reversed. If operand is the accumulator, all the bits in the accumulator are reversed.
Page 293 Decrement Register Syntax DEC register Instructions DEC A DEC direct DEC @R0 DEC @R1 DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 DEC decrements the value of register by 1. If the initial value of register is 0, decrementing the value causes it to reset to 255 (0xFF Note: The carry flag is not set when the value rolls over from 0 to 255.
Page 294 8052 Instruction Set DJNZ Decrement and Jump if Not Zero Syntax DJNZ register,relAddr Instructions DJNZ direct,relAddr DJNZ R0,relAddr DJNZ R1,relAddr DJNZ R2,relAddr DJNZ R3,relAddr DJNZ R4,relAddr DJNZ R5,relAddr DJNZ R6,relAddr DJNZ R7,relAddr DJNZ decrements the value of register by 1. If the initial value of register is 0, decrementing the value causes it to reset to 255 (0xFF register is not 0, the program branchs to the address indicated by relAddr.
Page 295 Increment Reister Syntax INC register Instructions INC A INC direct INC @R0 INC @R1 INC R0 INC R1 INC R2 INC R3 INC R4 INC R5 INC R6 INC R7 INC DPTR INC increments the value of register by 1. If the initial value of register is 255 (0xFF ), incrementing the value causes it to reset to 0.
Page 296 8052 Instruction Set Jump if Bit Set Syntax JB bitAddr,relAddr Instructions JB bitAddr,relAddr JB branches to the address indicated by relAddr if the bit indicated by bitAddr is set. If the bit is not set, program execution continues with the instruction fol- lowing the JB instruction.
Page 297 Jump to Data Pointer + Accumulator Syntax JMP @A+DPTR Instructions JMP @A+DPTR JMP jumps unconditionally to the address represented by the sum of the value of DPTR and the value of the accumulator. See also: LJMP, AJMP, SJMP Jump if Bit Not Set Syntax JNB bitAddr,reladdr Instructions...
Page 298 8052 Instruction Set Jump if Accumulator Not Zero Syntax JNZ reladdr Instructions JNZ relAddr JNZ branches to the address indicated by relAddr if the accumulator contains any value except 0. If the value of the accumulator is zero, program execution continues with the instruction following the JNZ instruction.
Page 299 Move Memory Into/Out of Accumulator Syntax MOV operand1, operand2 Instructions MOV A,#data8 MOV A,@R0 MOV A,@R1 MOV @R0,A MOV @R1,A MOV A,R0 MOV A,R1 MOV A,R2 MOV A,R3 MOV A,R4 MOV A,R5 MOV A,R6 MOV A,R7 MOV A,direct MOV R0,A MOV R1,A MOV R2,A MOV R3,A...
Page 300 8052 Instruction Set Move into/out of Internal RAM Syntax MOV operand1,operand2 Instructions MOV @R0,#data8 MOV @R1,#data8 MOV @R0,direct MOV @R1,direct MOV R0,#data8 MOV R1,#data8 MOV R2,#data8 MOV R3,#data8 MOV R4,#data8 MOV R5,#data8 MOV R6,#data8 MOV R7,#data8 MOV R0,direct MOV R1,direct MOV R2,direct MOV R3,direct MOV R4,direct...
Page 301 MOV DPTR Move value into DPTR Syntax MOV DPTR,#data16 Instructions MOV DPTR,#data16 Sets the value of the data pointer (DPTR) to the value data16. See also: MOVX, MOVC MOVC Move Code Byte to Accumulator Syntax MOVC A,@A+register Instructions MOVC A,@A+DPTR MOVC A,@A+PC MOVC moves a byte from code memory into the accumulator.
Page 302 8052 Instruction Set Multiply Accumulator by B Syntax MUL AB Instructions MUL AB MUL multiplies the unsigned value in the accumulator by the unsigned value in the B register. The least-significant byte of the result is placed in the accumu- lator and the most-significant byte is placed in the B register.
Page 303 Bitwise OR Syntax Syntax: ORL operand1,operand2 Instructions ORL direct,A ORL direct,#data8 ORL A,#data8 ORL A,direct ORL A,@R0 ORL A,@R1 ORL A,R0 ORL A,R1 ORL A,R2 ORL A,R3 ORL A,R4 ORL A,R5 ORL A,R6 ORL A,R7 ORL C,bitAddr ORL C,/bitAddr ORL does a bitwise OR operation between operand1 and operand2, leaving the resulting value in operand1.
Page 304 8052 Instruction Set Pop Value from Stack Syntax POP register Instructions POP direct POP pops the last value placed on the stack into the direct address specified. In other words, POP will load direct with the value of the internal RAM address pointed to by the current stack pointer.
Page 305: Return From Interrupt
Return from Subroutine Syntax Instructions RET is used to return from a subroutine previously called by LCALL or ACALL. Program execution continues at the address that is calculated by POPping the top-most two bytes off the stack. The most-significant byte is POPped off the stack first, followed by the least-significant byte.
Page 306 8052 Instruction Set Rotate Accumulator Left Through Carry – Syntax RLC A Instructions RLC A RLC shifts the bits of the accumulator to the left. The left-most bit (bit 7) of the accumulator is loaded into the carry flag, and the original carry flag is loaded into bit 0 of the accumulator.
Page 307 SJMP Short Jump Syntax SJMP relAddr Instructions SJMP relAddr SJMP jumps unconditionally to the address specified relAddr. RelAddr must be within −128 or +127 bytes of the instruction that follows the SJMP instruc- tion. See also: LJMP, AJMP SUBB Subtract from Accumulator with Borrow Syntax SUBB A,operand Instructions...
Page 308 8052 Instruction Set SWAP Subtract Accumulator Nibbles Syntax SWAP A Instructions SWAP A SWAP swaps bits 0−3 of the accumulator with bits 4−7 of the accumulator. This instruction is identical to executing RR A or RL A four times. See also: RL, RLC, RR, RRC Exchange Bytes Syntax XCH A,register...
Page 309 Bitwise Exclusive OR Syntax XRL operand1,operand2 Instructions XRL direct,A XRL direct,#data8 XRL A,#data8 XRL A,direct XRL A,@R0 XRL A,@R1 XRL A,R0 XRL A,R1 XRL A,R2 XRL A,R3 XRL A,R4 XRL A,R5 XRL A,R6 XRL A,R7 XRL does a bitwise exclusive OR operation between operand1 and operand2, leaving the resulting value in operand1.
Page 310 8052 Instruction Set UNDEFINED Undefined Instruction Syntax Instructions The undefined instruction is, as the name suggests, not a documented instruc- tion. The 8052 supports 255 instructions and OpCode 0xA5 is the single op- code that is not used by any documented function. It is not recommended that it be executed because it is not documented nor defined.
Page 311 Appendix F Appendix F defines the MSC1210 bit-addressable special function registers (SFRs) in alphabetical order. Topic Page Bit-Addressable SFRs (alphabetical) ......
Page 312: F.1 Bit Addressable Sfrs (Alphabetical)
Bit Addressable SFRs (alphabetical) F.1 Bit Addressable SFRs (alphabetical) Enable Interrupt Control (EICON) SFR Name: SFR Address: Bit-Addressable: Yes Bit Definitions: bit 7 bit 6 Name SMOD1 — Bit Address DF H DE H SMOD1—Serial Port 1 Mode. 0 = Normal baud rate for serial port 1, 1 = Serial port 1 baud rate doubled.
Page 313 Extended Interrupt Priority (EIP) SFR Name: SFR Address: Bit-Addressable: Yes Bit Definitions: bit 7 bit 6 Name — — Bit Address FF H FE H PWDI—Watchdog Interrupt Priority. 1 = Watchdog interrupt high-level priority, 0 = low-level priority. PX5—External 5 Interrupt Priority. 1 = External 5 interrupt high-level priority, 0 = low-level priority.
Page 314 Bit Addressable SFRs (alphabetical) INTERRUPT PRIORITY (IP) SFR Name: SFR Address: Bit−Addressable: Yes Bit−Definitions: bit 7 bit 6 Name — — Bit Address BF H BE H PT2—Priority Timer 2 Interupt. 1 = high-priority interrupt, 0 = low-priority interrupt. PS—Priority Serial Interupt. 1 = high-priority interrupt, 0 = low-priority interrupt.
Page 315 Port 1 (P1) SFR Name: SFR Address: Bit−Addressable: Yes Bit−Definitions: bit 7 bit 6 Name P1.7 P1.6 Bit Address 97 H 96 H T2EX—Timer 2 Capture/Reload. Optional external capturing or reloading of timer 2. T2—Timer 2 External Input. Optionally used to control timer/counter 2 via external source.
Page 316 Bit Addressable SFRs (alphabetical) Port 3 (P3) SFR Name: SFR Address: Bit−Addressable: Yes Bit−Definitions: bit 7 bit 6 Name Bit Address B7 H B6 H RD—Read Strobe. 0 = external memory read strobe. WR—Write Strobe. 0 = external memory write strobe. T1—Timer/Counter 1 External Input.
Page 317: Program Status Word (Psw)
Program Status Word (PSW) SFR Name: SFR Address: Bit−Addressable: Yes Bit−Definitions: bit 7 bit 6 Name Bit Address D7 H D6 H CY—Carry Flag. Set or cleared by instructions ADD, ADDC, SUBB, MUL, and DIV. AC—Auxiliary Carry. Set or cleared by instructions ADD, ADDC. F0—Flag 0.
Page 318 Bit Addressable SFRs (alphabetical) Serial Control (SCON) SFR Name: SFR Address: Bit−Addressable: Yes Bit−Definitions: bit 7 bit 6 Name Bit Address 9F H 9E H SM0/SM1– Serial Mode. These two bits, taken together, select the serial mode in which the serial port will operate. SM2—Serial Mode 2 (Multiprocessor Communication).
Page 319 Timer Control (TCON) SFR Name: SFR Address: Bit−Addressable: Yes Bit−Definitions: bit 7 bit 6 Name Bit Address 8F H 8E H TF1—Timer 1 Overflow Flag. This bit is set by the MCU when Timer 1 overflows from FFFF automatically by hardware if a Timer 1 interrupt is triggered. TR1—Timer 1 Run Control.
Page 320 Bit Addressable SFRs (alphabetical) Timer 2 Control (T2CON) SFR Name: SFR Address: Bit−Addressable: Yes Bit−Definitions: bit 7 bit 6 Name EXF2 Bit Address CF H CE H TF2—Timer 2 Overflow Flag. This bit is set by the MCU when Timer 2 over- flows from FFFF terrupt.
Page 321: G.1 Sfr/Address Cross-Reference
Appendix G Appendix G lists an alphabetical cross-reference of the MSC1210 special function registers (SFRs) and their addresses. Topic Page G.1 SFR/Address Cross-Reference ....... . .
Page 322 SFR/Address Cross-Reference G.1 SFR/Address Cross-Reference SFR Name Description ACLK Analog Clock ADCON0 ADC Control 0 ADCON1 ADC Control 1 ADCON2 ADC Control 2 ADCON3 ADC Control 3 ADMUX ADC Multiplexer ADRESH ADC Result High ADRESL ADC Result Low ADRESM ADC Result Middle Auxiliary Interrupt Enable AISTAT Auxiliary Interrupt Status...
Page 323 MPAGE Memory Page MSECH Millisecond Counter High MSECL Millisecond Counter Low MSINT Microseconds Interrupt Memory Write Select ADC Offset Calibration High ADC Offset Calibration Low ADC Offset Calibration Middle ODAC Offset DAC Port 0 P0DDRH Port 0 Data Direction High P0DDRL Port 0 Data Direction Low Port 1...
Page 324 SFR/Address Cross-Reference SPIRCON SPI Receive Control SPISTART SPI Buffer Start Address SPITCON SPI Transmit Control SRST System Reset SSCON Summation/Shifter Control SSUMR0 Summation Register 0 SSUMR1 Summation Register 1 SSUMR2 Summation Register 2 SSUMR3 Summation Register 3 T2CON Timer 2 Control TCON Timer Control Timer 0 High...

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