ASRock Industrial IMB-1248-WV Settings Manual

IMB-1248-WV
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Multimedia Interface, and the HDMI logo are
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Licensing LLC in the United States and other
countries.
Revision History
Date Description
February 6, 2025 First Release
1 : CLRMOS2_PCIE_PWR1
Pin Signal Name
1
CLRMOS2
Open : Normal (Default)
Short : Auto Clear CMOS (Power Off)
2
PCIE_PWR1
3
(For VGA Power Card Only):
Pin3: PSON#
4
Pin4: GND
2 : Clear CMOS Header (CLRMOS1)
1-2: Normal (Default)
2-3: Clear CMOS
3 : Battery Connector (BAT1)
Pin Signal Name
1 +BAT
2 GND
4 : ESPI Header (ESPI1)
Pin Signal Name
1 GND
2 ESPI_CLK
3 GND
4 ESPI_CS#
5 ESPI_RESET#
6 GND
7 +3V
8 ESPI_CS#1
9 PLTRST#
10 COM_RST#
11 ESPI_IO0
12 ESPI_IO1
13 ESPI_IO2
14 ESPI_IO3
15 ALERT#1
16 +3VSB
17 Internal Use
18 +5VSB
19 ESPI_ALERT#
20 GND
5 : USB 3.2 Gen1 Header (USB3_3_4)
Pin Signal Name Signal Name Pin
1 DUMMY IntA_PA_D+ 2
3 IntA_PB_D+ IntA_PA_D- 4
5 IntA_PB_D- GND 6
7 GND IntA_PA_SSTX+ 8
9 IntA_PB_SSTX+ IntA_PA_SSTX- 10
11 IntA_PB_SSTX- GND 12
13 GND IntA_PA_SSRX+ 14
15 IntA_PB_SSRX+ IntA_PA_SSRX- 16
17 IntA_PB_SSRX- Vbus 18
19 Vbus 20
6 : USB 2.0 Header (USB2_7_8)
Pin Signal Name Signal Name Pin
1 USB_PWR USB_PWR 2
3 P- P- 4
5 P+ P+ 6
7 GND GND 8
9 DUMMY 10
7 : SATA Power Output Connector
(SATA_PWR1)
Pin Signal Name
1 +5V
2 GND
3 GND
4 +12V
Jumpers and Headers Setting Guide
1
1
CLRMOS2_PCIE_PWR1
USB 3.2 Gen2
45
Top: USB3_2
Bottom: USB3_1
CLRMOS1
44
LAN1
1
BAT1
43
LAN2
SATA3_5
42
USB 2.0
41
Top: USB2_6
Bottom: USB2_5
1 SATA3_4
40
Thunderbolt
39
Type-C
1
(TC_TB_1)
38
HDMI_DP_1
37
Top: DP1
Bottom: HDMI1
BUZZ1
36
35
Line Out
1
HD_AUDIO1
34
Mic In
DC_4PIN1
33 1
DC_JACK1
1
32 1
PCIE_MODE1
DC_4PIN2
31 30
8 : Digital Input/Output Default Value
Setting (JGPIO_SET1)
1-2: Pull-High (Default)
1 4
2-3: Pull-Low
9 : Digital Input/Output Pin Header (JGPIO1)
Pin Signal Name
1 GPP_E4
3 GPP_E5
5 GPP_E6
7 GPP_E7
9 JGPIOPWR_R
3 1
Parameter
GPIO input Low voltage
GPIO input High voltage
GPIO output Low voltage
GPIO output High voltage
Note:
2
Max. load per GPI/O pin: 3mA
1
Current Max. 1A per power pin
10 : COM Port Headers
COM1 (RS232/422/485)*
COM3 (RS232)
20
1
COM3 Port Pin Definition
Pin Signal Name
1 DDCD#
3 TTXD
5 GND
7 RRTS#
9 NA
* This motherboard supports RS232/422/485 on COM1 port. Please refer to the
table below for the pin definition. In addition, COM1 port (RS232/422/485) can
be adjusted in BIOS setup utility > Advanced Screen > Super IO Configuration.
You may refer to our user manual for details.
COM1 Port Pin Definition
Pin RS232
1 DCD
2 RXD
3 TXD
1 2 4 DTR
5 GND
6 DSR
7 RTS
8 CTS
9 PWR
19 20
11 : Brightness Control Mode (BLT_PWM1)
1-2: From eDP PWM to CON_LBKLT_CTL
2-3: From LVDS PWM to CON_LBKLT_CTL
2 10
(Default)
* Please set to 1-2 when adjusting brightness by
Brightness Control bar under OS.
1 9
* Please set to 2-3 when adjusting brightness by BLT_VOL1.
12 : COM Port PWR Setting Jumpers
PWR_COM1 (For COM Port1)
Open: +0V
1-2: +5V (Default)
4
2-3: +12V
1
13 : Brightness Control Mode (BLT_PWM2)
1-2 : 3V Level (Default)
2-3 : 5V Level
2 3 4 5 6 7 8 9
1
1
JGPIO_SET1
JGPIO COM3
1 ESPI1
1
USB2_7_8
1
SATA_PWR1
1
1
USB3_3_4
1
1
M2_M1
IMB-124 -WV
1
1
M2_ 1 E
TPM1
BIOS
ROM
1
SPEAKER1
1
A1
PCIE1
B1
29
3
9
Signal Name Pin
GPP_SD00 2
GPP_SD01 4
GPP_I02 6
GPP_I03 8
GND 10
10
Range
Max: 0.8V
Min: 2.4V
Max: 0.9V
Min: 2.5V
Signal Name Pin
10
RRXD 2
DDTR# 4
DDSR# 6
CCTS# 8
9
10
RS422 RS485
TX- RTX-
TX+ RTX+
RX+ NA
RX- NA
GND GND
NA NA
NA NA
NA NA
PWR PWR
3
1
3
10 11 12 13 14 15
1 1
1 16
1 1 BKT_PWR1 DACC1
1
1 1
COM1 PWR_COM1 BLT_PWM2
17
BLT_PWM1 HEATER1
DDR5_B1
18
DDR5_A1
1
19
1
1
1
20
1
C PU _FAN1
PNL _PWR 1
21
8
22
23
24
1
25
1
1
26
27
WRBTN
PLE D P
28
1
HDLE D ESET R
PANEL1
14 : Backlight Power Select
(LCD_BLT_VCC) (BKT_PWR1)
1-2: LCD_BLT_VCC: +5V (Default)
1
2-3: LCD_BLT_VCC: +12V
4-5: LCD_BLT_VCC: DC_IN
15 : DACC1
1
Open: no ACC
Short: ACC (Default)
• Auto clear CMOS when system boot improperly.
2
16 : HEATER1 Header (HEATER1)
Pin Signal Name
1 Heater PWR (5V/1A)
2 GND
NTC (Negative Temperature Coefficient)
3
thermistors)
* The 10k Ohm NTC thermistor is suggested.
* Deep mode is not supported when the preheat function is enabled.
17 : Inverter Power Control Wafer (BLT_PWR1)
Pin Signal Name
1 GND
2 GND
3 CON_LBKLT_CTL
2
4 CON_LBKLT_EN
5 LCD_BLT_VCC
6 LCD_BLT_VCC
1
18 : LVDS Panel Connector (LVDS1)
Pin Signal Name
1 LCD_VCC
3 +3.3V
5 NA LVDS_A_DATA0#
7 LVDS_A_DATA0
9 LVDS_A_DATA1#
11 GND LVDS_A_DATA2# 12
13 LVDS_A_DATA2
15 LVDS_A_DATA3#
17 GND
19 LVDS_A_CLK
21 LVDS_B_DATA0#
23 GND LVDS_B_DATA1# 24
25 LVDS_B_DATA1
27 LVDS_B_DATA2#
29 DPLVDD_EN LVDS_B_DATA3# 30
31 LVDS_B_DATA3
33 LVDS_B_CLK#
35 GND CON_LBKLT_EN
37 CON_LBKLT_CTL
39 LCD_BLT_VCC
• eDP by pass mode pin definition:
Pin Signal Name
1 LCD_VCC
3 NA
1
5 NA
7 NA
9 EDP_TX1#
11 GND
13 EDP_TX0
15 NA
17 GND
19 EDP_AUXP
21 NA
23 GND
25 NA
3
27 NA
29 DPLVDD_EN
31 NA
33 NA
35 GND CON_LBKLT_EN
37 CON_LBKLT_CTL
39 LCD_BLT_VCC
1
1 5
1 2
3 1
6
1
Signal Name Pin
LCD_VCC 2
39 40
39 40
NA 4
6
GND 8
LVDS_A_DATA1 10
GND 14
LVDS_A_DATA3 16
LVDS_A_CLK# 18
1 2
1 2
GND 20
LVDS_B_DATA0 22
GND 26
LVDS_B_DATA2 28
GND 32
LVDS_B_CLK 34
36
LCD_BLT_VCC 38
LCD_BLT_VCC 40
Signal Name Pin
LCD_VCC 2
NA 4
NA 6
GND 8
EDP_TX1 10
EDP_TX0# 12
GND 14
NA 16
EDP_AUXN 18
GND 20
NA 22
NA 24
GND 26
NA 28
NA 30
GND 32
NA 34
36
LCD_BLT_VCC 38
LCD_BLT_VCC 40