Download Print this page

Renesas R9A02G015 User Manual

Assp (usb power delivery controller)

Table Of Contents

page of 828

/ 828
Contents
Table of Contents
Bookmarks

Table of Contents

Advertisement

Quick Links

Download this manual

Cover

R9A02G015

16

ASSP (USB Power Delivery Controller)

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev.1.00

Mar 2019

Table of Contents

Advertisement

Table of Contents

Need help?

Need help?

Do you have a question about the R9A02G015 and is the answer not in the manual?

Questions and answers

Summary of Contents for Renesas R9A02G015

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
Page 3 Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
Page 4: How To Use This Manual
This manual is intended to give users an understanding of the functions described in the Organization below. Organization The R9A02G015 manual is separated into three parts: this manual, Data Sheet, and the software edition (common to the RL78 family). R9A02G015 RL78 Family User’s Manual: Hardware...
Page 5 E2 Emulator RTE0T00020KCE00000R User’s Manual R20UT3538E E2 Emulator Lite RTE0T0002LKCE00000R User’s Manual R20UT3240E Renesas Flash Programmer Flash Memory Programming Software User’s Manual R20UT4066E Renesas Flash Development Toolkit User’s Manual R20UT0508E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing.
Page 6: Table Of Contents
CONTENTS OUTLINE ............................17 Features ..........................17 Ordering Information ....................... 19 Pin Configuration (Top View) ....................20 1.3.1 32-pin product (with USB) ....................20 1.3.2 32-pin product (without USB) ..................... 21 Pin Identification ........................22 Block Diagram ........................23 1.5.1 32-pin products ........................
Page 7 3.4.8 Based indexed addressing ....................76 3.4.9 Stack addressing ........................ 77 PORT FUNCTIONS ........................80 Port Functions ........................80 Port Configuration ........................80 4.2.1 Port 0 ..........................80 4.2.2 Port 2 ..........................80 4.2.3 Port 4 ..........................81 4.2.4 Port 5 ..........................81 4.2.5 Port 6 ..........................
Page 8 5.3.12 USB clock selection register (UCKSEL) ................121 System Clock Oscillator ......................122 5.4.1 X1 oscillator ........................122 5.4.2 High-speed on-chip oscillator ................... 125 5.4.3 Low-speed on-chip oscillator .................... 125 5.4.4 PLL (Phase Locked Loop) ....................125 Clock Generator Operation ....................126 Controlling Clock ........................
Page 9 6.6.2 TOmn Pin Output Setting ....................192 6.6.3 Cautions on Channel Output Operation ................193 6.6.4 Collective manipulation of TOmn bit ................. 198 6.6.5 Timer Interrupt and TOmn Pin Output at Operation Start ..........199 Timer Input (TImn) Control ....................200 6.7.1 TImn input circuit configuration ..................
Page 10 Operation of Watchdog Timer ....................261 9.4.1 Controlling operation of watchdog timer ................261 9.4.2 Setting overflow time of watchdog timer ................262 9.4.3 Setting window open period of watchdog timer ..............263 9.4.4 Setting watchdog timer interval interrupt ................264 A/D CONVERTER ........................
Page 11 11.1.1 3-wire serial I/O (CSI00, CSI01) ..................319 11.1.2 UART (UART0) ......................... 320 11.1.3 Simplified I C (IIC00, IIC01) ..................... 321 11.2 Configuration of Serial Array Unit ..................322 11.2.1 Shift register ........................325 11.2.2 Lower 8/9 bits of the serial data register mn (SDRmn) ............. 325 11.3 Registers Controlling Serial Array Unit .................
Page 12 11.7.5 Calculating transfer rate ....................454 11.7.6 Procedure for processing errors that occurred during simplified I C (IIC00, IIC01) communication ......................... 456 SERIAL INTERFACE IICA ......................457 12.1 Functions of Serial Interface IICA ..................457 12.2 Configuration of Serial Interface IICA ................... 460 12.3 Registers Controlling Serial Interface IICA ................
Page 13 13.3.5 CFIFO port select register (CFIFOSEL), DnFIFO port select register (DnFIFOSEL) (n = 0, 1) ........................... 562 13.3.6 CFIFO port control register (CFIFOCTR), DnFIFO port control register (DnFIFOCTR) (n = 0, 1) ........................... 566 13.3.7 Interrupt enable register 0 (INTENB0) ................570 13.3.8 Interrupt enable register n (INTENBn) (n = 1, 2) ..............
Page 14 13.4.13 Battery charging detection processing ................661 INTERRUPT FUNCTIONS ......................666 14.1 Interrupt Function Types ....................... 666 14.2 Interrupt Sources and Configuration ..................666 14.3 Registers Controlling Interrupt Functions ................671 14.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) ....... 674 14.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) .....
Page 15 18.4.3 When used as interrupt and reset mode ................734 18.5 Changing of LVD Detection Voltage Setting ................. 739 18.5.1 Changing of LVD detection voltage setting in LVD reset mode ........740 18.5.2 Changing of LVD detection voltage setting in LVD interrupt mode ........741 18.6 Cautions for Voltage Detector ....................
Page 16 22.4.4 Communication commands ....................788 22.5 Processing Time for Each Command When PG-FP6 Is in Use (Reference Value) ....790 22.6 Self-Programming ......................... 791 22.6.1 Self-programming procedure .................... 792 22.6.2 Boot swap function ......................793 22.6.3 Flash shield window function .................... 795 22.7 Security Settings ........................
Page 17: Outline
R9A02G015 R19UH0112EJ0100 ASSP (USB Power Delivery Controller) Rev.1.00 Mar 29, 2019 CHAPTER 1 OUTLINE Features Ultra-low power consumption technology = single power supply voltage of 2.7 to 5.5 V HALT mode STOP mode SNOOZE mode RL78 CPU core CISC architecture with 3-stage pipeline Minimum instruction execution time: 0.04167 μs: @ 24 MHz operation with high-speed on-chip oscillator...
Page 18 R9A02G015 CHAPTER 1 OUTLINE Power management and reset function On-chip power-on-reset (POR) circuit On-chip voltage detector (LVD) (Select reset from 6 levels) Complying with USB Specification Revision 2.0, incorporating host/function controller Corresponding to full-speed transfer (12 Mbps) and low-speed (1.5 Mbps) Complying with Battery Charging Specification Revision 1.2...
Page 19: Ordering Information
Product without USB (R9A02G0151) Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R19UH0112EJ0100 Rev.1.00 Page 19 of 825...
Page 20: Pin Configuration (Top View)
R9A02G015 CHAPTER 1 OUTLINE Pin Configuration (Top View) 1.3.1 32-pin product (with USB) • 32-pin QFN (4 × 4 mm, 0.4 mm pitch) exposed die pad 24 23 22 21 20 19 18 17 P25/ANI5 P53/INTP9/TI02 /TO02 /SCL01 /SCK 01/UOVRCUR1...
Page 21: 32-Pin Product (Without Usb)
R9A02G015 CHAPTER 1 OUTLINE 1.3.2 32-pin product (without USB) • 32-pin QFN (4 × 4 mm, 0.4 mm pitch) exposed die pad 24 23 22 21 20 19 18 17 P25/ANI5 P53/INTP9/TI02 /TO02 /SCL01 /SCK 01 P24/ANI4 P52/INTP8/TI01 /TO01 /SO 00/TXD0 /TOOLTXD...
Page 22: Pin Identification
R9A02G015 CHAPTER 1 OUTLINE Pin Identification ANI0 to ANI5, ANI16, ANI17: Analog input A/D converter reference potential (- side) input REFM A/D converter reference potential (+ side) input REFP EXCLK: External clock input (main system clock) INTP0 to INTP15: External interrupt input...
Page 23: Block Diagram
R9A02G015 CHAPTER 1 OUTLINE Block Diagram 1.5.1 32-pin products Port 0 P00, P01 TIMER ARRAY UNIT 0 (8ch) TI00 Port 2 P20 to P25 ch00 TO00 TI01 ch01 Port 4 TO01 TI02 ch02 TO02 Port 5 P50 to P55 TI03...
Page 24: Outline Of Functions
R9A02G015 CHAPTER 1 OUTLINE Outline of Functions (1/2) 32-pin (with USB) 32-pin (without USB) Item R9A02G0150 R9A02G0151 Code flash memory (KB) 128 KB Data flash memory (KB) 2 KB Note 1 Address space 1 MB Main system clock High-speed system clock (f...
Page 25 R9A02G015 CHAPTER 1 OUTLINE (2/2) 32-pin (with USB) 32-pin (without USB) Item R9A02G0150 R9A02G0151 Power supply voltage = 2.7 to 5.5 V Operating ambient temperature = -40 to +85°C Note 1. The flash library uses RAM in self-programming and rewriting of the data flash memory.
Page 26: Pin Functions
R9A02G015 CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS Port Functions Pin I/O buffer power supplies are shown below. Table 2 - 1 Pin I/O Buffer Power Supplies Power Supply Corresponding Pins All pins other than UDP0, UDM0, UDP1, and UDM1 UDP0, UDM0, UDP1, UDM1 Set in each port I/O, buffer, pull-up resistor is also valid for alternate functions.
Page 27 R9A02G015 CHAPTER 2 PIN FUNCTIONS (2/2) Function After Reset Pin Type Alternate Function Function Name Release 12-1-3 Input port INTP1/SCLA0 Port 6. 5-bit I/O port. INTP2/SDAA0 Input/output can be specified in 1-bit units. Output can be set to N-ch open-drain output (6 V tolerance).
Page 28: Functions Other Than Port Pins
R9A02G015 CHAPTER 2 PIN FUNCTIONS Functions other than port pins (1/2) Product with USB Product without USB Function Name Function 32-pin 32-pin ANI0 Input A/D converter analog input   ANI1   ANI2   ANI3   ANI4 ...
Page 29 R9A02G015 CHAPTER 2 PIN FUNCTIONS (2/2) Product with USB Product without USB Function Name Function 32-pin 32-pin SI00 Input Serial data input to CSI00, CSI01   SI01   SO00 Output Serial data output from CSI00, CSI01  ...
Page 30 R9A02G015 CHAPTER 2 PIN FUNCTIONS Table 2 - 2 Relationships Between P40/TOOL0 and Operation Mode After Reset Release P40/TOOL0 Operating mode Normal operation mode Flash memory programming mode For details, see 22.4 Programming Method. Remark Use bypass capacitors (about 0.1 μF) as noise and latch up countermeasures with relatively thick wires at the shortest...
Page 31: Connection Of Unused Pins
R9A02G015 CHAPTER 2 PIN FUNCTIONS Connection of Unused Pins Table 2 - 3 shows the Connection of Unused Pins. Remark The mounted pins depend on the product. Refer to 1.3 Pin Configuration (Top View) and 2.1 Port Functions. Table 2 - 3 Connection of Unused Pins...
Page 32: Pin Block Diagrams
R9A02G015 CHAPTER 2 PIN FUNCTIONS Pin Block Diagrams For the pin types listed in 2.1.1 32-pin Products, pin block diagrams are shown in Figures 2 - 1 to 2 - 11. Figure 2 - 1 Pin Block Diagram of Pin Type 2-1-1...
Page 33 R9A02G015 CHAPTER 2 PIN FUNCTIONS Figure 2 - 3 Pin Block Diagram of Pin Type 2-2-1 Clock generator OSCSEL Alternate function P122/X2/EXCLK/Alternate function EXCLK, OSCSEL N-ch P-ch Alternate function P121/X1/Alternate function Remark Refer to 2.1 Port Functions for alternate functions.
Page 34 R9A02G015 CHAPTER 2 PIN FUNCTIONS Figure 2 - 4 Pin Block Diagram of Pin Type 4-3-5 0: Digital I/O 1: Analog input PMC register PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) PMS register P-ch A/D converter N-ch R19UH0112EJ0100 Rev.1.00...
Page 35 R9A02G015 CHAPTER 2 PIN FUNCTIONS Figure 2 - 5 Pin Block Diagram of Pin Type 7-1-3 Alternate function PU register P-ch (PUmn) Schmitt2 PORT PORT Output latch (Pmn) P-ch N-ch PMS register PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU) Remark 1.
Page 36 R9A02G015 CHAPTER 2 PIN FUNCTIONS Figure 2 - 6 Pin Block Diagram of Pin Type 8-1-4 PU register (PUmn) P-ch PIM register (PIMmn) Alternate function Schmitt2 CMOS PORT PORT Output latch (Pmn) P-ch N-ch PMS register PM register (PMmn) POM register...
Page 37 R9A02G015 CHAPTER 2 PIN FUNCTIONS Figure 2 - 7 Pin Block Diagram of Pin Type 8-3-4 PU register (PUmn) P-ch PIM register (PIMmn) PMC register (PMCmn) Alternate function Schmitt2 PORT CMOS PORT Output latch (Pmn) P-ch N-ch PMS register PM register...
Page 38 R9A02G015 CHAPTER 2 PIN FUNCTIONS Figure 2 - 8 Pin Block Diagram of Pin Type 12-1-2 Alternate function PORT Schmitt1 PORT Output latch (Pmn) N-ch PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU) Remark 1. Refer to 2.1 Port Functions for alternate functions.
Page 39 R9A02G015 CHAPTER 2 PIN FUNCTIONS Figure 2 - 9 Pin Block Diagram of Pin Type 12-1-3 Alternate function PER0 PER0 (IICENj) Schmitt1 PORT Output latch (Pmn) N-ch PM register (PMmn) PMS register Alternate function (SAU) Alternate function (other than SAU) Remark 1.
Page 40 R9A02G015 CHAPTER 2 PIN FUNCTIONS Figure 2 - 10 Pin Block Diagram of Pin Type 17-11-1 Pull-down N-ch N-ch enable R19UH0112EJ0100 Rev.1.00 Page 40 of 825 Mar 29, 2019...
Page 41 R9A02G015 CHAPTER 2 PIN FUNCTIONS Figure 2 - 11 Pin Block Diagram of Pin Type 18-11-1 Pull-up P-ch enable Data P-ch Output N-ch disable Pull-down N-ch enable Input enable Input enable Pull-up P-ch enable Data P-ch Output N-ch disable Pull-down...
Page 42: Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE The R9A02G015 has the RL78-S3 CPU core. The CPU core in the RL78-S3 employs the Harvard architecture which has independent instruction fetch bus, address bus and data bus. In addition, through the adoption of three-stage pipeline control of fetch, decode, and memory access, the operation efficiency is remarkably improved over the conventional CPU core.
Page 43: Memory Space
R9A02G015 CHAPTER 3 CPU ARCHITECTURE Memory Space Products in the R9A02G015 can access a 1 MB address space. Figures 3 - 1 shows the memory maps. Figure 3 - 1 Memory Map FFFFFH 1FFFFH Special function register (SFR) 256 bytes...
Page 44 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3 - 1 Correspondence Between Address Values and Block Numbers in Flash Memory .
Page 45: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. The R9A02G015 products incorporate internal ROM (flash memory), as shown below. Table 3 - 2 Internal ROM Capacity Internal ROM Part Number...
Page 46 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Table 3 - 3 Vector Table (2/2) Vector Table Address Interrupt Source With USB Without USB 32-pin 32-pin 00038H INTIT   0003CH INTUSB   0003EH INTRSUM   00040H INTIICA2 —  00044H INTTM04 ...
Page 47: Mirror Area
3.1.2 Mirror area The R9A02G015 mirrors the code flash area of 00000H to 0FFFFH, to F0000H to FFFFFH (the code flash area to be mirrored is set by the processor mode control register (PMC)). By reading data from F0000H to FFFFFH, an instruction that does not have the ES register as an operand can be used, and thus the contents of the code flash can be read with the shorter code.
Page 48: Internal Data Memory Space
Caution 2. After setting the PMC register, wait for at least one instruction and access the mirror area. 3.1.3 Internal data memory space The R9A02G015 products incorporate the following RAMs. Table 3 - 4 Internal RAM Capacity Part Number Internal RAM R9A02G0150 7168 ×...
Page 49: Special Function Register (Sfr) Area
R9A02G015 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Tables 3 - 5 in 3.2.4 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned.
Page 50: Data Memory Addressing
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the R9A02G015, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of the special function registers (SFR) and general- purpose registers are available for use.
Page 51: Processor Registers
R9A02G015 CHAPTER 3 CPU ARCHITECTURE Processor Registers The R9A02G015 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
Page 52 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. In-service priority flags (ISP1, ISP0) This flag manages the priority of acknowledgeable maskable vectored interrupts.
Page 53: General-Purpose Registers
R9A02G015 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Page 54: And Cs Registers
R9A02G015 CHAPTER 3 CPU ARCHITECTURE 3.2.3 ES and CS registers The ES register and CS register are used to specify the higher address for data access and when a branch instruction is executed (register direct addressing), respectively. The default value of the ES register after reset is 0FH, and that of the CS register is 00H.
Page 55: Special Function Registers (Sfrs)
R9A02G015 CHAPTER 3 CPU ARCHITECTURE 3.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
Page 56 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Table 3 - 5 Special Function Register (SFR) List (1/3) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit FFF00H Port register 0 —   FFF02H Port register 2 —...
Page 57 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Table 3 - 5 Special Function Register (SFR) List (2/3) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit FFF64H Timer data register 02 TDR02 — — 0000H ...
Page 58 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Table 3 - 5 Special Function Register (SFR) List (3/3) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit FFFECH Priority specification flag register 10 PR10L PR10  ...
Page 59: Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)
R9A02G015 CHAPTER 3 CPU ARCHITECTURE 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2 SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area.
Page 60 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Table 3 - 6 Extended Special Function Register (2nd SFR) List (1/6) Address Extended Special Function Register Symbol Manipulable Bit Range After Reset (2nd SFR) Name 1-bit 8-bit 16-bit F0010H A/D converter mode register 2 ADM2 —...
Page 61 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Table 3 - 6 Extended Special Function Register (2nd SFR) List (2/6) Address Extended Special Function Register Symbol Manipulable Bit Range After Reset (2nd SFR) Name 1-bit 8-bit 16-bit F011AH Serial communication operation setting register 01 SCR01 —...
Page 62 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Table 3 - 6 Extended Special Function Register (2nd SFR) List (3/6) Address Extended Special Function Register Symbol Manipulable Bit Range After Reset (2nd SFR) Name 1-bit 8-bit 16-bit F019CH Timer mode register 06 TMR06 —...
Page 63 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Table 3 - 6 Extended Special Function Register (2nd SFR) List (4/6) Address Extended Special Function Register Symbol Manipulable Bit Range After Reset (2nd SFR) Name 1-bit 8-bit 16-bit F0240H IICCTL20 — Note 1 ...
Page 64 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Table 3 - 6 Extended Special Function Register (2nd SFR) List (5/6) Address Extended Special Function Register Symbol Manipulable Bit Range After Reset (2nd SFR) Name 1-bit 8-bit 16-bit F0434H INTENB2 — — 0000H Note 3 ...
Page 65 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Table 3 - 6 Extended Special Function Register (2nd SFR) List (6/6) Address Extended Special Function Register Symbol Manipulable Bit Range After Reset (2nd SFR) Name 1-bit 8-bit 16-bit F046EH PIPEPERI — — 0000H Note 3 ...
Page 66: Instruction Address Addressing
R9A02G015 CHAPTER 3 CPU ARCHITECTURE Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: -128 to +127 or -32768 to +32767) to the program counter (PC)’s value (the start address of the next instruction), and specifies the program address to be used as the...
Page 67: Register Indirect Addressing
(PC) as 16-bit data, and specifies the program address. Table indirect addressing is applied only for CALLT instructions. In the R9A02G015, branching is enabled only to the 64 KB space from 00000H to 0FFFFH. Figure 3 - 13 Outline of Table Indirect Addressing OP code High Addr.
Page 68: Addressing For Processing Data Addresses
R9A02G015 CHAPTER 3 CPU ARCHITECTURE Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word.
Page 69: Direct Addressing
R9A02G015 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier Description !addr16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable)
Page 70: Short Direct Addressing
R9A02G015 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH. [Operand format]...
Page 71: Sfr Addressing
R9A02G015 CHAPTER 3 CPU ARCHITECTURE 3.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format]...
Page 72: Register Indirect Addressing
R9A02G015 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description — [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) —...
Page 73: Based Addressing
R9A02G015 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address.
Page 74 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Figure 3 - 25 Example of word [B], word [C] word [B], word [C] <1> <2> <1> <2> FFFFFH Instruction code Array of <2> Target memory word-sized <2> Offset data OP-code r (B/C) Low Addr.
Page 75 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Figure 3 - 28 Example of word [B], word [C] ES: word [B], ES: word [C] <1> <2> <3><1> <2> <3> XFFFFH <3> Array of Instruction code <3> Target memory word-sized OP-code Offset data r (B/C) <2>...
Page 76: Based Indexed Addressing
R9A02G015 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address.
Page 77: Stack Addressing
R9A02G015 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) values. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request.
Page 78 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Figure 3 - 33 Example of POP <1> <2> SP + 2 <1> (SP + 1) SP + 1 Instruction code Stack area (SP) OP-code <2> F0000H • Stack addressing is specified <1>. • The contents of addresses SP and SP + 1 are stored in the lower-order and higher-order bytes of the pair of registers indicated by rp <2>, respectively.
Page 79 R9A02G015 CHAPTER 3 CPU ARCHITECTURE Figure 3 - 36 Example of Interrupt, BRK <2> <1> Instruction code SP-1 PC19-PC16 SP-2 Stack area OP-code SP-3 PC15-PC8 SP-4 <3> PC7-PC0 Interrupt <2> F0000H • Stack addressing is specified <1>. In response to a BRK...
Page 80: Port Functions
CHAPTER 4 PORT FUNCTIONS Port Functions The R9A02G015 is provided with digital I/O ports, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS.
Page 81: Port 4
R9A02G015 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 4 Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 pin is used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4).
Page 82: Port 13
R9A02G015 CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 13 P137 is a 1-bit input-only port. P137 is fixed an input ports. This port can also be used for external interrupt request input. R19UH0112EJ0100 Rev.1.00 Page 82 of 825 Mar 29, 2019...
Page 83: Registers Controlling Port Function
R9A02G015 CHAPTER 4 PORT FUNCTIONS Registers Controlling Port Function Port functions are controlled by the following registers. • Port mode registers (PMxx) • Port registers (Pxx) • Pull-up resistor option registers (PUxx) • Port input mode registers (PIMxx) • Port output mode registers (POMxx) •...
Page 84 R9A02G015 CHAPTER 4 PORT FUNCTIONS Table 4 - 2 PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (2/2) Bit Name Product with USB Product without USB Port PMxx PUxx PIMxx POMxx PMCxx 32-pin 32-pin...
Page 85: Port Mode Registers (Pmxx)
R9A02G015 CHAPTER 4 PORT FUNCTIONS 4.3.1 Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.
Page 86: Port Registers (Pxx)
R9A02G015 CHAPTER 4 PORT FUNCTIONS 4.3.2 Port registers (Pxx) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is...
Page 87: Pull-Up Resistor Option Registers (Puxx)
R9A02G015 CHAPTER 4 PORT FUNCTIONS 4.3.3 Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode (PMmn = 1 and POMmn = 0) for the pins to which the use of an on-chip pull-up resistor has been specified in these registers.
Page 88: Port Output Mode Registers (Pomxx)
R9A02G015 CHAPTER 4 PORT FUNCTIONS 4.3.5 Port output mode registers (POMxx) These registers set the output mode in 1-bit units. N-ch open-drain output (V tolerance) mode can be selected during serial communication with an external device of the different potential, and for the SDA00 and SDA01 pins during simplified I C communication with an external device of the same potential.
Page 89: Port Function Operations
R9A02G015 CHAPTER 4 PORT FUNCTIONS Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 90: Handling Different Potential (1.8 V, 2.5 V) By Using I/O Buffers
R9A02G015 CHAPTER 4 PORT FUNCTIONS 4.4.4 Handling different potential (1.8 V, 2.5 V) by using I/O buffers It is possible to connect an external device operating on a different potential (1.8 V, 2.5 V) by switching I/O buffers with the port input mode register (PIMxx) and port output mode register (POMxx).
Page 91 R9A02G015 CHAPTER 4 PORT FUNCTIONS (3) Setting procedure when using I/O pins of IIC00 and IIC01 functions with a different potential (1.8 V, 2.5 V) In case of simplified IIC00: P50, P51 In case of simplified IIC01: P53, P54 <1> Using an external resistor, pull up externally the pin to be used to the power supply of the target device (on-chip pull-up resistor cannot be used).
Page 92: Register Settings When Using Alternate Function
R9A02G015 CHAPTER 4 PORT FUNCTIONS Register Settings When Using Alternate Function 4.5.1 Basic concept when using alternate function In the beginning, for a pin also assigned to be used for analog function, use the port mode control register (PMCxx) to specify whether to use the pin for analog function or digital input/output.
Page 93: Register Settings For Alternate Function Whose Output Function Is Not Used
R9A02G015 CHAPTER 4 PORT FUNCTIONS 4.5.2 Register settings for alternate function whose output function is not used When the output of an alternate function of the pin is not used, the following settings should be made. (1) SOp = 1, TxDq = 1 (settings when the serial output (SOp/TxDq) of SAU is not used)
Page 94: Register Setting Examples For Used Port And Alternate Functions
R9A02G015 CHAPTER 4 PORT FUNCTIONS 4.5.3 Register setting examples for used port and alternate functions Register setting examples for used port and alternate functions are shown in Tables 4 - 4 to 4 - 11. The registers used to control the port functions should be set as shown in Tables 4 - 4 to 4 - 11. See the following remark for legends used in Tables 4 - 4 to 4 - 11.
Page 95 R9A02G015 CHAPTER 4 PORT FUNCTIONS Table 4 - 5 Setting Examples of Registers When Using P20 to 25 Pin Function Used Function Alternate Function Output 32-pin ADM2 POMxx PMCxx PMxx Function SAU Output Other than without Name with USB Name...
Page 96 R9A02G015 CHAPTER 4 PORT FUNCTIONS Table 4 - 7 Setting Examples of Registers When Using P50 to P55 Pin Function (1/2) Used Function Alternate Function Output 32-pin POMxx PMCxx PMxx Function SAU Output without Name Other than SAU with USB...
Page 97 R9A02G015 CHAPTER 4 PORT FUNCTIONS Table 4 - 7 Setting Examples of Registers When Using P50 to P55 Pin Function (2/2) Used Function Alternate Function Output 32-pin POMxx PMCxx PMxx Function SAU Output without Name Other than SAU with USB...
Page 98 R9A02G015 CHAPTER 4 PORT FUNCTIONS Table 4 - 9 Setting Examples of Registers When Using P70 to P74 Pin Function Used Function Alternate Function Output 32-pin POMxx PMCxx PMxx Function SAU Output without Name Other than SAU with USB Name...
Page 99: Cautions When Using Port Function
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A 1-bit manipulation instruction is executed in the following order in the R9A02G015. <1> The Pn register is read in 8-bit units.
Page 100: Notes On Specifying The Pin Settings
R9A02G015 CHAPTER 4 PORT FUNCTIONS 4.6.2 Notes on specifying the pin settings For an output pin to which multiple functions are assigned, the output of the unused alternate functions must be set to its initial state so as to prevent conflicting outputs. For details about the alternate function output, see 4.5 Register Settings When Using Alternate Function.
Page 101: Clock Generator
R9A02G015 CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two kinds of system clocks and clock oscillators are selectable.
Page 102 R9A02G015 CHAPTER 5 CLOCK GENERATOR (2) Low-speed on-chip oscillator clock (Low-speed on-chip oscillator) This circuit oscillates a clock of f = 15 kHz (TYP.). The low-speed on-chip oscillator clock cannot be used as the CPU clock. Only the following peripheral hardware runs on the low-speed on-chip oscillator clock.
Page 103: Configuration Of Clock Generator
R9A02G015 CHAPTER 5 CLOCK GENERATOR Configuration of Clock Generator The clock generator includes the following hardware. Table 5 - 1 Configuration of Clock Generator Item Configuration Control registers Clock operation mode control register (CMC) System clock control register (CKC) Clock operation status control register (CSC)
Page 104 R9A02G015 CHAPTER 5 CLOCK GENERATOR Figure 5 - 1 Block Diagram of Clock Generator (Note and Remark are listed on the next page.) R19UH0112EJ0100 Rev.1.00 Page 104 of 825 Mar 29, 2019...
Page 105: Registers Controlling Clock Generator
R9A02G015 CHAPTER 5 CLOCK GENERATOR Note Be sure to select f when using the USB host/function controller. Remark X1 clock oscillation frequency Main system clock source frequency when the high-speed on-chip oscillator clock divided 1, 2, 4, or 8, or the PLL clock divided by 2, 4, or 8 is selected (24 MHz max.) : High-speed on-chip oscillator clock frequency (48 MHz max.)
Page 106: Clock Operation Mode Control Register (Cmc)
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.3.1 Clock operation mode control register (CMC) This register is used to set the operation mode of the X1/P121, X2/EXCLK/P122 pins, and to select a gain of the oscillator. The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release. This register can be read by an 8-bit memory manipulation instruction.
Page 107: System Clock Control Register (Ckc)
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.3.2 System clock control register (CKC) This register is used to select a CPU/peripheral hardware clock and a main system clock. The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 108: Clock Operation Status Control Register (Csc)
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.3.3 Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock and high-speed on-chip oscillator. The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 109: Oscillation Stabilization Time Counter Status Register (Ostc)
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.3.4 Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. The X1 clock oscillation stabilization time can be checked in the following case, •...
Page 110 R9A02G015 CHAPTER 5 CLOCK GENERATOR Figure 5 - 5 Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H After reset: 00H Symbol MOST MOST MOST MOST MOST MOST OSTC MOST8 MOST9 Oscillation stabilization time status MOST MOST MOST...
Page 111: Oscillation Stabilization Time Select Register (Osts)
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.3.5 Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time. When the X1 clock is made to oscillate by clearing the MSTOP bit to start the X1 oscillation circuit operating, actual operation is automatically delayed for the time set in the OSTS register.
Page 112 R9A02G015 CHAPTER 5 CLOCK GENERATOR Figure 5 - 6 Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H Symbol OSTS OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection OSTS2 OSTS1 OSTS0 = 10 MHz = 20 MHz 25.6 µs...
Page 113: Peripheral Enable Registers 0, 2 (Per0, Per2)
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.3.6 Peripheral enable registers 0, 2 (PER0, PER2) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise.
Page 114 R9A02G015 CHAPTER 5 CLOCK GENERATOR Figure 5 - 7 Format of Peripheral Enable Register 0 (PER0) Address: F00F0H After reset: 00H Symbol <7> <5> <4> <2> <0> PER0 IICA2EN Note IICA1EN ADCEN IICA0EN SAU0EN TAU0EN IICA2EN Note Control of serial interface IICA2 input clock supply Stops input clock supply.
Page 115: Subsystem Clock Supply Mode Control Register (Osmc)
R9A02G015 CHAPTER 5 CLOCK GENERATOR Figure 5 - 8 Format of Peripheral Enable Register 2 (PER2) Address: F00FCH After reset: 00H Symbol PER2 TMKAEN TMKAEN Control of 12-bit interval timer input clock supply Stops input clock supply. • SFRs used by the 12-bit interval timer cannot be written.
Page 116: High-Speed On-Chip Oscillator Frequency Select Register (Hocodiv)
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.3.8 High-speed on-chip oscillator frequency select register (HOCODIV) The frequency of the high-speed on-chip oscillator which is set by an option byte (000C2H) can be changed by using high-speed on-chip oscillator frequency select register (HOCODIV). However, the selectable frequency depends on the FRQSEL4 and FRQSEL3 bits of the option byte (000C2H).
Page 117: High-Speed On-Chip Oscillator Trimming Register (Hiotrm)
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.3.9 High-speed on-chip oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the high-speed on-chip oscillator. With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock input (timer array unit), and so on, the accuracy can be adjusted.
Page 118: Pll Control Register (Dscctl)
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.3.10 PLL control register (DSCCTL) This register is used to control the operations of the PLL oscillator. The DSCCTL register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 119 R9A02G015 CHAPTER 5 CLOCK GENERATOR The combination which user can select as the USB clock when the PLL is used is shown below. Figure 5 - 13 Relationship between the PLL and the USB Clock High-speed Divided by k n times...
Page 120: Main Clock Control Register (Mckc)
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.3.11 Main clock control register (MCKC) This register is used to control the operations of the main clock. The MCKC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 121: Usb Clock Selection Register (Ucksel)
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.3.12 USB clock selection register (UCKSEL) The UCKSEL register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 5 - 15 Format of USB clock selection register (UCKSEL)
Page 122: System Clock Oscillator
R9A02G015 CHAPTER 5 CLOCK GENERATOR System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
Page 123 R9A02G015 CHAPTER 5 CLOCK GENERATOR Figure 5 - 17 shows examples of incorrect resonator connection. Figure 5 - 17 Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT (c) The X1 and X2 signal line wires cross.
Page 124 R9A02G015 CHAPTER 5 CLOCK GENERATOR Figure 5 - 17 Examples of Incorrect Resonator Connection (2/2) (f) Current flowing through ground line of oscillator (e) Wiring near high alternating current (potential at points A, B, and C fluctuates) High current (g) Signals are fetched R19UH0112EJ0100 Rev.1.00...
Page 125: High-Speed On-Chip Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4.2 High-speed on-chip oscillator The high-speed on-chip oscillator is incorporated in the R9A02G015. Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC). The high-speed on-chip oscillator automatically starts oscillating after reset release.
Page 126: Clock Generator Operation
R9A02G015 CHAPTER 5 CLOCK GENERATOR Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5 - 1). • Main system clock MAIN • High-speed system clock...
Page 127 2.4 AC Characteristics of the R9A02G015 Data Sheet (R19DS0101E) (the above figure is an example when the external reset is in use).
Page 128: Controlling Clock
R9A02G015 CHAPTER 5 CLOCK GENERATOR Controlling Clock 5.6.1 Example of setting high-speed on-chip oscillator After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on- chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected from 48, 24, 16, 12, 8, 6, 4, 3, 2, and 1 MHz by using FRQSEL0 to FRQSEL4 of the option byte (000C2H).
Page 129 R9A02G015 CHAPTER 5 CLOCK GENERATOR [High-speed on-chip oscillator frequency select register (HOCODIV) setting] Address: F00A8H Symbol HOCODIV HOCODIV2 HOCODIV1 HOCODIV0 Selection of high-speed on-chip oscillator clock frequency HOCODIV2 HOCODIV1 HOCODIV0 FRQSEL4 = 0 FRQSEL4 = 1 FRQSEL3 = 0 FRQSEL3 = 1...
Page 130: Example Of Setting X1 Oscillation Clock
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.6.2 Example of setting X1 oscillation clock After a reset release, the CPU/peripheral hardware clock (f always starts operating with the high-speed on- CLK) chip oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start...
Page 131: Example Of Setting Pll Circuit
R9A02G015 CHAPTER 5 CLOCK GENERATOR Caution Set the HOCODIV register within the operable voltage range of the flash operation mode set in the option byte (000C2H) before and after the frequency change. Option Byte (000C2H) Value Operating Frequency Flash Operation Mode...
Page 132 R9A02G015 CHAPTER 5 CLOCK GENERATOR <5> Set (1) the CKSELR bit of the MCKC register to select PLL output for the system clock. RDIV1 RDIV0 CKSELR MCKC <6> Use software to set up a wait of 135 µs. Note 3 <7>...
Page 133: Cpu Clock Status Transition Diagram
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.6.4 CPU clock status transition diagram Figure 5 - 19 shows the CPU clock status transition diagram of this product. Figure 5 - 19 CPU Clock Status Transition Diagram High-speed on-chip oscillation: Woken up Power ON...
Page 134 (OSTS) Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see ELECTRICAL SPECIFICATIONS in the R9A02G015 Data Sheet (R19DS0101E)). R19UH0112EJ0100 Rev.1.00 Page 134 of 825...
Page 135 (OSTS) Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see ELECTRICAL SPECIFICATIONS in the R9A02G015 Data Sheet (R19DS0101E)). R19UH0112EJ0100 Rev.1.00 Page 135 of 825...
Page 136 R9A02G015 CHAPTER 5 CLOCK GENERATOR Table 5 - 4 CPU Clock Transition and SFR Register Setting Examples (3/4) (4) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register...
Page 137 R9A02G015 CHAPTER 5 CLOCK GENERATOR Table 5 - 4 CPU Clock Transition and SFR Register Setting Examples (4/4) (6) CPU clock changing from high-speed system clock (PLL mode) (K) to high-speed on-chip oscillator clock (Setting sequence of SFR registers) Setting Flag of SFR Register...
Page 138: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.6.5 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5 - 5 Changing CPU Clock (1/2)
Page 139 R9A02G015 CHAPTER 5 CLOCK GENERATOR Table 5 - 5 Changing CPU Clock (2/2) CPU Clock Condition Before Change Processing After Change Before Change After Change External main system High-speed on-chip Enabling oscillation of high-speed on-chip External main system clock input...
Page 140: Time Required For Switchover Of Cpu Clock And System Clock
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.6.6 Time required for switchover of CPU clock and system clock By setting bit 4 (MCM0) of the system clock control register (CKC), the CPU clock can be switched, and main system clock can be switched (between the high-speed on-chip oscillator clock and the high-speed system clock).
Page 141: Conditions Before Clock Oscillation Is Stopped
R9A02G015 CHAPTER 5 CLOCK GENERATOR 5.6.7 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Before stopping the clock oscillation, check the conditions before the clock oscillation is stopped.
Page 142: Resonator And Oscillator Constants
Caution 2. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the R9A02G015 so that the internal operation conditions are within the specifications of the DC and AC characteristics.
Page 143 R9A02G015 CHAPTER 5 CLOCK GENERATOR X1 oscillation: As of March, 2013 (1/2) Flash Recommended Circuit Oscillation Voltage Part Number operation Note 2 SMD/ Frequency Range (V) Constants (reference) Manufacturer Resonator Note 3 mode Lead (MHz) Note 1 Rd (k  )
Page 144 R9A02G015 CHAPTER 5 CLOCK GENERATOR As of March, 2013 (2/2) Flash Recommended Circuit Oscillation Voltage operation Note 2 SMD/ Frequency Range (V) Constants (reference) Manufacturer Resonator Part Number mode Lead (MHz) Note 1 Rd (k  ) C1 (pF) C2 (pF) MIN.
Page 145: Timer Array Unit
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT CHAPTER 6 TIMER ARRAY UNIT The timer array unit has eight 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can be used to create a high-accuracy timer.
Page 146: Functions Of Timer Array Unit
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Functions of Timer Array Unit Timer array unit has the following functions. 6.1.1 Independent channel operation function By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels.
Page 147: Simultaneous Channel Operation Function
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT (5) Measurement of high-/low-level width of input signal Counting is started by a single edge of the signal input to the timer input pin (TImn), and the count value is captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured.
Page 148: 8-Bit Timer Operation Function (Channels 1 And 3 Only)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT (2) PWM (Pulse Width Modulation) output Two channels are used as a set to generate a pulse with a specified period and a specified duty factor. Compare operation Operation clock Interrupt signal (INTTMmn) Channel n (master)
Page 149: Configuration Of Timer Array Unit
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Configuration of Timer Array Unit Timer array unit includes the following hardware. Table 6 - 1 Configuration of Timer Array Unit Item Configuration Timer/counter Timer count register mn (TCRmn) Register Timer data register mn (TDRmn)
Page 150 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT The port pins alternatively used as timer I/O pins in each timer array unit channel depend on the product. Table 6 - 2 Timer I/O Pins provided in Each Product Timer array unit channels...
Page 151 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 1 Entire Configuration of Timer Array Unit 0 Timer clock select register 0 (TPS0) PRS031 PRS030 PRS021 PRS020 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 Timer input select register 0 (TIS0)
Page 152 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 2 Internal Block Diagram of Channel 0 of Timer Array Unit Timer CK00 TCLK Output controller controller TO00 Mode CK01 Output latch selection (Pxx) PMxx Interrupt controller INTTM00 (Timer interrupt) Timer counter register 00 (TCR00)
Page 153 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 4 Internal Block Diagram of Channel n of Timer Array Unit Interrupt signal from master channel Timer CK00 Output controller controller TCLK TO0n CK01 Mode Output latch selection (Pxx) PMxx Interrupt controller...
Page 154 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 6 Internal Block Diagram of Channel 5 of Timer Array Unit Interrupt signal from master channel CK00 TCLK Output controller TO05 Timer controller CK01 Output latch Mode (Pxx) PMxx selection Interrupt controller...
Page 155: Timer Count Register Mn (Tcrmn)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.2.1 Timer count register mn (TCRmn) The TCRmn register is a 16-bit read-only register and is used to count clocks. The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock.
Page 156 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT The TCRmn register read value differs as follows according to operation mode changes and the operating status. Table 6 - 3 Timer Count Register mn (TCRmn) Read Value in Various Operation Modes Note Timer count register mn (TCRmn) Read Value...
Page 157: Timer Data Register Mn (Tdrmn)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.2.2 Timer data register mn (TDRmn) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn).
Page 158: Registers Controlling Timer Array Unit
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers. • Peripheral enable register 0 (PER0) • Timer clock select register m (TPSm) • Timer mode register mn (TMRmn) • Timer status register mn (TSRmn) •...
Page 159: Peripheral Enable Register 0 (Per0)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.3.1 Peripheral enable register 0 (PER0) This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
Page 160: Timer Clock Select Register M (Tpsm)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.3.2 Timer clock select register m (TPSm) The TPSm register is a 16-bit register that is used to select two types or four types of operation clocks (CKm0, CKm1, CKm2, CKm3) that are commonly supplied to each channel. CKm0 is selected by using bits 3 to 0 of the TPSm register, and CKm1 is selected by using bits 7 to 4 of the TPSm register.
Page 161 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 12 Format of Timer clock select register m (TPSm) (1/2) Address: F01B6H, F01B7H After reset: 0000H Symbol PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm TPSm Note...
Page 162 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 13 Format of Timer clock select register m (TPSm) (2/2) Address: F01B6H, F01B7H After reset: 0000H Symbol PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm PRSm TPSm Note...
Page 163: Timer Mode Register Mn (Tmrmn)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.3.3 Timer mode register mn (TMRmn) The TMRmn register sets an operation mode of channel n. This register is used to select the operation clock ), select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count).
Page 164 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 14 Format of Timer mode register mn (TMRmn) (1/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMRmn CKSm CKSm CCSm MAST STSm STSm STSm CISmn CISmn...
Page 165 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 15 Format of Timer mode register mn (TMRmn) (2/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMRmn CKSm CKSm CCSm MAST STSm STSm STSm CISmn CISmn...
Page 166 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 16 Format of Timer mode register mn (TMRmn) (3/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMRmn CKSm CKSm CCSm MAST STSm STSm STSm CISmn CISmn...
Page 167 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 17 Format of Timer mode register mn (TMRmn) (4/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMRmn CKSm CKSm CCSm MAST STSm STSm STSm CISmn CISmn...
Page 168: Timer Status Register Mn (Tsrmn)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.3.4 Timer status register mn (TSRmn) The TSRmn register indicates the overflow status of the counter of channel n. The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode (MDmn3 to MDmn1 = 110B).
Page 169: Timer Channel Enable Status Register M (Tem)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.3.5 Timer channel enable status register m (TEm) The TEm register is used to enable or stop the timer operation of each channel. Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer channel stop register m (TTm).
Page 170: Timer Channel Start Register M (Tsm)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.3.6 Timer channel start register m (TSm) The TSm register is a trigger register that is used to initialize timer count register mn (TCRmn) and start the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is set to 1.
Page 171: Timer Channel Stop Register M (Ttm)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.3.7 Timer channel stop register m (TTm) The TTm register is a trigger register that is used to stop the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is cleared to 0.
Page 172: Timer Input Select Register 0 (Tis0)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.3.8 Timer input select register 0 (TIS0) The TIS0 register is used to select the channel 0 and 1 timer input. The TIS0 register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 173: Timer Output Enable Register M (Toem)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.3.9 Timer output enable register m (TOEm) The TOEm register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer output register m (TOm) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TOmn).
Page 174: Timer Output Register M (Tom)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.3.10 Timer output register m (TOm) The TOm register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TOmn) of each channel.
Page 175: Timer Output Level Register M (Tolm)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.3.11 Timer output level register m (TOLm) The TOLm register is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOEmn = 1) in the Slave channel output mode (TOMmn = 1).
Page 176: Timer Output Mode Register M (Tomm)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.3.12 Timer output mode register m (TOMm) The TOMm register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0.
Page 177: Noise Filter Enable Register 1 (Nfen1)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.3.13 Noise filter enable register 1 (NFEN1) The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
Page 178 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 27 Format of Noise filter enable register 1 (NFEN1) Address: F0071H After reset: 00H Symbol NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00 TNFEN07 Enable/disable using noise filter of TI07 pin...
Page 179: Registers That Control Port Functions Of Timer Input/Output Pins
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.3.14 Registers that control port functions of timer input/output pins Using the timer array unit requires setting of the registers that control the port functions for the port pins with which the timer array unit pin functions for the target channel are multiplexed (port mode register (PMxx), port register (Pxx), and port mode control register (PMCxx)).
Page 180: Basic Rules Of Timer Array Unit
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Basic Rules of Timer Array Unit 6.4.1 Basic rules of simultaneous channel operation function When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.
Page 181 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT The rules of the simultaneous channel operation function are applied in a channel group (a master channel and slave channels forming one simultaneous channel operation function). If two or more channel groups that do not operate in combination are specified, the basic rules of the simultaneous channel operation function in 6.4.1 Basic rules of simultaneous channel operation function do not apply to the...
Page 182: Basic Rules Of 8-Bit Timer Operation Function (Channels 1 And 3 Only)
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-bit timer channels.
Page 183: Operation Of Counter
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Operation of Counter 6.5.1 Count clock (f TCLK The count clock (f ) of the timer array unit can be selected between following by CCSmn bit of timer mode TCLK register mn (TMRmn). • Operation clock (f ) specified by the CKSmn0 and CKSmn1 bits •...
Page 184 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) The count clock (f ) becomes the signal that detects valid edge of input signal via the TImn pin and...
Page 185: Start Timing Of Counter
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.5.2 Start timing of counter Timer count register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start register m (TSm). Operations from count operation enabled state to timer count Register mn (TCRmn) count start is shown in Table 6 - 6.
Page 186: Operation Of Counter
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.5.3 Operation of counter Here, the counter operation in each mode is explained. (1) Operation of interval timer mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. Timer count register mn (TCRmn) holds the initial value until count clock generation.
Page 187 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT (2) Operation of event counter mode <1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0). <2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
Page 188 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT (3) Operation of capture mode (input pulse interval measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until count clock generation.
Page 189 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT (4) Operation of one-count mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation. <3> Rising edge of the TImn input is detected.
Page 190 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT (5) Start timing in capture & one-count mode (when high-level width is measured) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm).
Page 191: Channel Output (Tomn Pin) Control
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Channel Output (TOmn pin) Control 6.6.1 TOmn pin output circuit configuration Figure 6 - 35 Output Circuit Configuration <5> TOmn register Interrupt signal of the master channel (INTTMmn) TOmn pin Interrupt signal of the slave channel...
Page 192: Tomn Pin Output Setting
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.6.2 TOmn Pin Output Setting The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer operation start. Figure 6 - 36 Status Transition from Timer Output Setting to Operation Start...
Page 193: Cautions On Channel Output Operation
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.6.3 Cautions on Channel Output Operation (1) Changing values set in the registers TOm, TOEm, and TOLm during timer operation Since the timer operations (operations of timer count register mn (TCRmn) and timer data register mn...
Page 194 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT (2) Default level of TOmn pin and output level after timer operation start The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer output is disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1) before port output is enabled, is shown below.
Page 195 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT When operation starts with slave channel output mode (TOMmp = 1) setting (PWM output)) When slave channel output mode (TOMmp = 1), the active level is determined by timer output level register m (TOLm) setting.
Page 196 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT (3) Operation of TOmn pin in slave channel output mode (TOMmn = 1) When timer output level register m (TOLm) setting has been changed during timer operation When the TOLm register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TOmn pin change condition.
Page 197 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 40 Set/Reset Timing Operating Statuses (1) Basic operation timing TCLK INTTMmn Master Internal reset channel signal TOmn pin/TOmn Toggle Toggle Internal reset signal 1 clock delay INTTMmp Slave channel Internal reset...
Page 198: Collective Manipulation Of Tomn Bit
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.6.4 Collective manipulation of TOmn bit In timer output register m (TOm), the setting bits for all the channels are located in one register in the same way as timer channel start register m (TSm). Therefore, the TOmn bit of all the channels can be manipulated collectively.
Page 199: Timer Interrupt And Tomn Pin Output At Operation Start
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.6.5 Timer Interrupt and TOmn Pin Output at Operation Start In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to generate a timer interrupt at count start.
Page 200: Timer Input (Timn) Control
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Timer Input (TImn) Control 6.7.1 TImn input circuit configuration A signal is input from a timer input pin, goes through a noise filter and an edge detector, and is sent to a timer controller. Enable the noise filter for the pin in need of noise removal. The following shows the configuration of the input circuit.
Page 201: Cautions On Channel Input Operation
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.7.3 Cautions on channel input operation When a timer input pin is set as unused, the operating clock is not supplied to the noise filter. Therefore, after settings are made to use the timer input pin, the following wait time is necessary before a trigger is specified to enable operation of the channel corresponding to the timer input pin.
Page 202: Independent Channel Operation Function Of Timer Array Unit
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Independent Channel Operation Function of Timer Array Unit 6.8.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals.
Page 203 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 46 Block Diagram of Operation as Interval Timer/Square Wave Output CKm1 Note Operation clock Timer counter Output TOmn pin CKm0 register mn (TCRmn) controller Timer data Interrupt Interrupt signal TSmn register mn (TDRmn)
Page 204 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 48 Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn Note STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1...
Page 205 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 49 Operation Procedure of Interval Timer/Square Wave Output Function (1/2) Software Operation Hardware Status Power-off status (Clock supply is stopped and writing to each register default setting is disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Page 206 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 50 Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Software Operation Hardware Status To hold the TOmn pin output level Clears the TOmn bit to 0 after the value to stop be held is set to the port register.
Page 207: Operation As External Event Counter
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.8.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an interrupt.
Page 208 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 52 Example of Basic Timing of Operation as External Event Counter TSmn TEmn TImn TCRmn 0000H 0003H 0002H TDRmn INTTM mn 4 events 4 events 3 events Remark 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7) Remark 2.
Page 209 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 53 Example of Set Contents of Registers in External Event Counter Mode Timer mode register mn (TMRmn) CKSmn1 CKSmn0 C CSmn Note S TSmn2 STSmn1 S TSmn0 CISmn1 CISmn0 MDmn3 M Dmn2...
Page 210 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 54 Operation Procedure When External Event Counter Function Is Used Software Operation Hardware Status Power-off status (Clock supply is stopped and writing to each register default setting is disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Page 211: Operation As Input Pulse Interval Measurement
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.8.3 Operation as input pulse interval measurement The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured. In addition, the count value can be captured by using software operation (TSmn = 1) as a capture trigger while the TEmn bit is set to 1.
Page 212 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 56 Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0 = 0) TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn 0000H INTTMmn Remark 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7) Remark 2.
Page 213 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 57 Example of Set Contents of Registers to Measure Input Pulse Interval Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn Note STSmn2 STSmn1 STSmn0 C ISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0...
Page 214 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 58 Operation Procedure When Input Pulse Interval Measurement Function Is Used Software Operation Hardware Status Power-off status (Clock supply is stopped and writing to each register default setting is disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Page 215: Operation As Input Signal High-/Low-Level Width Measurement
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.8.4 Operation as input signal high-/low-level width measurement By starting counting at one edge of the TImn pin input and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of TImn can be measured. The signal width of TImn can be calculated by the following expression.
Page 216 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 60 Example of Basic Timing of Operation as Input Signal High-/Low-Level Width Measurement TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn 0000H INTTMmn Remark 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7) Remark 2.
Page 217 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 61 Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn Note STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0...
Page 218 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 62 Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used Software Operation Hardware Status Power-off status (Clock supply is stopped and writing to each register default setting is disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Page 219: Operation As Delay Counter
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.8.5 Operation as delay counter It is possible to start counting down when the valid edge of the TImn pin input is detected (an external event), and then generate INTTMmn (a timer interrupt) after any specified interval.
Page 220 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 64 Example of Basic Timing of Operation as Delay Counter TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn INTTMmn a + 1 b + 1 Remark 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7) Remark 2.
Page 221 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 65 Example of Set Contents of Registers to Delay Counter Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn Note STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn Operation mode of channel n...
Page 222 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 66 Operation Procedure When Delay Counter Function Is Used Software Operation Hardware Status Power-off status (Clock supply is stopped and writing to each register default setting is disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Page 223: Simultaneous Channel Operation Function Of Timer Array Unit
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Simultaneous Channel Operation Function of Timer Array Unit 6.9.1 Operation as one-shot pulse output function By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the TImn pin.
Page 224 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 67 Block Diagram of Operation as One-Shot Pulse Output Function Master channel (one-count mode) CKm1 Operation clock Timer counter CKm0 register mn (TCRmn) TNFENmn TSmn Timer data Interrupt signal Interrupt register mn (TDRmn)
Page 225 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 68 Example of Basic Timing of Operation as One-Shot Pulse Output Function TSmn TEmn TImn Master FFFFH channel TCRmn 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp 0000H Slave channel TDRmp...
Page 226 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 69 Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel) Timer mode register mn (TMRmn) TERmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3...
Page 227 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 70 Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel) Timer mode register mp (TMRmp) CKSmp1 CKSmp0 CCSmp Note STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3...
Page 228 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 71 Operation Procedure of One-Shot Pulse Output Function (1/2) Software Operation Hardware Status Power-off status (Clock supply is stopped and writing to each register default setting is disabled.) Sets the TAUmEN bit of peripheral enable registers 0 (PER0) to 1.
Page 229 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 72 Operation Procedure of One-Shot Pulse Output Function (2/2) Software Operation Hardware Status Operation Sets the TOEmp bit (slave) to 1 (only when operation is The TEmn and TEmp bits are set to 1 and the master resumed).
Page 230: Operation As Pwm Function
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.9.2 Operation as PWM function Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions.
Page 231 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 73 Block Diagram of Operation as PWM Function Master channel (interval timer mode) CKm1 Operation clock Timer counter CKm0 register mn (TCRmn) Timer data Interrupt signal Interrupt TSmn register mn (TDRmn)
Page 232 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 74 Example of Basic Timing of Operation as PWM Function TSmn TEmn FFFFH TCRmn Master 0000H channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp 0000H Slave channel TDRmp TOmp INTTMmp a + 1...
Page 233 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 75 Example of Set Contents of Registers When PWM Function (Master Channel) Is Used Timer mode register mn (TMRmn) TERmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1...
Page 234 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 76 Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used Timer mode register mp (TMRmp) CKSmp1 CKSmp0 CCSmp Note STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3 MDmp2 MDmp1...
Page 235 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 77 Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status Power-off status (Clock supply is stopped and writing to each register default setting is disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Page 236 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 78 Operation Procedure When PWM Function Is Used (2/2) Software Operation Hardware Status Operation Sets the TOEmp bit (slave) to 1 (only when operation is resumed). start The TSmn (master) and TSmp (slave) bits of timer...
Page 237: Operation As Multiple Pwm Output Function
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.9.3 Operation as multiple PWM output function By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values can be output. For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the following expressions.
Page 238 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 79 Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs) Master channel (interval timer mode) CKm1 Operation clock Timer counter CKm0 register mn (TCRmn) Timer data...
Page 239 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 80 Example of Basic Timing of Operation as Multiple PWM Output Function (Output two types of PWMs) (1/2) TSmn TEmn FFFFH TCRmn Master 0000H channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH...
Page 240 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Remark 1. m: Unit number (m = 0), n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n < p < q ≤ 7 (Where p and q are integers greater than n) Remark 2.
Page 241 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 81 Example of Set Contents of Registers When Multiple PWM Output Function (Master Channel) Is Used Timer mode register mn (TMRmn) TERmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3...
Page 242 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 82 Example of Set Contents of Registers When Multiple PWM Output Function (Slave Channel) Is Used (output two types of PWMs) Timer mode register mp, mq (TMRmp, TMRmq) CKSmp1 CKSmp0 CCSmp...
Page 243 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 83 Operation Procedure When Multiple PWM Output Function Is Used (output two types of PWMs) (1/2) Software Operation Hardware Status Power-off status (Clock supply is stopped and writing to each register...
Page 244 R9A02G015 CHAPTER 6 TIMER ARRAY UNIT Figure 6 - 84 Operation Procedure When Multiple PWM Output Function Is Used (output two types of PWMs) (2/2) Software Operation Hardware Status Operation (Sets the TOEmp and TOEmq (slave) bits to 1 only when resuming operation.)
Page 245: Cautions When Using Timer Array Unit
R9A02G015 CHAPTER 6 TIMER ARRAY UNIT 6.10 Cautions When Using Timer Array Unit 6.10.1 Cautions When Using Timer output Depends on products, a pin is assigned a timer output and other alternate functions. In this case, outputs of the other alternate functions must be set in initial status.
Page 246: Bit Interval Timer
R9A02G015 CHAPTER 7 12-BIT INTERVAL TIMER CHAPTER 7 12-BIT INTERVAL TIMER Functions of 12-bit Interval Timer An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from STOP mode and triggering an A/D converter’s SNOOZE mode.
Page 247: Registers Controlling 12-Bit Interval Timer
R9A02G015 CHAPTER 7 12-BIT INTERVAL TIMER Registers Controlling 12-bit Interval Timer The 12-bit interval timer is controlled by the following registers. • Peripheral enable register 2 (PER2) • Peripheral reset control register 2 (PRR2) • Subsystem clock supply mode control register (OSMC) •...
Page 248: Peripheral Reset Control Register 2 (Prr2)
R9A02G015 CHAPTER 7 12-BIT INTERVAL TIMER 7.3.2 Peripheral reset control register 2 (PRR2) This register is used for individual reset control of each peripheral hardware. This MCU controls reset and reset release of each peripheral hardware supported by the PRR2 register.
Page 249: 12-Bit Interval Timer Control Register (Itmc)
R9A02G015 CHAPTER 7 12-BIT INTERVAL TIMER 7.3.4 12-bit interval timer control register (ITMC) This register is used to set up the starting and stopping of the 12-bit interval timer operation and to specify the timer compare value. The ITMC register can be set by a 16-bit memory manipulation instruction.
Page 250: 12-Bit Interval Timer Operation
R9A02G015 CHAPTER 7 12-BIT INTERVAL TIMER 12-bit Interval Timer Operation 7.4.1 12-bit interval timer operation timing The count value specified for the ITCMP11 to ITCMP0 bits is used as an interval to operate an 12-bit interval timer that repeatedly generates interrupt requests (INTIT).
Page 251: Start Of Count Operation And Re-Enter To Halt/Stop Mode After Returned From Halt/Stop Mode
R9A02G015 CHAPTER 7 12-BIT INTERVAL TIMER 7.4.2 Start of count operation and re-enter to HALT/STOP mode after returned from HALT/STOP mode When setting the RINTE bit after returned from HALT or STOP mode and entering HALT or STOP mode again, write 1 to the RINTE bit, and confirm the written value of the RINTE bit is reflected or wait for at least one cycle of the count clock.
Page 252: Clock Output/Buzzer Output Controller
R9A02G015 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for clock output for supply to peripheral ICs. Buzzer output is a function to output a square wave of buzzer frequency.
Page 253 R9A02G015 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 8 - 1 Block Diagram of Clock Output/Buzzer Output Controller Prescaler MAIN to f MAIN MAIN Clock/buzzer P00/INTP12/TI05/TO05/ to f controller MAIN MAIN ANI16/PCLBUZ0 PCLOE0 Output latch PM00 (P00) CCS02 CCS01 CCS00...
Page 254: Configuration Of Clock Output/Buzzer Output Controller
R9A02G015 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 8 - 1 Configuration of Clock Output/Buzzer Output Controller Item Configuration Control registers Clock output select registers n (CKSn)
Page 255 R9A02G015 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 8 - 2 Format of Clock output select registers n (CKSn) Address: FFFA5H (CKS0) After reset: 00H Symbol <7> CKSn PCLOEn CCSn2 CCSn1 CCSn0 PCLOEn PCLBUZ0 pin output enable/disable specification Output disable (default)
Page 256: Registers Controlling Port Functions Of Pins To Be Used For Clock Or Buzzer Output
R9A02G015 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 8.3.2 Registers controlling port functions of pins to be used for clock or buzzer output Using a port pin for clock or buzzer output requires setting of the registers that control the port functions multiplexed on the target pin (port mode register (PMxx), port register (Pxx)).
Page 257: Operations Of Clock Output/Buzzer Output Controller
R9A02G015 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Operations of Clock Output/Buzzer Output Controller One pin can be used to output a clock or buzzer sound. The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0).
Page 258: Watchdog Timer
R9A02G015 CHAPTER 9 WATCHDOG TIMER CHAPTER 9 WATCHDOG TIMER Functions of Watchdog Timer The counting operation of the watchdog timer is set by the option byte (000C0H). The watchdog timer operates on the low-speed on-chip oscillator clock (f The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated.
Page 259: Configuration Of Watchdog Timer
R9A02G015 CHAPTER 9 WATCHDOG TIMER Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 9 - 1 Configuration of Watchdog Timer Item Configuration Counter Internal counter (17 bits) Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option byte.
Page 260: Register Controlling Watchdog Timer
R9A02G015 CHAPTER 9 WATCHDOG TIMER Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). 9.3.1 Watchdog timer enable register (WDTE) Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again.
Page 261: Operation Of Watchdog Timer
R9A02G015 CHAPTER 9 WATCHDOG TIMER Operation of Watchdog Timer 9.4.1 Controlling operation of watchdog timer When the watchdog timer is used, its operation is specified by the option byte (000C0H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 21).
Page 262: Setting Overflow Time Of Watchdog Timer
R9A02G015 CHAPTER 9 WATCHDOG TIMER Caution 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H). WDSTBYON = 0 WDSTBYON = 1 In HALT mode Watchdog timer operation stops.
Page 263: Setting Window Open Period Of Watchdog Timer
R9A02G015 CHAPTER 9 WATCHDOG TIMER 9.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (000C0H). The outline of the window is as follows.
Page 264: Setting Watchdog Timer Interval Interrupt
R9A02G015 CHAPTER 9 WATCHDOG TIMER Remark If the overflow time is set to 2 , the window close time and open time are as follows. Setting of Window Open Period 100% Window close time 0 to 20.08 ms 0 to 10.04 ms...
Page 265: A/D Converter
R9A02G015 CHAPTER 10 A/D CONVERTER CHAPTER 10 A/D CONVERTER The number of analog input channels of the A/D converter is shown below. with USB without USB 32-pin 32-pin 8 ch 8 ch Analog input channels (ANI0 to ANI5, ANI16 and ANI17) (ANI0 to ANI5, ANI16 and ANI17) 10.1...
Page 266 R9A02G015 CHAPTER 10 A/D CONVERTER Various A/D conversion modes can be specified by using the mode combinations below. Trigger mode Software trigger Conversion is started by software. Hardware trigger no-wait mode Conversion is started by detecting a hardware trigger. Hardware trigger wait mode...
Page 267 R9A02G015 CHAPTER 10 A/D CONVERTER Figure 10 - 1 Block Diagram of A/D Converter R19UH0112EJ0100 Rev.1.00 Page 267 of 825 Mar 29, 2019...
Page 268: Configuration Of A/D Converter
R9A02G015 CHAPTER 10 A/D CONVERTER 10.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI5, ANI16 and ANI17 These are the analog input pins of the 8 channels of the A/D converter. They input analog signals to be converted into digital signals.
Page 269 R9A02G015 CHAPTER 10 A/D CONVERTER (6) 10-bit A/D conversion result register (ADCR) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lower 6 bits are fixed to 0).
Page 270: Registers Controlling A/D Converter
R9A02G015 CHAPTER 10 A/D CONVERTER 10.3 Registers Controlling A/D Converter The A/D converter is controlled by the following registers. • Peripheral enable register 0 (PER0) • A/D converter mode register 0 (ADM0) • A/D converter mode register 1 (ADM1) • A/D converter mode register 2 (ADM2) •...
Page 271: Peripheral Enable Register 0 (Per0)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
Page 272: A/D Converter Mode Register 0 (Adm0)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.3.2 A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 273 R9A02G015 CHAPTER 10 A/D CONVERTER Table 10 - 1 Settings of ADCS and ADCE Bits ADCS ADCE A/D Conversion Operation Conversion stopped state Conversion standby state Setting prohibited Conversion-in-progress state Table 10 - 2 Setting and Clearing Conditions for ADCS Bit...
Page 274 R9A02G015 CHAPTER 10 A/D CONVERTER Figure 10 - 4 Timing Chart When A/D Voltage Comparator Is Used A/D voltage comparator: enables operation ADCE Note 2 Conversion start time A/D voltage comparator Conversion Conversion Conversion Conversion standby operation standby stopped Software...
Page 275 ) described in 2.6.1 CONV A/D converter characteristics of the R9A02G015 Data Sheet (R19DS0101E). Caution 2. Rewrite the FR2 to FR0, LV1 and LV0 bits to other than the same data while conversion is stopped (ADCS = 0, ADCE = 0).
Page 276 Caution 1. The A/D conversion time must also be within the relevant range of conversion times (t ) described in 2.6.1 CONV A/D converter characteristics of the R9A02G015 Data Sheet (R19DS0101E). Note that the conversion time (t CONV does not include the A/D power supply stabilization wait time.
Page 277 R9A02G015 CHAPTER 10 A/D CONVERTER Figure 10 - 5 A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode) 1 is written to ADCS or ADS is rewritten. ADCS Sampling timing INTAD Sampling Conversion Sampling Successive conversion Successive conversion...
Page 278: A/D Converter Mode Register 1 (Adm1)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.3.3 A/D converter mode register 1 (ADM1) This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal. The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 279: A/D Converter Mode Register 2 (Adm2)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.3.4 A/D converter mode register 2 (ADM2) This register is used to select the + side or - side reference voltage of the A/D converter, check the upper limit and lower limit A/D conversion result values, select the resolution, and specify whether to use the SNOOZE mode.
Page 280 R9A02G015 CHAPTER 10 A/D CONVERTER Figure 10 - 8 Format of A/D Converter Mode Register 2 (ADM2) (2/2) Address: F0010H After reset: 00H Symbol <3> <2> <0> ADM2 ADREFP1 ADREFP0 ADREFM ADRCK ADTYP Specification of the SNOOZE mode Do not use the SNOOZE mode function.
Page 281: 10-Bit A/D Conversion Result Register (Adcr)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.3.5 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR). The...
Page 282: 8-Bit A/D Conversion Result Register (Adcrh)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.3.6 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are Note stored The ADCRH register can be read by an 8-bit memory manipulation instruction.
Page 283: Analog Input Channel Specification Register (Ads)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.3.7 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 284 R9A02G015 CHAPTER 10 A/D CONVERTER Figure 10 - 13 Format of Analog Input Channel Specification Register (ADS) (2/2) Address: FFF31H After reset: 00H Symbol ADISS ADS4 ADS3 ADS2 ADS1 ADS0  Select mode (ADMD = 0) ADISS ADS4 ADS3 ADS2...
Page 285: Conversion Result Comparison Upper Limit Setting Register (Adul)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.3.8 Conversion result comparison upper limit setting register (ADUL) This register is used to specify the setting for checking the upper limit of the A/D conversion results. The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 10 - 8).
Page 286: A/D Test Register (Adtes)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.3.10 A/D test register (ADTES) This register is used to select the + side reference voltage or - side reference voltage for the converter, an analog input channel (ANIxx), the temperature sensor output, or the internal reference voltage output (1.45 V) as the target for conversion.
Page 287: A/D Converter Conversion Operations
R9A02G015 CHAPTER 10 A/D CONVERTER 10.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended.
Page 288 R9A02G015 CHAPTER 10 A/D CONVERTER Figure 10 - 17 Conversion Operation of A/D Converter (Software Trigger Mode) ADCS  1 or ADS rewrite Conversion time Sampling time A/D converter SAR clear A/D conversion Sampling operation Conversion Undefined result Conversion ADCR...
Page 289: Input Voltage And Conversion Results
R9A02G015 CHAPTER 10 A/D CONVERTER 10.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI5, ANI16 and ANI17) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.
Page 290: A/D Converter Operation Modes
R9A02G015 CHAPTER 10 A/D CONVERTER 10.6 A/D Converter Operation Modes The operation of each A/D converter mode is described below.In addition, the procedure for specifying each mode is described in 10.7 A/D Converter Setup Flowchart. 10.6.1 Software trigger mode (select mode, sequential conversion mode) <1>...
Page 291: Software Trigger Mode (Select Mode, One-Shot Conversion Mode)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.6.2 Software trigger mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 292: Software Trigger Mode (Scan Mode, Sequential Conversion Mode)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.6.3 Software trigger mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 293: Software Trigger Mode (Scan Mode, One-Shot Conversion Mode)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.6.4 Software trigger mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 294: Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 295: Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 296: Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 297: Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 298: Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 299: Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 300: Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 301: Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 302: A/D Converter Setup Flowchart
R9A02G015 CHAPTER 10 A/D CONVERTER 10.7 A/D Converter Setup Flowchart The A/D converter setup flowchart in each operation mode is described below. 10.7.1 Setting up software trigger mode Figure 10 - 31 Setting up Software Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
Page 303: Setting Up Hardware Trigger No-Wait Mode
R9A02G015 CHAPTER 10 A/D CONVERTER 10.7.2 Setting up hardware trigger no-wait mode Figure 10 - 32 Setting up Hardware Trigger No-Wait Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
Page 304: Setting Up Hardware Trigger Wait Mode
R9A02G015 CHAPTER 10 A/D CONVERTER 10.7.3 Setting up hardware trigger wait mode Figure 10 - 33 Setting up Hardware Trigger Wait Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
Page 305: Setup When Using Temperature Sensor (Example For Software Trigger Mode And One-Shot Conversion Mode)
R9A02G015 CHAPTER 10 A/D CONVERTER 10.7.4 Setup when using temperature sensor (example for software trigger mode and one-shot conversion mode) Figure 10 - 34 Setup when temperature sensor output/internal reference voltage output is selected Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
Page 306: Setting Up Test Mode
R9A02G015 CHAPTER 10 A/D CONVERTER 10.7.5 Setting up test mode Figure 10 - 35 Setting up Test Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
Page 307: Snooze Mode Function
R9A02G015 CHAPTER 10 A/D CONVERTER 10.8 SNOOZE Mode Function In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D conversion is stopped while in the STOP mode, but, by using the SNOOZE mode, A/D conversion can be performed without operating the CPU by inputting a hardware trigger.
Page 308 R9A02G015 CHAPTER 10 A/D CONVERTER (1) If an interrupt is generated after A/D conversion ends If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is generated.
Page 309 R9A02G015 CHAPTER 10 A/D CONVERTER (2) If no interrupt is generated after A/D conversion ends If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is not generated.
Page 310 R9A02G015 CHAPTER 10 A/D CONVERTER Figure 10 - 39 Flowchart for Setting up SNOOZE Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input.
Page 311: How To Read A/D Converter Characteristics Table
R9A02G015 CHAPTER 10 A/D CONVERTER 10.9 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 312 R9A02G015 CHAPTER 10 A/D CONVERTER (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0..000 to 0..001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0……001 to 0……010.
Page 313: Conversion Time
R9A02G015 CHAPTER 10 A/D CONVERTER Figure 10 - 44 Integral Linearity Error Figure 10 - 45 Differential Linearity Error 1..1 1..1 Ideal 1LSB width Ideal line Differential linearity error Integral linearity error 0..0 0..0 Analog input Analog input (8) Conversion time This expresses the time from the start of sampling to when the digital output is obtained.
Page 314: 10.10 Cautions For A/D Converter
R9A02G015 CHAPTER 10 A/D CONVERTER 10.10 Cautions for A/D Converter (1) Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time.
Page 315 R9A02G015 CHAPTER 10 A/D CONVERTER Figure 10 - 46 Analog Input Pin Connection If there is a possibility that noise equal to or higher than AV REFP or equal to or lower than AV and V may enter, clamp with...
Page 316 R9A02G015 CHAPTER 10 A/D CONVERTER Figure 10 - 47 Timing of A/D Conversion End Interrupt Request Generation ADS rewrite ADS rewrite ADIF is set but ANIm conversion (start of ANIn conversion) (start of ANIm conversion) has not ended. A/D conversion...
Page 317 R9A02G015 CHAPTER 10 A/D CONVERTER (10) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 10 - 48 Internal Equivalent Circuit of ANIn Pin ANIn Table 10 - 5 Resistance and Capacitance Values of Equivalent Circuit (Reference Values) ANIn Pins R1 [kΩ]...
Page 318: Serial Array Unit
CHAPTER 11 SERIAL ARRAY UNIT The serial array unit has two serial channels. All channels can achieve UART, 3-wire serial (CSI) and simplified I Function assignment of each channel supported by the R9A02G015 is as shown below. • 32-pin products...
Page 319: Functions Of Serial Array Unit
CHAPTER 11 SERIAL ARRAY UNIT 11.1 Functions of Serial Array Unit Each serial interface supported by the R9A02G015 has the following features. 11.1.1 3-wire serial I/O (CSI00, CSI01) Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel.
Page 320: Uart (Uart0)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.1.2 UART (UART0) This is a start-stop synchronization function using two lines: serial data transmission (TxD) and serial data reception (RxD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
Page 321: Simplified I 2 C (Iic00, Iic01)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.1.3 Simplified I C (IIC00, IIC01) This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master.
Page 322: Configuration Of Serial Array Unit
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.2 Configuration of Serial Array Unit The serial array unit includes the following hardware. Table 11 - 1 Configuration of Serial Array Unit Item Configuration Shift register 8 bits or 9 bits Buffer register...
Page 323 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Note The lower 8 bits of serial data register mn (SDRmn) can be read or written as the following SFRs, depending on the communication mode. • CSIp communication ..SIOp (CSIp data register) • UARTq reception....RXDq (UARTq receive data register) •...
Page 324 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 1 shows the Block Diagram of Serial Array Unit 0. Figure 11 - 1 Block Diagram of Serial Array Unit 0 Serial output register 0 (SO0) Noise filter enable register 0 (NFEN0)
Page 325: Shift Register
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.2.1 Shift register This is a 9-bit register that converts parallel data into serial data or vice versa. Note In case of the UART communication of nine bits of data, nine bits (bits 0 to 8) are used During reception, it converts data input to the serial pin into parallel data.
Page 326 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 2 Format of Serial data register mn (SDRmn) (mn = 00, 01) Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H FFF11H (SDR00) FFF10H (SDR00) SDRmn Shift register Remark For the function of the higher 7 bits of the SDRmn register, see 11.3 Registers Controlling Serial Array Unit .
Page 327: Registers Controlling Serial Array Unit
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3 Registers Controlling Serial Array Unit Serial array unit is controlled by the following registers. • Peripheral enable register 0 (PER0) • Peripheral reset control register 0 (PRR0) • Serial clock select register m (SPSm) •...
Page 328: Peripheral Enable Register 0 (Per0)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.1 Peripheral enable register 0 (PER0) PER0 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
Page 329: Peripheral Reset Control Register 0 (Prr0)
This register is used for individual reset control of each peripheral hardware. The R9A02G015 controls reset and reset release of each peripheral hardware supported by the PRR0 register. To reset the serial array unit, be sure to set bit 2 (SAU0RES) to 1.
Page 330: Serial Clock Select Register M (Spsm)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.3 Serial clock select register m (SPSm) The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register, and CKm0 is selected by bits 3 to 0.
Page 331 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 5 Format of Serial clock select register m (SPSm) Address: F0126H, F0127H (SPS0) After reset: 0000H Symbol SPSm Note Section of operation clock (CKmk) 2 MHz 5 MHz 10 MHz 20 MHz...
Page 332: Serial Mode Register Mn (Smrmn)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.4 Serial mode register mn (SMRmn) The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation clock (f ), specify whether the serial clock (f...
Page 333: Serial Communication Operation Setting Register Mn (Scrmn)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 7 Format of Serial mode register mn (SMRmn) (2/2) Address: F0110H, F0111H (SMR00) to F0112H, F0113H (SMR01) After reset: 0020H Symbol SMRmn Note Note Controls inversion of level of receive data of channel n in UART mode Note Falling edge is detected as the start bit.
Page 334 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 8 Format of Serial communication operation setting register mn (SCRmn) (1/2) Address: F0118H, F0119H (SCR00) to F011AH, F011BH (SCR01) After reset: 0087H Symbol SLCm DLSm SCRmn Note 1 Setting of operation mode of channel n Disable communication.
Page 335 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 9 Format of Serial communication operation setting register mn (SCRmn) (2/2) Address: F0118H, F0119H (SCR00) to F011AH, F011BH (SCR01) After reset: 0087H Symbol SLCm DLSm SCRmn Note 1 Setting of parity bit in UART mode...
Page 336: Serial Data Register Mn (Sdrmn)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.6 Serial data register mn (SDRmn) The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) of SDR00 and SDR01 as a transmit/receive buffer register, and bits 15 to 9 (higher 7 bits)
Page 337: Serial Flag Clear Trigger Register Mn (Sirmn)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.7 Serial flag clear trigger register mn (SIRmn) The SIRmn register is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of serial status register mn is cleared to 0.
Page 338: Serial Status Register Mn (Ssrmn)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.8 Serial status register mn (SSRmn) The SSRmn register is a register that indicates the communication status and error occurrence status of channel n. The errors indicated by this register are a framing error, parity error, and overrun error.
Page 339 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 13 Format of Serial status register mn (SSRmn) (2/2) Address: F0100H, F0101H (SSR00) to F0102H, F0103H (SSR01) After reset: 0000H Symbol SSRmn Note Framing error detection flag of channel n Note No error occurs.
Page 340: Serial Channel Start Register M (Ssm)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.9 Serial channel start register m (SSm) The SSm register is a trigger register that is used to enable starting communication/count by each channel. When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1 (Operation is enabled).
Page 341: Serial Channel Stop Register M (Stm)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.10 Serial channel stop register m (STm) The STm register is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0 (operation is stopped).
Page 342: Serial Channel Enable Status Register M (Sem)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.11 Serial channel enable status register m (SEm) The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1.
Page 343: Serial Output Enable Register M (Soem)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.12 Serial output enable register m (SOEm) The SOEm register is a register that is used to enable or stop output of the serial communication operation of each channel. Channel n that enables serial output cannot rewrite by software the value of the SOmn bit of serial output register m (SOm) to be described below, and a value reflected by a communication operation is output from the serial data output pin.
Page 344: Serial Output Register M (Som)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.13 Serial output register m (SOm) The SOm register is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n.
Page 345: Serial Output Level Register M (Solm)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.14 Serial output level register m (SOLm) The SOLm register is a register that is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0 for corresponding bit in the CSI mode and simplifies I C mode.
Page 346 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 20 Examples of Reverse Transmit Data Non-reverse Output (SOLmn = 0) SOLmn = 0 output TXDq Transmit data Reverse Output (SOLmn = 1) SOLmn = 1 output TXDq Transmit data (inverted)
Page 347: Serial Standby Control Register M (Sscm)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.15 Serial standby control register m (SSCm) The SSC0 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when receiving CSI00 or UART0 serial data. The SSCm register can be set by a 16-bit memory manipulation instruction.
Page 348 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 22 Interrupt in UART Reception Operation in SNOOZE Mode EOCmn Bit SSECm Bit Reception Ended Successfully Reception Ended in an Error INTSRx is generated. INTSRx is generated. INTSRx is generated. INTSRx is generated.
Page 349: Noise Filter Enable Register 0 (Nfen0)
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.16 Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel.
Page 350: 11.3.17 Registers Controlling Port Functions Of Serial Input/Output Pins
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.3.17 Registers controlling port functions of serial input/output pins Using the serial array unit requires setting of the registers that control the port functions multiplexed on the target channel (port mode register (PMxx), port register (Pxx), port input mode register (PIMxx), and port output mode register (POMxx)).
Page 351: Operation Stop Mode
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.4 Operation Stop Mode Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pin for serial interface can be used as port function pins in this mode.
Page 352: Stopping The Operation By Channels
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 11 - 25 Each Register Setting When Stopping the Operation by Channels Serial channel stop register m (STm)...
Page 353: Operation Of 3-Wire Serial I/O (Csi00, Csi01) Communication
SNOOZE mode makes data reception that does not require the CPU possible. Only following CSIs can be specified. • CSI00 Note Use the clocks within a range satisfying the SCK cycle time (t ) characteristics. For details, see ELECTRICAL SPECIFICATIONS in the R9A02G015 Data Sheet (R19DS0101E). R19UH0112EJ0100 Rev.1.00 Page 353 of 825 Mar 29, 2019...
Page 354 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT The channels supporting 3-wire serial I/O (CSI00, CSI01) are channels 0 and 1 of SAU0. • 32-pin products Unit Channel Used as CSI Used as UART Used as Simplified I CSI00 UART0 IIC00 CSI01 IIC01 3-wire serial I/O (CSI00, CSI01) performs the following seven types of communication operations.
Page 355: Master Transmission
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.5.1 Master transmission Master transmission is that the R9A02G015 microcontroller outputs a transfer clock and transmits data to another device. 3-Wire Serial I/O CSI00 CSI01 Target channel Channel 0 of SAU0 Channel 1 of SAU0...
Page 356: Register Setting
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11 - 26 Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI01) Serial mode register mn (SMRmn) CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 SMRmn...
Page 357: Operation Procedure
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11 - 27 Initial Setting Procedure for Master Transmission Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 358 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 29 Procedure for Resuming Master Transmission Starting setting for resumption Wait until stop the communication target (slave) or communication operation completed. (Essential) Slave ready? Disable data output and clock output of the target...
Page 359 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 11 - 30 Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2...
Page 360 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 31 Flowchart of Master Transmission (in Single-Transmission Mode) Starting CSI communication For the initial setting, refer to Figure 11 - 27 . (Select Transfer end interrupt) SAU default setting Set data for transmission and the number of data. Clear communication end flag...
Page 361 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 11 - 32 Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> <6> STmn SEmn SDRmn...
Page 362 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 33 Flowchart of Master Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, refer to Figure 11 - 27 . <1> (Select buffer empty interrupt) SAU default setting Set data for transmission and the number of data. Clear communication end flag...
Page 363: Master Reception
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.5.2 Master reception Master reception is that the R9A02G015 microcontroller outputs a transfer clock and receives data from other device. 3-Wire Serial I/O CSI00 CSI01 Target channel Channel 0 of SAU0 Channel 1 of SAU0...
Page 364 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11 - 34 Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI01) Serial mode register mn (SMRmn) CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 SMRmn...
Page 365 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11 - 35 Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 366 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 37 Procedure for Resuming Master Reception Starting setting for resumption Wait until stop the communication target (slave) or communication operation completed. (Essential) Completing slave preparations? Disable clock output of the target channel by...
Page 367 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 11 - 38 Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2...
Page 368 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 39 Flowchart of Master Reception (in Single-Reception Mode) Starting CSI communication For the initial setting, refer to Figure 11 - 35 . SAU default setting (Select Transfer end interrupt) Setting storage area of the receive data, number of communication data...
Page 369 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Processing flow (in continuous reception mode) Figure 11 - 40 Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3...
Page 370 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 41 Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication For the initial setting, refer to Figure 11 - 35 . (Select buffer empty interrupt) SAU default setting <1>...
Page 371: Master Transmission/Reception
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.5.3 Master transmission/reception Master transmission/reception is that the R9A02G015 microcontroller outputs a transfer clock and transmits/receives data to/from another device. 3-Wire Serial I/O CSI00 CSI01 Target channel Channel 0 of SAU0 Channel 1 of SAU0...
Page 372 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11 - 42 Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01) Serial mode register mn (SMRmn) CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 SMRmn...
Page 373 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11 - 43 Initial Setting Procedure for Master Transmission/Reception Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 374 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 45 Procedure for Resuming Master Transmission/Reception Starting setting for resumption Wait until stop the communication target (slave) or Completing slave communication operation completed. (Essential) preparations? Disable data output and clock output of the target...
Page 375 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 11 - 46 Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2...
Page 376 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 47 Flowchart of Master Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication For the initial setting, refer to Figure 11 - 43 . (Select transfer end interrupt) SAU default setting Setting storage data and number of data for transmission/reception data...
Page 377 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 11 - 48 Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3...
Page 378 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 49 Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, refer to Figure 11 - 43 . (Select buffer empty interrupt) SAU default setting <1> Setting storage data and number of data for transmission/reception...
Page 379: Slave Transmission
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.5.4 Slave transmission Slave transmission is that the R9A02G015 microcontroller transmits data to another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 Target channel...
Page 380 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11 - 50 Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00, CSI01) Serial mode register mn (SMRmn) CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 SMRmn...
Page 381 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11 - 51 Initial Setting Procedure for Slave Transmission Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 382 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 53 Procedure for Resuming Slave Transmission Starting setting for resumption Wait until stop the communication target (master) or operation completed. Completing master (Essential) preparations? Disable data output of the target channel by setting...
Page 383 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 11 - 54 Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2...
Page 384 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 55 Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication For the initial setting, refer to Figure 11 - 51 . (Select transfer end interrupt) SAU default setting Set storage area and the number of data for transmit data...
Page 385 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Processing flow (in continuous transmission mode) Figure 11 - 56 Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <6> STmn SEmn SDRmn Transmit data 2...
Page 386 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 57 Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, refer to Figure 11 - 51 . (Select buffer empty interrupt) SAU default setting <1> Set storage area and the number of data for transmit data...
Page 387: Slave Reception
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.5.5 Slave reception Slave reception is that the R9A02G015 microcontroller receives data from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 Target channel...
Page 388 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11 - 58 Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI01) Serial mode register mn (SMRmn) CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 SMRmn...
Page 389 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11 - 59 Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 390 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 61 Procedure for Resuming Slave Reception Starting setting for resumption Wait until stop the communication target (master) or operation completed. Completing master (Essential) preparations? Disable clock output of the target channel by...
Page 391 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 11 - 62 Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Receive data 1...
Page 392 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 63 Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication For the initial setting, refer to Figure 11 - 59 . (Select transfer end interrupt) SAU default setting Clear storage area setting and the number of receive data...
Page 393: Slave Transmission/Reception
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.5.6 Slave transmission/reception Slave transmission/reception is that the R9A02G015 microcontroller transmits/receives data to/from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 Target channel...
Page 394 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11 - 64 Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01) Serial mode register mn (SMRmn) CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 SMRmn...
Page 395 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11 - 65 Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 396 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 67 Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Wait until stop the communication target (master) or operation completed. Completing master (Essential) preparations? Disable data output of the target channel by setting...
Page 397 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 11 - 68 Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2...
Page 398 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 69 Flowchart of Slave Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication For the initial setting, refer to Figure 11 - 65 . (Select transfer end interrupt) SAU default setting Setting storage area and number of data for transmission/reception data...
Page 399 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 11 - 70 Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3...
Page 400 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 71 Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, refer to Figure 11 - 65 . (Select buffer empty interrupt) <1> SAU default setting Setting storage area and number of data for transmission/reception...
Page 401: Snooze Mode Function
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.5.7 SNOOZE mode function SNOOZE mode makes CSI operate reception by SCKp pin input detection while the STOP mode. Normally CSI stops communication in the STOP mode. But, using the SNOOZE mode makes reception CSI operate unless the CPU operation by detecting SCKp pin input.
Page 402 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 73 Flowchart of SNOOZE Mode Operation (once startup) SNOOZE operation TSFmn = 0 for all channels? <1> Write STm0 bit to 1 Become the operation STOP status (SEm0 = 0) SMRm0, SCRm0: Communication setting...
Page 403 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (2) SNOOZE mode operation (continuous startup) Figure 11 - 74 Timing Chart of SNOOZE Mode Operation (continuous startup) (Type 1: DAPmn = 0, CKPmn = 0) CPU operation Normal operation STOP mode SNOOZE mode...
Page 404 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 75 Flowchart of SNOOZE Mode Operation (continuous startup) SNOOZE operation TSFmn = 0 for all channels? <1> Write STm0 bit to 1 Become the operation STOP status (SEm0 = 0) SMRm0, SCRm0: Communication setting...
Page 405: Calculating Transfer Clock Frequency
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.5.8 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01) communication can be calculated by the following expressions. (1) Master (Transfer clock frequency) = {Operation clock (f ) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz]...
Page 406 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Table 11 - 2 Selection of Operation Clock For 3-Wire Serial I/O SMRmn SPSm Register Note Operation Clock (f Register CKSmn = 24 MHz × × × × 24 MHz × × × ×...
Page 407: Procedure For Processing Errors That Occurred During 3-Wire Serial I/O (Csi00, Csi01) Communication
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01) communication The procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01) communication is described in Figure 11 - 76.
Page 408: Operation Of Uart (Uart0) Communication
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.6 Operation of UART (UART0) Communication This is a start-stop synchronization function using two lines: serial data transmission (TxD) and serial data reception (RxD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
Page 409 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT UART0 uses channels 0 and 1 of SAU0. • 32-pin products Unit Channel Used as CSI Used as UART Used as Simplified I CSI00 UART0 IIC00 CSI01 IIC01 Select any function for each channel. Only the selected function is possible. If UART0 is selected for channels 0 and 1 of unit 0, for example, these channels cannot be used for CSI00 and IIC00.
Page 410: Uart Transmission
CHAPTER 11 SERIAL ARRAY UNIT 11.6.1 UART transmission UART transmission is an operation to transmit data from the R9A02G015 microcontroller to another device asynchronously (start-stop synchronization). Of two channels used for UART, the even channel is used for UART transmission.
Page 411: Register Setting
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11 - 77 Example of Contents of Registers for UART Transmission of UART (UART0) (1/2) Serial mode register mn (SMRmn) CKSmn CCSmn MDmn2 MDmn1 MDmn0 SMRmn Operation clock (f ) of channel n...
Page 412 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 78 Example of Contents of Registers for UART Transmission of UART (UART0) (2/2) Serial output register m (SOm)... Sets only the bits of the target channel. CKOm1 CKOm0 SOm1 SOm0 ×...
Page 413: Operation Procedure
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11 - 79 Initial Setting Procedure for UART Transmission Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 414 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 81 Procedure for Resuming UART Transmission Starting setting for resumption Wait until stop the communication target or communication operation completed Completing master (Essential) preparations? Disable data output of the target channel by setting...
Page 415 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 11 - 82 Timing Chart of UART Transmission (in Single-Transmission Mode) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 TxDq pin Transmit data 1...
Page 416 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 83 Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication For the initial setting, refer to Figure 11 - 79 . (Select transfer end interrupt) SAU default setting Set data for transmission and the number of data. Clear...
Page 417 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 11 - 84 Timing Chart of UART Transmission (in Continuous Transmission Mode) <1> SSmn <6> STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3...
Page 418 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 85 Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication For the initial setting, refer to Figure 11 - 79 . <1> (Select buffer empty interrupt) SAU default setting Set data for transmission and the number of data.
Page 419: Uart Reception
CHAPTER 11 SERIAL ARRAY UNIT 11.6.2 UART reception UART reception is an operation wherein the R9A02G015 microcontroller asynchronously receives data from another device (start-stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set.
Page 420 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11 - 86 Example of Contents of Registers for UART Reception of UART (UART0) (1/2) Serial mode register mn (SMRmn) CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 SMRmn Operation clock (f...
Page 421 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 87 Example of Contents of Registers for UART Reception of UART (UART0) (2/2) Serial output register m (SOm)... The register that not used in this mode. CKOm1 CKOm0 SOm1 SOm0 ×...
Page 422 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11 - 88 Initial Setting Procedure for UART Reception Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply. Setting the SPSm register Set the operation clock.
Page 423 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 90 Procedure for Resuming UART Reception Starting setting for resumption Stop the target for communication or wait until Completing communication completes its communication operation. (Essential) target preparations? Re-set the register to change the operation clock...
Page 424: Processing Flow
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow Figure 11 - 91 Timing Chart of UART Reception SSmn STmn SEmn Receive data 3 SDRmn Receive data 1 Receive data 2 RxDq pin Receive data 1 Receive data 2 Receive data 3...
Page 425 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 92 Flowchart of UART Reception Starting UART communication For the initial setting, refer to Figure 11 - 88 . (setting to mask for error interrupt) SAU default setting Setting storage area of the receive data, number of communication data...
Page 426: Snooze Mode Function
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.6.3 SNOOZE mode function The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP mode. Normally the UART stops communication in the STOP mode. However, using the SNOOZE mode enables the UART to perform reception operations without CPU operation.
Page 427 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Table 11 - 3 Baud Rate Setting for UART Reception in SNOOZE Mode Baud Rate for UART Reception in SNOOZE Mode High-speed On-chip Baud Rate of 4800 bps Oscillator (f Operation Clock Maximum Permissible...
Page 428 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (1) SNOOZE mode operation (EOCm1 = 0, SSECm = 0/1) Because of the setting of EOCm1 = 0, even though a communication error occurs, an error interrupt (INTSREq) is not generated, regardless of the setting of the SSECm bit. A transfer end interrupt (INTSRq) will be generated.
Page 429 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (2) SNOOZE mode operation (EOCm1 = 1, SSECm = 0: Error interrupt (INTSREq) generation is enabled) Because EOCm1 = 1 and SSECm = 0, an error interrupt (INTSREq) is generated when a communication error occurs.
Page 430 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 95 Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0) Setting start Does TSFmn = 0 on all channels? Writing 1 to the STmn bit The operation of all channels is also stopped to switch to the <1>...
Page 431 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (3) SNOOZE mode operation (EOCm1 = 1, SSECm = 1: Error interrupt (INTSREq) generation is stopped) Because EOCm1 = 1 and SSECm = 1, an error interrupt (INTSREq) is not generated when a communication error occurs.
Page 432 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 97 Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1) Setting start Does TSFmn = 0 on all channels? SIRm1 = 0007H Clear the all error flags. Writing 1 to the STmn bit The operation of all channels is also stopped to switch to the <1>...
Page 433 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Caution If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the PEFm1, FEFm1, or OVFm1 flag is not set and an error interrupt (INTSREq) is not generated. Therefore, when the setting of SSECm = 1 is made, clear the PEFm1, FEFm1, or OVFm1 flag before setting the SWCm bit to 1 and read the value in SDRm1[7:0] (RxDq register) (8 bits) or SDRm1[8:0] (9 bits).
Page 434: Calculating Baud Rate
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.6.4 Calculating baud rate (1) Baud rate calculation expression The baud rate for UART (UART0 to UART3) communication can be calculated by the following expressions. (Baud rate) = {Operation clock (f ) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [bps] Caution Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B, 0000001B) is prohibited.
Page 435 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Table 11 - 4 Selection of Operation Clock For UART SMRmn SPSm Register Note Operation Clock (f Register CKSmn = 24 MHz × × × × 24 MHz × × × × 12 MHz ×...
Page 436 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (2) Baud rate error during transmission The baud rate error of UART (UART0) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
Page 437 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UART0) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
Page 438: Procedure For Processing Errors That Occurred During Uart (Uart0) Communication
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.6.5 Procedure for processing errors that occurred during UART (UART0) communication The procedure for processing errors that occurred during UART (UART0) communication is described in Figures 11 - 99 and 11 - 100. Figure 11 - 99 Processing Procedure in Case of Parity Error or Overrun Error...
Page 439: Operation Of Simplified I 2 C (Iic00, Iic01) Communication
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.7 Operation of Simplified I C (IIC00, IIC01) Communication This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This communication function is designed to execute single communication with devices such as EEPROM, flash memory, and A/D converter, and therefore, can be used only by the master.
Page 440 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT The channel supporting simplified I C (IIC00, IIC01) is channels 0 and 1 of SAU0. • 32-pin products Unit Channel Used as CSI Used as UART Used as Simplified I CSI00 IIC00 UART0 CSI01...
Page 441: Address Field Transmission
Note 2. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the electrical specifications (see ELECTRICAL SPECIFICATIONS in the R9A02G015 Data Sheet (R19DS0101E)). Remark m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01 R19UH0112EJ0100 Rev.1.00...
Page 442: Register Setting
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11 - 101 Example of Contents of Registers for Address Field Transmission of Simplified I C (IIC00, IIC01) Serial mode register mn (SMRmn) STSmn SISmn0 CKSmn CCSmn MDmn2 MDmn1 MDmn0...
Page 443 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11 - 102 Initial Setting Procedure for Address Field Transmission Starting initial setting Release the serial array unit from the reset status Setting the PER0 register and start clock supply.
Page 444: Processing Flow
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow Figure 11 - 103 Timing Chart of Address Field Transmission SSmn SEmn SOEmn SDRmn Address field transmission SCLr output CKOmn bit manipulation SDAr output SOmn bit manipulation Address SDAr input Shift...
Page 445 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 104 Flowchart of Address Field Transmission Transmitting address field For the initial setting, refer to Figure 11 - 102 . Default setting Writing 0 to the SOmn bit Setting 0 to the SOmn bit...
Page 446: Data Transmission
Note 2. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the electrical specifications (see ELECTRICAL SPECIFICATIONS in the R9A02G015 Data Sheet (R19DS0101E)). Remark m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01 R19UH0112EJ0100 Rev.1.00...
Page 447 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11 - 105 Example of Contents of Registers for Data Transmission of Simplified I C (IIC00, IIC01) Serial mode register mn (SMRmn)... Do not manipulate this register during data transmission/reception.
Page 448 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (2) Processing flow Figure 11 - 106 Timing Chart of Data Transmission “L” SSmn SEmn “H” SOEmn “H” SDRmn Transmit data 1 SCLr output SDAr output SDAr input Shift Shift operation register mn INTIICr...
Page 449: Data Reception
Note 2. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the electrical specifications (see ELECTRICAL SPECIFICATIONS in the R9A02G015 Data Sheet (R19DS0101E)). Remark m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01 R19UH0112EJ0100 Rev.1.00...
Page 450 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11 - 108 Example of Contents of Registers for Data Reception of Simplified I C (IIC00, IIC01) Serial mode register mn (SMRmn)... Do not manipulate this register during data transmission/reception.
Page 451 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT (2) Processing flow Figure 11 - 109 Timing Chart of Data Reception When starting data reception SSmn STmn SEmn SOEmn “H” TXEmn, TXEmn = 1 / RXEmn = 0 TXEmn = 0 / RXEmn = 1...
Page 452 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Figure 11 - 110 Flowchart of Data Reception Address field transmission completed Data reception completed Stop operation for rewriting Writing 1 to the STmn bit SCRmn register. Set to receive only the operating Writing 0 to the TXEmn bit, and 1 to the RXEmn bit mode of the channel.
Page 453: Stop Condition Generation
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.7.4 Stop condition generation After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released. (1) Processing flow Figure 11 - 111 Timing Chart of Stop Condition Generation...
Page 454: Calculating Transfer Rate
C bus specifications. In addition, it may be required to set an appropriate transfer rate so that the data setup time (reception) of R9A02G015 meet the I2C bus specifications. Make sure that the SDRmn[15:9] value satisfies the I C bus specifications.
Page 455 R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT Table 11 - 5 Selection of Operation Clock For Simplified I SMRmn SPSm Register Note Operation Clock (f Register CKSmn = 24 MHz × × × × 24 MHz × × × × 12 MHz ×...
Page 456: Procedure For Processing Errors That Occurred During Simplified I 2 C (Iic00, Iic01) Communication
R9A02G015 CHAPTER 11 SERIAL ARRAY UNIT 11.7.6 Procedure for processing errors that occurred during simplified I (IIC00, IIC01) communication The procedure for processing errors that occurred during simplified I C (IIC00, IIC01) communication is described in Figures 11 - 113 and 11 - 114.
Page 457: Serial Interface Iica
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA CHAPTER 12 SERIAL INTERFACE IICA The number of channels of the serial Interface IICA differs, depending on the product. With USB Without USB 32-pin 32-pin Channels 2 ch 3 ch 12.1 Functions of Serial Interface IICA Serial interface IICA has the following three modes.
Page 458 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 1 Block Diagram of Serial Interface IICA Internal bus IICA status register 0 (IICS0) WUP0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IICA control register 00 Controller for (IICCTL00) STOP mode...
Page 459 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 2 shows a serial bus configuration example. Figure 12 - 2 Serial Bus Configuration Example Using I C Bus Serial data bus Master CPU2 Master CPU1 SDAAn SDAAn Slave CPU1 Slave CPU2...
Page 460: Configuration Of Serial Interface Iica
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table 12 - 1 Configuration of Serial Interface IICA Item Configuration Registers IICA shift register n (IICAn) Slave address register n (SVAn)
Page 461 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (2) Slave address register n (SVAn) This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode. The SVAn register can be set by an 8-bit memory manipulation instruction.
Page 462 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (9) ACK generator, stop condition detector, start condition detector, and ACK detector These circuits generate and detect each status. (10) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
Page 463: Registers Controlling Serial Interface Iica
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.3 Registers Controlling Serial Interface IICA Serial interface IICA is controlled by the following eight registers. • Peripheral enable register 0 (PER0) • IICA control register n0 (IICCTLn0) • IICA flag register n (IICFn) •...
Page 464: Peripheral Enable Register 0 (Per0)
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
Page 465 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 6 Format of IICA control register n0 (IICCTLn0) (1/4) Address: F0230H (IICCTL00), F0238H (IICCTL10), F0240H (IICCTL20) After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICCTLn0 IICEn LRELn...
Page 466 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 7 Format of IICA control register n0 (IICCTLn0) (2/4) SPIEn Enable/disable generation of interrupt request when stop condition is detected Note 1 Disable Enable If the WUPn bit of IICA control register n1 (IICCTLn1) is 1, no stop condition interrupt will be generated even if SPIEn =...
Page 467 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 8 Format of IICA control register n0 (IICCTLn0) (3/4) STTn Start condition trigger Notes 1, 2 Do not generate a start condition. When bus is released (in standby state, when IICBSYn = 0): If this bit is set (1), a start condition is generated (startup as the master).
Page 468 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 9 Format of IICA control register n0 (IICCTLn0) (4/4) Note Stop condition trigger SPTn Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). Cautions concerning set timing •...
Page 469: Iica Status Register N (Iicsn)
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.3.3 IICA status register n (IICSn) This register indicates the status of I The IICSn register is read by a 1-bit or 8-bit memory manipulation instruction only when STTn = 1 and during the wait period.
Page 470 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 11 Format of IICA status register n (IICSn) (2/3) EXCn Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXCn = 0) Condition for setting (EXCn = 1) •...
Page 471: Iica Flag Register N (Iicfn)
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 12 Format of IICA status register n (IICSn) (3/3) ACKDn Detection of acknowledge (ACK) Acknowledge was not detected. Acknowledge was detected. Condition for clearing (ACKDn = 0) Condition for setting (ACKDn = 1) •...
Page 472 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 13 Format of IICA flag register n (IICFn) Note Address: FFF52H (IICF0), FFF56H (IICF1), FFF62H (IICF2) After reset: 00H Symbol <7> <6> <1> <0> IICFn STCFn IICBSYn STCENn IICRSVn STCFn STTn clear flag...
Page 473: Iica Control Register N1 (Iicctln1)
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.3.5 IICA control register n1 (IICCTLn1) This register is used to set the operation mode of I C and detect the statuses of the SCLAn and SDAAn pins. The IICCTLn1 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLDn and DADn bits are read-only.
Page 474 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 15 Format of IICA control register n1 (IICCTLn1) (2/2) CLDn Detection of SCLAn pin level (valid only when IICEn = 1) The SCLAn pin was detected at low level. The SCLAn pin was detected at high level.
Page 475: Iica Low-Level Width Setting Register N (Iicwln)
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.3.6 IICA low-level width setting register n (IICWLn) This register is used to set the low-level width (t ) of the SCLAn pin signal that is output by serial interface IICA and to control the SDAAn pin signal.
Page 476: Port Mode Registers 6, 7 (Pm6, Pm7)
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.3.8 Port mode registers 6, 7 (PM6, PM7) These registers set the input/output of ports 6 and 7 in 1-bit units. When using the P60/SCLA0 (P62/SCLA1, P70/SCLA2) pin as clock I/O and the P61/SDAA0 (P63/SDAA1, P71/SDAA2) pin as serial data I/O, clear PM60 (PM62, PM70) and PM61 (PM63, PM71), and the output latches of P60 (P62, P70) and P61 (P63, P71) to 0.
Page 477: I 2 C Bus Mode Functions
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.4 C Bus Mode Functions 12.4.1 Pin configuration The serial clock pin (SCLAn) and the serial data bus pin (SDAAn) are configured as follows. (1) SCLAn..This pin is used for serial clock input and output.
Page 478: Setting Transfer Clock By Using Iicwln And Iicwhn Registers
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.4.2 Setting transfer clock by using IICWLn and IICWHn registers (1) Setting transfer clock on master side Transfer clock = IICWL + IICWH + f At this time, the optimal setting values of the IICWLn and IICWHn registers are as follows.
Page 479 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Remark 1. Calculate the rise time (t ) and fall time (t ) of the SDAAn and SCLAn signals separately, because they differ depending on the pull-up resistance and wire load. Remark 2. IICWLn: IICA low-level width setting register n...
Page 480: I 2 C Bus Definitions And Control Methods
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.5 C Bus Definitions and Control Methods The I C bus’s serial data communication format and the signals used by the I C bus are described below. Figure 12 - 21 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I C bus’s...
Page 481: Addresses
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.
Page 482: Acknowledge (Ack)
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued.
Page 483: Stop Condition
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.5.5 Stop condition When the SCLAn pin is at high level, changing the SDAAn pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed.
Page 484: Wait
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLAn pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin.
Page 485 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 28 Wait (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKEn = 1) Master and slave both wait Master after output of ninth clock...
Page 486: Canceling Wait
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.5.7 Canceling wait The I C usually cancels a wait state by the following processing. • Writing data to the IICA shift register n (IICAn) • Setting bit 5 (WRELn) of IICA control register n0 (IICCTLn0) (canceling wait) Note •...
Page 487: Interrupt Request (Intiican) Generation Timing And Wait Control
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.5.8 Interrupt request (INTIICAn) generation timing and wait control The setting of bit 3 (WTIMn) of IICA control register n0 (IICCTLn0) determines the timing by which INTIICAn is generated and the corresponding wait control, as shown in Table 12 - 2.
Page 488: Address Match Detection Method
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (4) Wait cancellation method The four wait cancellation methods are as follows. • Writing data to the IICA shift register n (IICAn) • Setting bit 5 (WRELn) of IICA control register n0 (IICCTLn0) (canceling wait) Note •...
Page 489: 12.5.11 Extension Code
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.5.11 Extension code (1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag (EXCn) is set to 1 for extension code reception and an interrupt request (INTIICAn) is issued at the falling edge of the eighth clock.
Page 490: 12.5.12 Arbitration
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.5.12 Arbitration When several master devices simultaneously generate a start condition (when the STTn bit is set to 1 before the STDn bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs.
Page 491 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Table 12 - 4 Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing During address transmission At falling edge of eighth or ninth clock following byte Note 1...
Page 492: 12.5.13 Wakeup Function
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.5.13 Wakeup function The I C bus slave function is a function that generates an interrupt request signal (INTIICAn) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIICAn signal from occurring when addresses do not match.
Page 493 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 31 Flow When Setting WUPn = 0 upon Address Match (Including Extension Code Reception) STOP mode state INTIICAn = 1? WUPn = 0 Wait Wait for 5 f clocks. Reading IICSn Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA.
Page 494 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 32 When Operating as Master Device after Releasing STOP Mode other than by INTIICAn START SPIEn = 1 WUPn = 1 Wait for 3 f clocks. Wait STOP instruction STOP mode state...
Page 495: 12.5.14 Communication Reservation
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.5.14 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSVn) of IICA flag register n (IICFn) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released.
Page 496 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 33 shows the Communication Reservation Timing. Figure 12 - 33 Communication Reservation Timing Write to Program processing STTn = 1 IICAn Set SPDn Hardware processing Communication reservation STDn INTIICAn SCLAn SDAAn...
Page 497 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 35 Communication Reservation Protocol SET1 STTn Sets STTn flag (communication reservation) Define communication Defines that communication reservation is in effect reservation (defines and sets user flag to any part of RAM)
Page 498 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (2) When communication reservation function is disabled (bit 0 (IICRSVn) of IICA flag register n (IICFn) = 1) When bit 1 (STTn) of IICA control register n0 (IICCTLn0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated.
Page 499: 12.5.15 Cautions
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.5.15 Cautions (1) When STCENn = 0 Immediately after I C operation is enabled (IICEn = 1), the bus communication status (IICBSYn = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication.
Page 500: 12.5.16 Communication Operations
The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the R9A02G015 as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup.
Page 501 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (1) Master operation in single master system Figure 12 - 36 Master Operation in Single-Master System START Release the serial interface IICA from the reset status and start clock supply. Setting the PER0 register...
Page 502 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (2) Master operation in multimaster system Figure 12 - 37 Master Operation in Multi-Master System (1/3) START Setting the PER0 register Release the serial interface IICA from the reset status and start clock supply.
Page 503 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 38 Master Operation in Multi-Master System (2/3) Enables reserving communication. Prepares for starting communication STTn = 1 (generates a start condition). Note Secure wait time by software. Wait MSTSn = 1?
Page 504 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 39 Master Operation in Multi-Master System (3/3) Starts communication Writing IICAn (specifies an address and transfer direction). INTIICAn interrupt occurs? Waits for detection of ACK. MSTSn = 1? ACKDn = 1?
Page 505 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIICAn interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary.
Page 506 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA The main processing of the slave operation is explained next. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt.
Page 507 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICAn interrupt is explained below (processing is performed assuming that no extension code is used). The INTIICAn interrupt checks the status, and the following operations are performed.
Page 508: Timing Of I C Interrupt Request (Intiican) Occurrence
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.5.17 Timing of I C interrupt request (INTIICAn) occurrence The timing of transmitting or receiving data and generation of interrupt request signal INTIICAn, and the value of the IICA status register n (IICSn) when the INTIICAn signal is generated are shown below.
Page 509 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (1) Master device operation Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIMn = 0 SPTn = 1  AD6 to AD0 R/W ACK D7 to D0 D7 to D0 ▲1: IICSn = 1000×110B...
Page 510 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIMn = 0 STTn = 1 SPTn = 1   AD6 to AD0 R/W ACK D7 to D0...
Page 511 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIMn = 0 SPTn = 1  AD6 to AD0 R/W ACK D7 to D0 D7 to D0 ▲1: IICSn = 1010×110B ▲2: IICSn = 1010×000B...
Page 512 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (2) Slave device operation (slave address data reception) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIMn = 0 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 ▲1: IICSn = 0001×110B ▲2: IICSn = 0001×000B...
Page 513 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, matches with SVAn) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0...
Page 514 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= extension code)) AD6 to AD0 R/W ACK D7 to D0...
Page 515 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK D7 to D0...
Page 516 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIMn = 0...
Page 517 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, matches SVAn) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 R/W ACK D7 to D0 ▲1: IICSn = 0010×010B...
Page 518 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIMn = 0 (after restart, extension code reception) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0...
Page 519 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK D7 to D0...
Page 520 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (4) Operation without communication Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 00000001B Remark : Generated only when SPIEn = 1...
Page 521 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (ii) When WTIMn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 ▲1: IICSn = 0101×110B ▲2: IICSn = 0001×100B ▲3: IICSn = 0001××00B 4: IICSn = 00000001B Remark ▲: Always generated : Generated only when SPIEn = 1 ×...
Page 522 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (ii) When WTIMn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 ▲1: IICSn = 0110×010B ▲2: IICSn = 0010×110B ▲3: IICSn = 0010×100B ▲4: IICSn = 0010××00B 5: IICSn = 00000001B Remark ▲: Always generated...
Page 523 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA When arbitration loss occurs during transmission of extension code AD6 to AD0 R/W ACK D7 to D0 D7 to D0 ▲1: IICSn = 0110×010B Sets LRELn = 1 by software 2: IICSn = 00000001B Remark ▲: Always generated...
Page 524 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (ii) When WTIMn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 ▲1: IICSn = 10001110B ▲2: IICSn = 01000100B 3: IICSn = 00000001B Remark ▲: Always generated : Generated only when SPIEn = 1...
Page 525 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA (ii) Extension code AD6 to AD0 R/W ACK D7 to Dm AD6 to AD0 R/W ACK D7 to D0 ▲1: IICSn = 1000×110B ▲2: IICSn = 01100010B Sets LRELn = 1 by software 3: IICSn = 00000001B Remark ▲: Always generated...
Page 526 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIMn = 0 STTn = 1  AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 ▲1: IICSn = 1000×110B...
Page 527 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIMn = 0 STTn = 1  AD6 to AD0 R/W ACK D7 to D0 ▲1: IICSn = 1000×110B ▲2: IICSn = 1000×000B (Sets the WTIMn bit to 1)
Page 528 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIMn = 0 SPTn = 1  AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 ▲1: IICSn = 1000×110B...
Page 529: Timing Charts
R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA 12.6 Timing Charts When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit (bit 3 of the IICA status register n (IICSn)), which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 530 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 42 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4) (1) Start condition ~ address ~ data Master side Note 1 IICAn <5>...
Page 531 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA The meanings of <1> to <6> in (1) Start condition ~ address ~ data in Figure 12 - 42 are explained below. <1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn = 1 changes SDAAn from 1 to 0) is generated once the bus data line goes low (SDAAn).
Page 532 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 43 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/4) (3) Address ~ data ~ data Master side Note 1...
Page 533 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA The meanings of <3> to <10> in (3) Address ~ data ~ data in Figure 12 - 43 are explained below. Note <3> In the slave device if the address received matches the address (SVAn value) of a slave device , that slave device sends an ACK by hardware to the master device.
Page 534 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 44 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/4) (3) Data ~ data ~ stop condition Master side Note 1 IICAn <9>...
Page 535 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA The meanings of <7> to <15> in (3) Data ~ data ~ stop condition in Figure 12 - 44 are explained below. <7> After data transfer is completed, because of ACKEn = 1, the slave device sends an ACK by hardware to the master device.
Page 536 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 45 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4) (3) Data ~ restart condition ~ address Master side IICAn <iii>...
Page 537 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA The following describes the operations in Figure 12 - 45 (3) Data ~ restart condition ~ address. After the operations in steps <7> and <8>, the operations in steps <i> to <iii> are performed. These steps return the processing to step <iii>, the data transmission step.
Page 538 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 46 Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) (1) Start condition ~ address ~ data Master side IICAn <2>...
Page 539 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA The meanings of <1> to <7> in (1) Start condition ~ address ~ data in Figure 12 - 46 are explained below. <1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn =1 changes SDAAn from 1 to 0) is generated once the bus data line goes low (SDAAn).
Page 540 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 47 Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3) (3) Address ~ data ~ data Master side IICAn ACKDn...
Page 541 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA The meanings of <3> to <12> in (3) Address ~ data ~ data in Figure 12 - 47 are explained below. Note <3> In the slave device if the address received matches the address (SVAn value) of a slave device , that slave device sends an ACK by hardware to the master device.
Page 542 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA Figure 12 - 48 Example of Slave to Master Communication (When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3) (3) Data ~ data ~ stop condition Master side...
Page 543 R9A02G015 CHAPTER 12 SERIAL INTERFACE IICA The meanings of <8> to <19> in (3) Data ~ data ~ stop condition in Figure 12 - 48 are explained below. <8> The master device sets a wait status (SCLAn = 0) at the falling edge of the 8th clock, and issues an interrupt (INTIICAn: end of transfer).
Page 544: Usb 2.0 Host/Function Module (Usb)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) The availability of each pin of USB port, VBUS supply enable output, and overcurrent detection input differs, depending on the product. R9A02G0150 R9A02G0151 UDP0 pin —...
Page 545 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Table 13 - 1 USB module Specifications Item Specifications Features • USB Device Controller (UDC) and transceiver for USB 2.0 are incorporated. • The USB host controller and USB function controller are incorporated (can be switched by software).
Page 546: Configuration Of Usb 2.0 Host/Function Module
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.2 Configuration of USB 2.0 Host/Function Module The USB module consists of the following hardware. • USB 2.0 Host/Function Controller This controls the host/function supporting full-speed (12 Mbps) and low-speed (1.5 Mbps) transfer.
Page 547 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Table 13 - 2 USB module I/O Pins Pin Name Function UDP0 D+ I/O pin of USB port 0 This pin should be connected to the D+ pin of the USB bus.
Page 548 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 1 Block diagram of USB module UVBUSSEN0 UVBUSSEN1 UOVRCUR0 UOVRCUR1 I/O buffer USB internal power supply USB power supply Battery Charging Battery Charging detection controller UDP0 USB host/functiion controller...
Page 549: Registers Used In Usb 2.0 Host/Function Module
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3 Registers Used in USB 2.0 Host/Function Module Table 13 - 3 lists the USB Registers. Table 13 - 3 List of USB Registers (1/2) Register Name Symbol After Reset Address Access Size...
Page 550 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Table 13 - 3 List of USB Registers (2/2) Register Name Symbol After Reset Address Access Size Pipe 4 Control Register PIPE4CTR 0000H F0476H, F0477H Pipe 5 Control Register PIPE5CTR 0000H F0478H, F0479H...
Page 551: System Configuration Control Register (Syscfg), System Configuration Control Register 1 (Syscfg1)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.1 System configuration control register (SYSCFG), system configuration control register 1 (SYSCFG1) Figure 13 - 2 Format of System Configuration Control Register (SYSCFG) Address: F0400H, F0401H After reset: 0000H Symbol DPRP DMRP SYSCFG —...
Page 552 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) DPRPU Note USB port 0 D+ line resistor control Pulling up the line is disabled. Pulling up the line is enabled. Enables or disables pulling up the D+ line when the function controller function is selected.
Page 553 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 3 Format of System Configuration Control Register 1 (SYSCFG1) Address: F0402H, F0403H After reset: 0000H Symbol SYSCFG1 — — — — — — — CNEN — — DRPD —...
Page 554: System Configuration Status Register N (Sysstsn) (N = 0, 1)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.2 System configuration status register n (SYSSTSn) (n = 0, 1) Figure 13 - 4 Format of System Configuration Status Register n (SYSSTSn) (n = 0, 1) Address: F0404H, F0405H (SYSSTS0), F0406H, F0407H (SYSSTS1) After reset: X00X0000 00X00000B...
Page 555: Device State Control Register N (Dvstctrn) (N = 0, 1)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.3 Device state control register n (DVSTCTRn) (n = 0, 1) Figure 13 - 5 Format of Device State Control Register 0 (DVSTCTR0) Address: F0408H, F0409H After reset: 0000H Symbol VBUS RWUP...
Page 556 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) USBRST USB port 0 USB bus reset output USB bus reset signal is not output. USB bus reset signal is output. Controls the USB bus reset signal output when the host controller function is selected.
Page 557 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) RHST2 RHST1 RHST0 USB port 0 USB bus reset status • When the host controller function is selected Communication speed not determined (powered state or no connection) USB bus reset in progress...
Page 558 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 6 Format of Device State Control Register 1 (DVSTCTR1) Address: F040AH, F040BH After reset: 0000H Symbol VBUS RWUP USBR RESU RHST RHST RHST DVSTCTR1 — — — — —...
Page 559 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) RESUME USB port 1 resume output Resume signal is not output. Resume signal is output. Controls the resume signal output when the host controller function is selected. Setting the RESUME bit to 1 allows the USB module to drive the port to the K-state and output the resume signal.
Page 560: Cfifo Port Register (Cfifom), Dnfifo Port Register (Dnfifom) (N = 0, 1)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.4 CFIFO port register (CFIFOM), DnFIFO port register (DnFIFOM) (n = 0, 1) Figure 13 - 7 Format of CFIFO Port Register (CFIFOM) Address: F0414H, F0415H After reset: 0000H Symbol CFIFOM CFIFO[15:0]...
Page 561 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 8 Format of DnFIFO Port Register (DnFIFOM) (n = 0, 1) Address: F0418H, F0419H (D0FIFOM), F041CH, F041DH (D1FIFOM) After reset: 0000H Symbol DnFIFOM DnFIFO[15:0] DnFIFO[15:0] FIFO port Addresses for CPU transfers using the DnFIFO port.
Page 562: Cfifo Port Select Register (Cfifosel), Dnfifo Port Select Register (Dnfifosel) (N = 0, 1)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.5 CFIFO port select register (CFIFOSEL), DnFIFO port select register (DnFIFOSEL) (n = 0, 1) Figure 13 - 9 Format of CFIFO Port Select Register (CFIFOSEL) Address: F0420H, F0421H After reset: 0000H...
Page 563 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Bits 7, 6 Nothing is assigned — The write value must be 0. The read value is 0. — ISEL CFIFO port access direction when DCP is selected Reading from the buffer memory is selected...
Page 564 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 10 Format of DnFIFO port select register (DnFIFOSEL) (n = 0, 1) Address: F0428H, F0429H (D0FIFOSEL), F042CH, F042DH (D1FIFOSEL) After reset: 0000H Symbol DCLR BIGE CURPI CURP CURP CURP RCNT REW —...
Page 565 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) DnFIFO port access bit width 8-bit width 16-bit width Specifies the bit width for accessing the DnFIFO port. When the selected pipe is in the receiving direction, once reading data is started after setting the MBW bit, this bit should not be modified until all the data has been read.
Page 566: Cfifo Port Control Register (Cfifoctr), Dnfifo Port Control Register (Dnfifoctr) (N = 0, 1)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.6 CFIFO port control register (CFIFOCTR), DnFIFO port control register (DnFIFOCTR) (n = 0, 1) Figure 13 - 11 Format of CFIFO Port Control Register (CFIFOCTR) Address: F0422H, F0423H After reset: 0000H...
Page 567 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) DTLN[8:0] Receive data length The DTLN[8:0] bits indicate the length of the receive data. While the FIFO buffer is being read, the DTLN[8:0] bits indicate different values depending on the RCNT bit value as described below.
Page 568 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 12 Format of DnFIFO Port Control Register (DnFIFOCTR) (n = 0, 1) Address: F042AH, F042BH (D0FIFOCTR), F042EH, F042FH (D1FIFOCTR) After reset: 0000H Symbol BVAL BCLR FRDY — — —...
Page 569 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) DTLN[8:0] Receive data length The DTLN[8:0] bits indicate the length of the receive data. While the FIFO buffer is being read, the DTLN[8:0] bits indicate different values depending on the RCNT bit value as described below.
Page 570: Interrupt Enable Register 0 (Intenb0)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.7 Interrupt enable register 0 (INTENB0) Figure 13 - 13 Format of Interrupt Enable Register 0 (INTENB0) Address: F0430H, F0431H After reset: 0000H Symbol BEMP NRDY BRDY INTENB0 VBSE RSME SOFE DVSE CTRE —...
Page 571 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Bits 7 to 0 Nothing is assigned — The write value must be 0. The read value is 0. — Note The RSME, DVSE, and CTRE bits can be set to 1 only when the function controller function is selected; do not set these bits to 1 (interrupt output enabled) when the host controller function is selected.
Page 572: Interrupt Enable Register N (Intenbn) (N = 1, 2)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.8 Interrupt enable register n (INTENBn) (n = 1, 2) Figure 13 - 14 Format of Interrupt Enable Register 1 (INTENB1) Address: F0432H, F0433H After reset: 0000H Symbol OVRC BCHG DTCH ATTCH...
Page 573 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Bits 3 to 1 Nothing is assigned — The write value must be 0. The read value is 0. — PDDETINTE USB port 0 Portable Device detection interrupt enable Interrupt output disabled Interrupt output enabled Enables or disables the USB interrupt output when the PDDETINT interrupt is detected.
Page 574 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 15 Format of Interrupt Enable Register 2 (INTENB2) Address: F0434H, F0435H After reset: 0000H Symbol OVRC BCHG DTCH ATTCH EOFE PDDET INTENB2 — — — — — — —...
Page 575: Brdy Interrupt Enable Register (Brdyenb)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.9 BRDY interrupt enable register (BRDYENB) Figure 13 - 16 Format of BRDY Interrupt Enable Register (BRDYENB) Address: F0436H, F0437H After reset: 0000H Symbol PIPE7 PIPE6 PIPE5 PIPE4 PIPE0 — — —...
Page 576: Bemp Interrupt Enable Register (Bempenb)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.11 BEMP interrupt enable register (BEMPENB) Figure 13 - 18 Format of BEMP Interrupt Enable Register (BEMPENB) Address: F043AH, F043BH After reset: 0000H Symbol PIPE7 PIPE6 PIPE5 PIPE4 PIPE0 — — —...
Page 577: Sof Output Configuration Register (Sofcfg)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.12 SOF output configuration register (SOFCFG) Figure 13 - 19 Format of SOF Output Configuration Register (SOFCFG) Address: F043CH, F043DH After reset: 0000H Symbol TRNE BRDY EDGE SOFCFG — — — —...
Page 578: Interrupt Status Register 0 (Intsts0)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.13 Interrupt status register 0 (INTSTS0) Figure 13 - 20 Format of Interrupt Status Register 0 (INTSTS0) Address: F0440H, F0441H After reset: 00000000 X0000000B Symbol INTSTS0 VBINT RESM SOFR DVST CTRT BEMP NRDY BRDY VBSTS DVSQ2 DVSQ1 DVSQ0 VALID CTSQ2 CTSQ1 CTSQ0...
Page 579 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) CTRT Note 3 Control transfer stage transition interrupt status Control transfer stage transition interrupts are not generated Note 2 Control transfer stage transition interrupts are generated. When the function controller function is selected, the USB module updates the CTSQ2 to CTSQ0 value and sets the CTRT bit to 1 on detecting a change in the control transfer stage.
Page 580 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) DVSQ2 DVSQ1 DVSQ1 Device state Powered state Default state Address state Configured state Suspended state These bits indicate the device status. When the host controller function is selected, the read value is invalid.
Page 581: Interrupt Status Register N (Intstsn) (N = 1, 2)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.14 Interrupt status register n (INTSTSn) (n = 1, 2) Figure 13 - 21 Format of Interrupt Status Register 1 (INTSTS1) Address: F0442H, F0443H After reset: XX0X0000 00000000B Symbol OVRC EOFE PDDET...
Page 582 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) ATTCH USB port 0 connection detection interrupt status Connection detection interrupts are not generated. Note 2 Connection detection interrupts are generated. Indicates the status of the ATTCH interrupt when the host controller function is selected.
Page 583 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Bits 3 to 1 Nothing is assigned — The write value must be 0. The read value is 0. — PDDETINT USB port 0 Portable Device detection interrupt status PDDETINT interrupts are not generated.
Page 584 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 22 Format of Interrupt Status Register 2 (INTSTS2) Address: F0444H, F0445H After reset: X00X0000 00000000B Symbol OVRC EOFE PDDET INTSTS2 BCHG — DTCH ATTCH — — — — —...
Page 585 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) ATTCH USB port 1 connection detection interrupt status Connection detection interrupts are not generated. Note 2 Connection detection interrupts are generated. Indicates the status of the ATTCH interrupt when the host controller function is selected.
Page 586: Brdy Interrupt Status Register (Brdysts)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.15 BRDY interrupt status register (BRDYSTS) Figure 13 - 23 Format of BRDY Interrupt Status Register (BRDYSTS) Address: F0446H, F0447H After reset: 0000H Symbol PIPE7 PIPE6 PIPE5 PIPE4 PIPE0 BRDYSTS — —...
Page 587: Bemp Interrupt Status Register (Bempsts)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.17 BEMP interrupt status register (BEMPSTS) Figure 13 - 25 Format of BEMP Interrupt Status Register (BEMPSTS) Address: F044AH, F044BH After reset: 0000H Symbol PIPE7 PIPE6 PIPE5 PIPE4 PIPE0 BEMPSTS — —...
Page 588: Usb Address Register (Usbaddr)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.19 USB address register (USBADDR) Figure 13 - 27 Format of USB Address Register (USBADDR) Address: F0450H, F0451H After reset: 0000H Symbol — — — — — — — — — USBADDR[6:0]...
Page 589: Usb Request Type Register (Usbreq)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.20 USB request type register (USBREQ) Figure 13 - 28 Format of USB Request Type Register (USBREQ) Address: F0454H, F0455H After reset: 0000H Symbol BREQUEST[7:0] BMREQUESTTYPE[7:0] USBREQ BREQUEST[7:0] Request These bits store the USB request bRequest value.
Page 590: Usb Request Index Register (Usbindx)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.22 USB request index register (USBINDX) Figure 13 - 30 Format of USB Request Index Register (USBINDX) Address: F0458H, F0459H After reset: 0000H Symbol WINDEX[15:0] USBINDX WINDEX[15:0] Index These bits store the USB request wIndex value.
Page 591: Dcp Configuration Register (Dcpcfg)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.24 DCP configuration register (DCPCFG) Figure 13 - 32 Format of DCP Configuration Register (DCPCFG) Address: F045CH, F045DH After reset: 0000H Symbol SHTNA DCPCFG — — — — — — — —...
Page 592: Dcp Maximum Packet Size Register (Dcpmaxp)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.25 DCP maximum packet size register (DCPMAXP) Figure 13 - 33 Format of DCP Maximum Packet Size Register (DCPMAXP) Address: F045EH, F045FH After reset: 0040H Symbol DEVSE DEVSE DEVSE DCPMAXP — —...
Page 593: Dcp Control Register (Dcpctr)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.26 DCP control register (DCPCTR) Figure 13 - 34 Format of DCP Control Register (DCPCTR) Address: F0460H, F0461H After reset: 0040H Symbol SURE SURE SQCL SQMO DCPCTR BSTS — — — —...
Page 594 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) SQCLR Note 2 Toggle bit clear Invalid Note 3 Specifies DATA0. Specifies DATA0 as the expected value of the sequence toggle bit for the next transaction during the DCP transfer. The SQCLR bit always indicates 0.
Page 595 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) CCPL Control transfer end enable Completion of control transfer is disabled. Completion of control transfer is enabled. When the function controller function is selected, setting the CCPL bit to 1 enables the status stage of the control transfer to be completed.
Page 596: Pipe Window Select Register (Pipesel)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.27 Pipe window select register (PIPESEL) Figure 13 - 35 Format of Pipe Window Select Register (PIPESEL) Address: F0464H, F0465H After reset: 0000H Symbol PIPES PIPES PIPES PIPES PIPESEL — — —...
Page 597: Pipe Configuration Register (Pipecfg)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.28 Pipe configuration register (PIPECFG) Figure 13 - 36 Format of Pipe Configuration Register (PIPECFG) Address: F0468H, F0469H After reset: 0000H Symbol SHTNA PIPECFG TYPE1 TYPE0 — — — BFRE DBLB —...
Page 598 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) SHTNAK Note 1 Pipe disabled at end of transfer Pipe continued at the end of transfer Pipe disabled at the end of transfer Specifies whether to modify PID to NAK upon the end of transfer when the selected pipe is in the receiving direction.
Page 599: Pipe Maximum Packet Size Register (Pipemaxp)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.29 Pipe maximum packet size register (PIPEMAXP) Figure 13 - 37 Format of Pipe Maximum Packet Size Register (PIPEMAXP) Address: F046CH, F046DH After reset: 0000H Symbol DEVSE DEVSE DEVSE PIPEMAXP — —...
Page 600: Pipe Cycle Control Register (Pipeperi)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.30 Pipe cycle control register (PIPEPERI) Figure 13 - 38 Format of Pipe Cycle Control Register (PIPEPERI) Address: F046EH, F046FH After reset: 0000H Symbol — — — — — — — —...
Page 601: Pipen Control Registers (Pipenctr) (N = 4 To 7)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.31 PIPEn control registers (PIPEnCTR) (n = 4 to 7) Figure 13 - 39 Format of PIPEn Control Registers (PIPEnCTR) (n = 4, 5) Address: F0476H, F0477H (PIPE4CTR), F0478H, F0479H (PIPE5CTR) After reset: 0000H...
Page 602 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) ACLRM Note 2 Auto buffer clear mode Disabled Enabled (all buffers are initialized) Enables or disables auto buffer clear mode for the relevant pipe. To delete the information in the FIFO buffer assigned to the relevant pipe completely, write 1 and then 0 to the ACLRM bit continuously.
Page 603 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) PID1 PID0 Response PID NAK response BUF response (depending on the buffer state) STALL response STALL response The PID1 and PID0 bits specify the response type for the next transaction of the relevant pipe.
Page 604 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Table 13 - 8 Operation of BSTS Bit DIR Bit BFRE Bit DCLRM Bit BSTS Bit Function 1 when the received data can be read from the FIFO buffer; 0 when the received data has been completely read from the FIFO buffer.
Page 605 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Table 13 - 11 Operation of USB Module depending on PID Bit Setting (When Function Controller Function is Selected) PID Bits Transfer Direction Transfer Type Operation of USB Module (PID1 and PID0)
Page 606 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) SQCLR Note 2 Toggle bit clear Invalid Note 3 Specifies DATA0. The SQCLR bit should be set to 1 to clear the expected value (to set DATA0 as the expected value) of the sequence toggle bit for the next transaction of the relevant pipe.
Page 607 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) PID1 PID0 Response PID NAK response BUF response (depending on the buffer state) STALL response STALL response The PID1 and PID0 bits specify the response type for the next transaction of the relevant pipe.
Page 608: Pipen Transaction Counter Enable Registers (Pipentre) (N = 4, 5)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.32 PIPEn transaction counter enable registers (PIPEnTRE) (n = 4, 5) Figure 13 - 41 Format of PIPEn Transaction Counter Enable Registers (PIPEnTRE) (n = 4, 5) Address: F049CH, F049DH (PIPE4TRE), F04A0H, F04A1H (PIPE5TRE)
Page 609: Pipen Transaction Counter Registers (Pipentrn) (N = 4, 5)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.33 PIPEn transaction counter registers (PIPEnTRN) (n = 4, 5) Figure 13 - 42 Format of PIPEn Transaction Counter Registers (PIPEnTRN) (4, 5) Address: F049EH, F049FH (PIPE4TRN), F04A2H, F04A3H (PIPE5TRN) After reset: 0000H...
Page 610: Bc Control Register N (Usbbcctrln) (N = 0, 1)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.34 BC control register n (USBBCCTRLn) (n = 0, 1) Figure 13 - 43 Format of BC Control Register 0 (USBBCCTRL0) Address: F04B0H, F04B1H After reset: 0000H Symbol CHGD PDDET BATCH DCPM...
Page 611 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) IDPSINKE0 UDP0 pin V (0.6 V) input detection (comparator and sink) control DP_SRC UDP0 pin (0.6 V) input detection disabled UDP0 pin (0.6 V) input detection enabled Controls the I (sink current) used for the 0.6 V input detection circuit (comparator) and detection for the DP_SINK UDP0 pin.
Page 612 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 44 Format of BC Control Register 1 (USBBCCTRL1) Address: F04B4H, F04B5H After reset: 0000H Symbol CHGD PDDET BATCH DCPM VDMS IDPSIN VDPS IDMSI IDPSR RPDM — — — —...
Page 613 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) VDPSRCE1 UDP1 pin V (0.6 V) output control DP_SRC output disabled DP_SRC output enabled (0.6 V output) DP_SRC Controls the V output. DP_SRC IDMSINKE1 UDM1 pin V (0.6 V) input detection (comparator and sink) control DM_SRC UDM1 pin (0.6 V) input detection disabled...
Page 614: Bc Option Control Register N (Usbbcoptn) (N = 0, 1)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.35 BC option control register n (USBBCOPTn) (n = 0, 1) Figure 13 - 45 Format of BC Option Control Register 0 (USBBCOPT0) Address: F04B8H, F04B9H After reset: 0000H Symbol DPCU DMCU...
Page 615 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Bit 4 Nothing is assigned — The write value must be 0. The read value is 0. — UDP0/UDM0 pin option output voltage and comparison voltage select (Option BC: VDSEL03 to VDSEL00...
Page 616 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 46 Format of BC Option Control Register 1 (USBBCOPT1) Address: F04BCH, F04BDH After reset: 0000H Symbol DPCU DMCU CUSD VDOU VDSEL VDSEL VDSEL VDSEL — — — — —...
Page 617 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) VDSEL13 to UDP1/UDM1 pin option output voltage and comparison voltage select (Option BC: Host) VDSEL10 Select UDP1/UDM1 pin output voltage and comparison voltage value (Refer to Remark) Note Valid when CUSDETE1 = 1...
Page 618: Usb Clock Selection Register (Ucksel)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.36 USB clock selection register (UCKSEL) Figure 13 - 47 Format of USB clock selection register (UCKSEL) Address: F04C4H, F04C5H After reset: 0000H Symbol UCKS UCKSEL UCKSELC USB clock selection High-speed on-chip oscillator clock (f...
Page 619: Usb Module Control Register (Usbmc)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.37 USB module control register (USBMC) Figure 13 - 48 Format of USB Module Control Register (USBMC) Address: F04CCH, F04CDH After reset: 0002H Symbol VBRP PXXC VDDU USBMC — — — —...
Page 620: Device Address N Configuration Registers (Devaddn) (N = 0 To 5)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.3.38 Device address n configuration registers (DEVADDn) (n = 0 to 5) Figure 13 - 49 Format of Device Address n Configuration Registers (DEVADDn) (n = 0 to 5) Address: F04D0H, F04D1H (DEVADD0), F04D2H, F04D3H (DEVADD1),...
Page 621: Operation
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4 Operation 13.4.1 System control This section describes the register settings that are necessary for initialization of this module and power consumption control. 13.4.1.1 Starting operation The source for the USB power supply (UV...
Page 622 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Note 4. When the USB internal power supply is used, A/D conversion cannot be performed using the temperature sensor or internal reference voltage. Note 5. When using the USB internal power supply, connect an external 0.33 μF stabilization capacitance (for V ) to the UV pin.
Page 623 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Table 13 - 15 Controlling USB Data Bus Resistors of USB port 1 Settings USB Data Bus Resistor Control DRPD D- Line D+ Line Remarks Open Open When USB port 1 is not used...
Page 624 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 52 USB Connector Function Connection Example in Self-powered Mode (5 V) 5.0 V The board must be designed so that total 0.33 µF VBUS capacitance is 10 µF or less.
Page 625 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 54 USB Connector Function Connection Example in Bus-powered Mode (5 V) The board must be designed so that total 0.33 µF VBUS capacitance is 10 µF or less. 100 ...
Page 626: Interrupt Sources
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.2 Interrupt sources Table 13 - 16 lists the Interrupt Sources in the USB module. When an interrupt generation condition is satisfied and the interrupt output is enabled using the corresponding interrupt enable register, the USB issues a USB interrupt request to the interrupt controller and an USB interrupt will be generated.
Page 627 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Table 13 - 16 Interrupt Sources (2/2) Function That Bit to be Set Name Interrupt Source Generates Status Flag Interrupt SIGN Error interrupt for setup • When a setup transaction error (no response or ACK packet Host —...
Page 628 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 56 shows the USB interrupt relationship, Table 13 - 17 lists the USB interrupts. Figure 13 - 56 USB Interrupts Relationship USB_RESUME VBSE USB bus reset detection VBINT Set_Address detection...
Page 629 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Table 13 - 17 USB Interrupt List Interrupt Name Interrupt Flag Priority USB_INT VBUS interrupt High Resume interrupt Frame number update interrupt Device state transition interrupt Control transfer stage transition interrupt Buffer empty interrupt...
Page 630: Interrupts
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.3 Interrupts 13.4.3.1 BRDY interrupt The BRDY interrupt is generated when either of the host controller function or function controller function is selected. The following shows the conditions under which the USB module sets 1 to a corresponding bit in the BRDYSTS register.
Page 631 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) On any of the following conditions, the USB module determines that the last data for a single transfer has been received. • When a short packet including a zero-length packet is received.
Page 632 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 57 Timing of BRDY Interrupt Generation (1) Example of zero-length packet reception or data packet reception when BFRE = 0 (single-buffer mode) Token Packet Data Packet ACK Handshake USB bus...
Page 633 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.3.2 NRDY interrupt On generating an internal NRDY interrupt request for the pipe whose PID bits are set to BUF by software, the USB module sets the corresponding PIPEnNRDY bit in the NRDYSTS register to 1. If the corresponding bit in the NRDYENB register has been set to 1 by software, the USB module sets the NRDY bit in the INTSTS0 register to 1 and generates a USB interrupt.
Page 634 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) [For the pipe set to the receiving direction] • When an OUT token is received while there is no space available in the FIFO buffer. The USB module generates a NRDY interrupt request when a NAK handshake is transferred after the data following the OUT token is received, and sets the PIPEnNRDY bit to 1.
Page 635 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.3.3 BEMP interrupt On detecting a BEMP interrupt for the pipe whose PID bits are set to BUF by software, the USB module sets the corresponding PIPEnBEMP bit in the BEMPSTS register to 1. If the corresponding bit in the BEMPENB register has been set to 1 by software, the USB module sets the BEMP bit in the INTSTS0 register to 1 and generates a USB interrupt.
Page 636 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 59 shows the Timing of BEMP Interrupt Generation When Function Controller Function is Selected. Figure 13 - 59 Timing of BEMP Interrupt Generation When Function Controller Function is Selected...
Page 637 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.3.4 Device state transition interrupt Figure 13 - 60 is a diagram of Device State Transitions in the USB module. The USB module controls device state and generates device state transition interrupts. However, recovery from the suspended state (resume signal detection) is detected by means of the resume interrupt.
Page 638 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.3.5 Control transfer stage transition interrupt Figure 13 - 61 is a diagram of Control Transfer Stage Transitions in the USB module. The USB module controls the control transfer sequence and generates control transfer stage transition interrupts. The control transfer stage transition interrupts can be enabled or disabled individually using the INTENB0 register.
Page 639: Overcurrent Interrupt
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 61 Control Transfer Stage Transitions Setup token reception CTSQ2 to CTSQ0 = 110B control transfer Error Error detection and setup token reception sequence error detection Setup token reception are valid at all stages in the box.
Page 640 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) For USB port 1, an OVRCR interrupt is generated when the UOVRCUR1 pin level has changed. The level of the UOVRCUR1 pin can be checked with the OVCMON1 and OVCMON0 bits in the SYSSTS1 register. The external power-supply IC can check whether overcurrent has been detected using the OVRCR interrupt.
Page 641 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) • Modifies the UACT bit in the DVSTCTR0 register for the port in which an EOFERR interrupt has been detected to 0. • Puts the port in which an EOFERR interrupt has been generated into the idle state.
Page 642: Pipe Control
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.4 Pipe control Table 13 - 19 lists the Pipe Settings in the USB module. With USB data transfer, data transfer has to be carried out using the logic pipe called the endpoint. The USB module has five pipes that are used for data transfer.
Page 643: Transfer Types
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.4.1 Pipe control register switching procedures The following bits in the pipe control registers can be modified only when USB communication is disabled (PID = NAK). Registers that Should Not be Set in the USB Communication Enabled (PID = BUF) State: •...
Page 644 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) specification. For PIPE6, PIPE7, 64 bytes are the upper limit of the maximum packet size. The maximum packet size should be set before beginning the transfer (PID = BUF). • DCP: Set 8, 16, 32, or 64.
Page 645 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) • When an NRDY interrupt is generated.(For details, refer to 13.4.3.2 NRDY interrupt.) • If a short packet is received when the SHTNAK bit in the PIPECFG register has been set to 1 for bulk transfer.
Page 646 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.4.10 OUT-NAK mode With the pipes for bulk OUT transfer, NAK is returned in response to an OUT token and an NRDY interrupt is output when the ATREPM bit is set to 1. To make a transition from normal mode to OUT-NAK mode, OUT-NAK mode should be specified in the pipe operation disabled state (response PID = NAK) before enabling pipe operation (response PID = BUF).
Page 647: Fifo Buffer Memory
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.5 FIFO buffer memory 13.4.5.1 FIFO buffer memory The USB module has FIFO buffer memory for data transfer. The memory area used for each pipe is managed by the USB module. The FIFO buffer memory has two states depending on whether the access right is assigned to the system (CPU side) or the USB module (SIE side).
Page 648 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) (2) FIFO Buffer Clearing Tables 13 - 22 shows the clearing of the FIFO buffer memory by the USB module. The buffer memory can be cleared using the BCLR, DCLRM, and ACLRM bits.
Page 649 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.5.2 FIFO port functions Tables 13 - 23 shows the FIFO Port Function Settings for the USB module. In write access, writing data until the maximum packet size is reached automatically enables transmission of the data. To enable transmission before the maximum packet size is reached, the BVAL bit in the CFIFOCTR or DnFIFOCTR register should be set to end writing.
Page 650 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) (2) REW Bit It is possible to temporarily stop access to the pipe currently being accessed, access a different pipe, and then continue processing for the current pipe again. The REW bit in the CFIFOSEL or DnFIFOSEL register is used for this processing.
Page 651: Control Transfers (Dcp)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.6 Control transfers (DCP) In the data stage of control transfers, data is transferred using the default control pipe (DCP). The DCP buffer memory is a 64-byte single buffer and is a fixed area that is shared for both control reading and control writing.
Page 652 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.6.2 Control transfers when function controller function is selected (1) Setup Stage The USB module always sends an ACK response for a correct setup packet targeted to the USB module. The operation of the USB module in the setup stage is described below.
Page 653: Bulk Transfers (Pipe4, Pipe5)
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.7 Bulk transfers (PIPE4, PIPE5) The buffer memory usage (single/double buffer setting) can be selected for bulk transfers. The USB provides the following functions for bulk transfers. • BRDY interrupt function (BFRE bit: refer to 13.4.3.1 BRDY interrupt.) •...
Page 654: Sof Interpolation Function
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.9 SOF interpolation function When the function controller function is selected and if data could not be received at intervals of 1 ms because an SOF packet was corrupted or missing, the USB module interpolates the SOF. The SOF interpolation operation begins when the USBE and SCKE bits in the SYSCFG register have been set to 1 and an SOF packet is received.
Page 655: 13.4.10 Pipe Schedule
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.10 Pipe schedule 13.4.10.1 Conditions for generating a transaction When the host controller function is selected and the UACT bit has been set to 1, the USB module generates a transaction under the conditions shown in Table 13 - 25.
Page 656: 13.4.11 Controlling Battery Charging Detection
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.11 Controlling battery charging detection It is possible to control the processing for data contact detection (D+ line contact check), primary detection (charger detection), and secondary detection (charger verification) in compliance with Battery Charging Specification Revision 1.2.
Page 657 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 63 BC Connection Detection Interface Circuit (USB Port1) with Host/Function BC Connection Detection Function Inside of chip Outside of chip IDPSRCE1 bit DAT_REF DP_SRC DP_SRC DCPMODE1 VDPSRCE1 bit UDP1 single-ended input...
Page 658: 13.4.12 Battery Charging Connection Detection Optional Functions
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.12 Battery charging connection detection optional functions For extensibility of the battery charging specifications, the following optional functions are added to control connection detection. • USB port voltage output function (four patterns) As an optional function of the host BC connection detection function, this function can divide 5 V applied to the pin and output to the USB port.
Page 659 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 64 BC Connection Detection Optional Function Interface Circuit (USB Port 0) with Host/Function BC Connection Detection Function USB Port Output Voltage Selection Circuit Inside of chip Outside of chip...
Page 660 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 65 BC Connection Detection Optional Function Interface Circuit (USB Port 1) with Host/Function BC Connection Detection Function USB Port Output Voltage Selection Circuit Inside of chip Outside of chip...
Page 661: 13.4.13 Battery Charging Detection Processing
R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.13 Battery charging detection processing It is possible to control to the processing for Data Contact Detection (D+ line contact check), Primary Detection (Charger detection), and Secondary Detection (Charger verification), which are defined by the Battery Charging Specification.
Page 662 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 66 Process Flow for Operating as Portable Device Detect VBUS Set BATCHGE bit Set CNEN bit Data Contact Detection Data Contact Set RPDME bit (software waiting method) Detection Set IDPSRCE bit (hardware Wait for min.
Page 663 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) 13.4.13.2 Processing when host controller is selected The following processing is required when operating the USB module as a Charging Downstream Port for Battery Charging. (1) Start driving the VBUS. (2) Enable the Portable Device detection circuit.
Page 664 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 67 Process Flow for Operating as Charging Downstream Port (Steps (1) to (4)) Portable Device Detection Drive VBUS Processing PD detection circuit enabled (IDPSINKE = 1) PD detection interrupt enabled...
Page 665 R9A02G015 CHAPTER 13 USB 2.0 HOST/FUNCTION MODULE (USB) Figure 13 - 68 Process Flow for Operating as Charging Downstream Port (Steps (A) to (B)) D-Line Drive Control Drive VBUS Set VDMSRCE bit Connection detected? Clear VDMSRCE bit (within 10 ms)
Page 666: Interrupt Functions
R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS CHAPTER 14 INTERRUPT FUNCTIONS The interrupt function switches the program execution to other processing. When the branch processing is finished, the program returns to the interrupted processing. The number of interrupt sources differs, depending on the product.
Page 667 R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS Table 14 - 1 Interrupt Source List (1/2) Interrupt Source Name Trigger INTWDTI Internal 0004H Note 3   Watchdog timer interval (75% of overflow time + 1/2 f INTLVI 0006H Note 4  ...
Page 668 R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS Table 14 - 1 Interrupt Source List (2/2) Interrupt Source Name Trigger INTP7 Pin input edge detection External 004CH   INTP8 004EH   INTP9 0050H   INTP10 0052H   INTP11 0054H ...
Page 669 R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14 - 1 Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus ISP1 ISP0 Vector table Priority controller Interrupt request address generator Standby release signal (B) External maskable interrupt (INTPn) Internal bus...
Page 670 R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14 - 2 Basic Configuration of Interrupt Function (2/2) (C) Software interrupt Internal bus Vector table Interrupt request address generator R19UH0112EJ0100 Rev.1.00 Page 670 of 825 Mar 29, 2019...
Page 671: Registers Controlling Interrupt Functions
R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS 14.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. • Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) • Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) •...
Page 672 R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS Table 14 - 2 Flags Corresponding to Interrupt Request Sources (1/2) Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag with without Register Register Register INTWDTI WDTIIF IF0L WDTIMK MK0L WDTIPR0, WDTIPR1 PR00L, ...
Page 673 R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS Note 2. If one of the interrupt sources INTSR0, INTCSI01, and INTIIC01 is generated, bit 2 of the IF0H register is set to 1. Bit 2 of the MK0H, PR00H, and PR10H registers supports these three interrupt sources.
Page 674: Interrupt Request Flag Registers (If0L, If0H, If1L, If1H, If2L, If2H)
R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS 14.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
Page 675 R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14 - 3 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) Address: FFFE0H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> IF0L PIF5 PIF4 PIF3 PIF2...
Page 676: Interrupt Mask Flag Registers (Mk0L, Mk0H, Mk1L, Mk1H, Mk2L, Mk2H)
R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS 14.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt. The MK0L, MK0H, MK1L, MK1H, MK2L and MK2H registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 677: Priority Specification Flag Registers (Pr00L, Pr00H, Pr01L, Pr01H, Pr02L, Pr10L, Pr10H, Pr11L, Pr11H, Pr12L, Pr12H)
R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS 14.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) The priority specification flag registers are used to set the corresponding maskable interrupt priority level. A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L or 2H).
Page 678 R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14 - 6 Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (2/2) Address: FFFEBH After reset: FFH Symbol <6> <5> <4> <2> <0> PR01H IICAPR02...
Page 679: External Interrupt Rising Edge Enable Register (Egp0, Egp1), External Interrupt Falling Edge Enable Register (Egn0, Egn1)
R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS 14.3.4 External interrupt rising edge enable register (EGP0, EGP1), external interrupt falling edge enable register (EGN0, EGN1) These registers specify the valid edge for INTP0 to INT15. The EGP0, EGP1, EGN0, EGN1 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 680 R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS Table 14 - 3 shows the Ports Corresponding to EGPn and EGNn Bits. Table 14 - 3 Ports Corresponding to EGPn and EGNn Bits with USB without USB Detection Enable Bit Interrupt Request Signal 32-pin...
Page 681: Program Status Word (Psw)
R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS 14.3.5 Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple interrupt servicing are mapped to the PSW.
Page 682: Interrupt Servicing Operations
R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS 14.4 Interrupt Servicing Operations 14.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 683 R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14 - 9 Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending No (Low priority) (xxPR1, xxPR0)  (ISP1, ISP0) Interrupt request held pending...
Page 684 R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14 - 10 Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction Instruction jump to interrupt servicing program xxIF 9 clocks Remark 1 clock: 1/f...
Page 685: Software Interrupt Request Acknowledgment
R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS 14.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH, 0007FH) are loaded into the PC and branched.
Page 686 R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS Table 14 - 5 Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request Maskable Interrupt Request Priority Level 0 Priority Level 1 Priority Level 2 Priority Level 3 Software...
Page 687 R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14 - 12 Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice INTxx servicing INTyy servicing INTzz servicing Main processing IE = 0 IE = 0 IE = 0 INTxx...
Page 688 R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14 - 13 Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 00)
Page 689: Interrupt Servicing During Division Instruction
14.4.4 Interrupt servicing during division instruction The R9A02G015 handles interrupts during the DIVHU/DIVWU instruction in order to enhance the interrupt response when a division instruction is executed. • When an interrupt is generated while the DIVHU/DIVWU instruction is executed, the instruction is suspended •...
Page 690 NOP instruction immediately after any DIVHU or DIVWU instruction output during the build process. - V. 1.71 and later versions of the CA78K0R (Renesas Electronics compiler), for both C and assembly language source code - Service pack 1.40.3 and later versions of the EWRL78 (IAR compiler), for C language source...
Page 691: Interrupt Request Hold
R9A02G015 CHAPTER 14 INTERRUPT FUNCTIONS 14.4.5 Interrupt request hold There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 692: Standby Function
R9A02G015 CHAPTER 15 STANDBY FUNCTION CHAPTER 15 STANDBY FUNCTION 15.1 Standby Function The standby function reduces the operating current of the system, and the following three modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high-speed system clock oscillator, or high-speed on-chip oscillator is operating before the HALT mode is set, oscillation of each clock continues.
Page 693: Registers Controlling Standby Function
R9A02G015 CHAPTER 15 STANDBY FUNCTION Caution 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation operating with main system clock before executing STOP instruction (except SNOOZE mode setting unit). Caution 2. When using CSI00, UART0, or the A/D converter in the SNOOZE mode, set up serial standby control register m (SSCm) and A/D converter mode register 2 (ADM2) before switching to the STOP mode.
Page 694: Standby Function Operation
R9A02G015 CHAPTER 15 STANDBY FUNCTION 15.3 Standby Function Operation 15.3.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, or high-speed on-chip oscillator clock.
Page 695 R9A02G015 CHAPTER 15 STANDBY FUNCTION Table 15 - 1 Operating Statuses in HALT Mode HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on...
Page 696 R9A02G015 CHAPTER 15 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed.
Page 697 R9A02G015 CHAPTER 15 STANDBY FUNCTION Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.
Page 698: Stop Mode
R9A02G015 CHAPTER 15 STANDBY FUNCTION 15.3.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the high-speed on-chip oscillator clock, X1 clock, or external main system clock.
Page 699 R9A02G015 CHAPTER 15 STANDBY FUNCTION Table 15 - 2 Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on...
Page 700 R9A02G015 CHAPTER 15 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following two sources. Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
Page 701 R9A02G015 CHAPTER 15 STANDBY FUNCTION Figure 15 - 4 STOP Mode Release by Interrupt Request Generation (2/2) (2) When high-speed system clock (X1 oscillation) is used as CPU clock Interrupt STOP request instruction Note 1 Standby release signal Note 2...
Page 702 R9A02G015 CHAPTER 15 STANDBY FUNCTION Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.
Page 703: Snooze Mode
R9A02G015 CHAPTER 15 STANDBY FUNCTION 15.3.3 SNOOZE mode (1) SNOOZE mode setting and operating statuses The SNOOZE mode can be set by the CSI00, UART0, and A/D converter. Note that this mode can only be specified if the CPU clock is the high-speed on-chip oscillator clock.
Page 704 R9A02G015 CHAPTER 15 STANDBY FUNCTION Table 15 - 3 Operating Statuses in SNOOZE Mode SNOOZE Mode Setting When Inputting CSI00 Data Reception Signal or A/D Converter Timer Trigger Signal While in STOP Mode Item When CPU Is Operating on High-speed on-chip oscillator clock (f...
Page 705 R9A02G015 CHAPTER 15 STANDBY FUNCTION (2) Timing diagram when the interrupt request signal is generated in the SNOOZE mode Figure 15 - 6 When the Interrupt Request Signal is Generated in the SNOOZE Mode STOP Trigger instruction detection Interrupt request...
Page 706: Reset Function
10 μs or more within the operating voltage range shown in 2.4 AC Characteristics of the R9A02G015 Data Sheet (R19DS0101E), and then input a high level to the pin.
Page 707 R9A02G015 CHAPTER 16 RESET FUNCTION Figure 16 - 1 Block Diagram of Reset Function Internal bus Power-on-reset status Reset control flag register (RESF) register (PORSR) PORF TRAP WDTRF RPERF IAWRF LVIRF Watchdog timer reset signal Clear Clear Clear Clear Clear...
Page 708: Timing Of Reset Operation
Timing of Reset Operation The R9A02G015 is reset by input of the low level on the RESETB pin and released from the reset state by input of the high level on the RESETB pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the operating clock starts.
Page 709 R9A02G015 CHAPTER 16 RESET FUNCTION Note 1. Reset times (times for release from the external reset state) After the first release of the POR: 0.672 ms (TYP.), 0.832 ms (MAX.) when the LVD is in use. 0.399 ms (TYP.), 0.519 ms (MAX.) when the LVD is off.
Page 710 R9A02G015 CHAPTER 16 RESET FUNCTION Table 16 - 1 Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Operation stopped HOCO Operation stopped (the X1 and X2 pins are input port mode)
Page 711 R9A02G015 CHAPTER 16 RESET FUNCTION Table 16 - 2 Hardware Statuses After Reset Acknowledgment Hardware Note After Reset Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW)
Page 712: Register For Confirming Reset Source
16.2.1 Reset control flag register (RESF) Many internal reset generation sources exist in the R9A02G015. The reset control flag register (RESF) is used to store which source has generated the reset request. The RESF register can be read by an 8-bit memory manipulation instruction.
Page 713 R9A02G015 CHAPTER 16 RESET FUNCTION The status of the RESF register when a reset request is generated is shown in Table 16 - 3. Table 16 - 3 RESF Register Status When Reset Request Is Generated Reset by Reset Source...
Page 714 R9A02G015 CHAPTER 16 RESET FUNCTION Figure 16 - 5 Example of Procedure for Checking Reset Source After reset acceptance Read the RESF register (clear the RESF register) and Read RESF register store the value of the RESF register in any RAM.
Page 715: Peripheral Reset Control Register 0 (Prr0)
This register is used for individual reset control of each peripheral hardware. The R9A02G015 controls reset and reset release of each peripheral hardware supported by the PRR0 register. Figure 16 - 6 Format of Peripheral reset control register 0 (PRR0)
Page 716: Peripheral Reset Control Register 2 (Prr2)
This register is used for individual reset control of each peripheral hardware. The R9A02G015 controls reset and reset release of each peripheral hardware supported by the PRR2 register. Figure 16 - 7 Format of Peripheral reset control register 2 (PRR2)
Page 717: Power-On-Reset Circuit
(RESF) and the power-on-reset status register (PORSR) are cleared (00H). Remark 1. The R9A02G015 incorporates multiple hardware functions that generate an internal reset signal. A flag that indicates the reset source is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT), voltage-detector (LVD), illegal instruction execution, RAM parity error, or illegal-memory access.
Page 718: Configuration Of Power-On-Reset Circuit
R9A02G015 CHAPTER 17 POWER-ON-RESET CIRCUIT 17.2 Configuration of Power-on-reset Circuit The block diagram of the power-on-reset circuit is shown in Figure 17 - 1. Figure 17 - 1 Block Diagram of Power-on-reset Circuit Internal reset signal Reference voltage source 17.3 Operation of Power-on-reset Circuit The timing of generation of the internal reset signal by the power-on-reset circuit and voltage detector is shown next.
Page 719 Note 4. After power is supplied, the reset state must be retained until the operating voltage becomes in the range defined in 2.4 AC Characteristics of the R9A02G015 Data Sheet (R19DS0101E). This is done by controlling the externally input reset signal.
Page 720 R9A02G015 CHAPTER 17 POWER-ON-RESET CIRCUIT Figure 17 - 3 Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (2/3) (2) LVD is interrupt & reset mode (option byte 000C1: LVIMDS1, LVIMDS0 = 1, 0) Supply voltage (V...
Page 721 R9A02G015 CHAPTER 17 POWER-ON-RESET CIRCUIT Figure 17 - 4 Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (3/3) (3) LVD reset mode (option byte 000C1H: LVIMDS1, LVIMDS0 = 1, 1) Supply voltage (V Operating voltage range lower limit = 1.51 V (TYP.)
Page 722: Voltage Detector
• After power is supplied, the reset state must be retained until the operating voltage becomes in the range defined in 2.4 AC Characteristics of the R9A02G015 Data Sheet (R19DS0101E). This is done by utilizing the voltage detection circuit or controlling the externally input reset signal. After the power supply is turned off, this LSI should be placed in the STOP mode, or placed in the reset state by utilizing the voltage detection circuit or controlling the externally input reset signal before the voltage falls below the operating range.
Page 723 R9A02G015 CHAPTER 18 VOLTAGE DETECTOR The reset and internal interrupt signals are generated in each mode as follows. Interrupt & reset mode Reset mode Interrupt mode (LVIMDS1, LVIMDS0 = 1, 0) (LVIMDS1, LVIMDS0 = 1, 1) (LVIMDS1, LVIMDS0 = 0, 1)
Page 724: Configuration Of Voltage Detector
R9A02G015 CHAPTER 18 VOLTAGE DETECTOR 18.2 Configuration of Voltage Detector The block diagram of the voltage detector is shown in Figure 18 - 1. Figure 18 - 1 Block Diagram of Voltage Detector N-ch Internal reset signal LVDH LVDL INTLVI...
Page 725: Voltage Detection Register (Lvim)
R9A02G015 CHAPTER 18 VOLTAGE DETECTOR 18.3.1 Voltage detection register (LVIM) This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as well as to check the LVD output mask status. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 726: Voltage Detection Level Register (Lvis)
R9A02G015 CHAPTER 18 VOLTAGE DETECTOR 18.3.2 Voltage detection level register (LVIS) This register selects the voltage detection level. The minimum supply voltage (LVD detection voltage) and LVD detection level settings that are set by the user option byte can be changed by software.
Page 727 & reset mode. Note 3. Indicates an approximate detection value. For details on the actual detection voltage, refer to 2.6.4 LVD circuit characteristics in the R9A02G015 Data Sheet (R19DS0101E). Note 4. Cannot be selected when LVIMDS1 and LVIMDS0 = 1 and 0.
Page 728 010C1H. Remark 1. For details on the LVD circuit, see CHAPTER 18 VOLTAGE DETECTOR . Remark 2. The detection voltage is a TYP. value. For details, see 2.6.4 LVD circuit characteristics in the R9A02G015 Data Sheet (R19DS0101E). ( Cautions are listed on the next page.) R19UH0112EJ0100 Rev.1.00...
Page 729 Remark 1. ×: Don’t care Remark 2. For details on the LVD circuit, see CHAPTER 18 VOLTAGE DETECTOR . Remark 3. The detection voltage is a TYP. value. For details, see 2.6.4 LVD circuit characteristics in the R9A02G015 Data Sheet (R19DS0101E).
Page 730: Operation Of Voltage Detector
R9A02G015 CHAPTER 18 VOLTAGE DETECTOR 18.4 Operation of Voltage Detector 18.4.1 When used as reset mode Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the initial detection voltage (V by using the option byte 000C1H. The detection voltages can be reset using the LVIS register.
Page 731 R9A02G015 CHAPTER 18 VOLTAGE DETECTOR Figure 18 - 5 Timing of Voltage Detector Internal Reset Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 1) Supply voltage (V Lower limit of operation voltage = 1.51 V (TYP.) = 1.50 V (TYP.)
Page 732: When Used As Interrupt Mode
STOP mode, or placed in the reset state by controlling the externally input reset signal, before the voltage falls below the operating voltage range defined in 2.4 AC Characteristics of the R9A02G015 Data Sheet (R19DS0101E). When restarting the operation, make sure that the operation voltage has returned within the range of operation.
Page 733 2.4 AC Characteristics of the R9A02G015 Data Sheet (R19DS0101E). When restarting the operation, make sure that the operation voltage has returned within the range of operation.
Page 734: When Used As Interrupt And Reset Mode
R9A02G015 CHAPTER 18 VOLTAGE DETECTOR 18.4.3 When used as interrupt and reset mode Specify the operation mode (the interrupt & reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage (V LVDH ) by using the option byte 000C1H. Do not manipulate the detection voltage using the LVIS register.
Page 735 R9A02G015 CHAPTER 18 VOLTAGE DETECTOR Figure 18 - 7 Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2) If a reset is not generated after releasing the mask,  V determine that a condition of V...
Page 736 R9A02G015 CHAPTER 18 VOLTAGE DETECTOR Note 1. The LVIMK flag is set to “1” by reset signal generation. Note 2. After an interrupt is generated, perform the processing according to Figure 18 - 9 Setting Procedure for Operating Voltage Check and Reset in interrupt and reset mode.
Page 737 R9A02G015 CHAPTER 18 VOLTAGE DETECTOR Figure 18 - 8 Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2) When a condition of V is V < V after releasing the mask, LVDH a reset is generated because of LVIMD = 1 (reset mode).
Page 738 R9A02G015 CHAPTER 18 VOLTAGE DETECTOR Note 1. The LVIMK flag is set to “1” by reset signal generation. Note 2. After an interrupt is generated, perform the processing according to Figure 18 - 9 Setting Procedure for Operating Voltage Check and Reset in interrupt and reset mode.
Page 739: Changing Of Lvd Detection Voltage Setting
R9A02G015 CHAPTER 18 VOLTAGE DETECTOR 18.5 Changing of LVD Detection Voltage Setting To change the LVD detection voltage by software, use the following procedure. The LVD detection voltage can be changed in interrupt mode and reset mode. In interrupt & reset mode, the value of the LVD detection voltage cannot be changed. Keep the initial value (set value in the option byte) unchanged.
Page 740: Changing Of Lvd Detection Voltage Setting In Lvd Reset Mode
R9A02G015 CHAPTER 18 VOLTAGE DETECTOR 18.5.1 Changing of LVD detection voltage setting in LVD reset mode Figure 18 - 11 shows an Example of Timing for Changing LVD Detection Voltage Setting in LVD Reset Mode. Figure 18 - 11 Example of Timing for Changing LVD Detection Voltage Setting in LVD Reset Mode...
Page 741: Changing Of Lvd Detection Voltage Setting In Lvd Interrupt Mode
R9A02G015 CHAPTER 18 VOLTAGE DETECTOR 18.5.2 Changing of LVD detection voltage setting in LVD interrupt mode Figure 18 - 12 shows an Example of Timing for Changing LVD Detection Voltage Setting in LVD Interrupt Mode. Figure 18 - 12 Example of Timing for Changing LVD Detection Voltage Setting in LVD Interrupt Mode...
Page 742 R9A02G015 CHAPTER 18 VOLTAGE DETECTOR Figure 18 - 13 Example of Timing for Changing LVD Detection Voltage Using LVDIS When V < V Option byte initial value Detection voltage LVIF flag LVISEN (set by software) LVIOMSK flag Internal reset signal...
Page 743: Cautions For Voltage Detector
In this case, the time from release of reset to the start of the operation of the R9A02G015 can be arbitrarily set by taking the following action.
Page 744 RESETB pin, turn power on, continue to input a low level to the pin for 10 μs or more within the operating voltage range shown in 2.4 AC Characteristics of the R9A02G015 Data Sheet (R19DS0101E), and then input a high level to the pin.
Page 745: Safety Functions
(1) Flash memory CRC operation function (high-speed CRC, general-purpose CRC) This detects data errors in the flash memory by performing CRC operations. Two CRC functions are provided in R9A02G015 that can be used according to the application or purpose of use.
Page 746: Registers Used By Safety Functions
The IEC60730 standard mandates the checking of data in the flash memory, and recommends using CRC to do it. The high-speed CRC provided in R9A02G015 can be used to check the entire code flash memory area during the initialization routine. The high-speed CRC can be executed only when the program is allocated on the RAM and in the HALT mode of the main system clock.
Page 747 R9A02G015 CHAPTER 19 SAFETY FUNCTIONS 19.3.1.1 Flash memory CRC control register (CRC0CTL) This register is used to control the operation of the high-speed CRC ALU, as well as to specify the operation range. The CRC0CTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 748 R9A02G015 CHAPTER 19 SAFETY FUNCTIONS 19.3.1.2 Flash memory CRC operation result register (PGCRCL) This register is used to store the high-speed CRC operation results. The PGCRCL register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H.
Page 749 R9A02G015 CHAPTER 19 SAFETY FUNCTIONS <Operation flow> Figure 19 - 3 Flowchart of Flash Memory CRC Operation Function (High-speed CRC) Start ; Store the expected CRC operation result ; value in the lowest 4 bytes. Set FEA5 to FEA0 bits ;...
Page 750: Crc Operation Function (General-Purpose Crc)
CPU is operating. In R9A02G015, a general CRC operation can be executed as a peripheral function while the CPU is operating. The general CRC can be used for checking various data in addition to the code flash memory area. The data to be checked can be specified by using software (a user-created program).
Page 751 R9A02G015 CHAPTER 19 SAFETY FUNCTIONS 19.3.2.1 CRC input register (CRCIN) CRCIN register is an 8-bit register that is used to set the CRC operation data of general-purpose CRC. The possible setting range is 00H to FFH. The CRCIN register can be set by an 8-bit memory manipulation instruction.
Page 752 R9A02G015 CHAPTER 19 SAFETY FUNCTIONS 19.3.2.2 CRC data register (CRCD) This register is used to store the general-purpose CRC operation result. The possible setting range is 0000H to FFFFH. After 1 clock of CPU/peripheral hardware clock (f ) has elapsed from the time CRCIN register is written, the CRC operation result is stored to the CRCD register.
Page 753: Ram Parity Error Detection Function
The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit data in R9A02G015’s RAM. By using this RAM parity error detection function, the parity bit is appended when data is written, and the parity is checked when the data is read. This function can also be used to trigger a reset when a parity error occurs.
Page 754 R9A02G015 CHAPTER 19 SAFETY FUNCTIONS Figure 19 - 8 RAM Parity Error Check Flow Check start Note RPERF = 1 RPERDIS = 1 Disable parity error resets RAM check Read RAM RAM check Parity error has RPEF = 1 occurred Confirm that a parity error has occurred.
Page 755: Ram Guard Function
R9A02G015 CHAPTER 19 SAFETY FUNCTIONS 19.3.4 RAM guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important data stored in the RAM be protected, even if the CPU freezes. This RAM guard function is used to protect data in the specified memory space.
Page 756: Sfr Guard Function
R9A02G015 CHAPTER 19 SAFETY FUNCTIONS 19.3.5 SFR guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important SFRs be protected from being overwritten, even if the CPU freezes. This SFR guard function is used to protect data in the control registers used by the port function, interrupt function, clock control function, voltage detection function, and RAM parity error detection function.
Page 757: Invalid Memory Access Detection Function
R9A02G015 CHAPTER 19 SAFETY FUNCTIONS 19.3.6 Invalid memory access detection function The IEC60730 standard mandates checking that the CPU and interrupts are operating correctly. The illegal memory access detection function triggers a reset if a memory space specified as access-prohibited is accessed.
Page 758 R9A02G015 CHAPTER 19 SAFETY FUNCTIONS 19.3.6.1 Invalid memory access detection control register (IAWCTL) This register is used to control the detection of invalid memory access and RAM/SFR guard function. IAWEN bit is used in invalid memory access detection function. The IAWCTL register can be set by an 8-bit memory manipulation instruction.
Page 759: Frequency Detection Function
R9A02G015 CHAPTER 19 SAFETY FUNCTIONS 19.3.7 Frequency detection function The IEC60730 standard mandates checking that the oscillation frequency is correct. By using the CPU/peripheral hardware clock frequency (f and measuring the pulse width of the input signal CLK) to channel 1 of the timer array unit 0 (TAU0), whether the proportional relationship between the two clock frequencies is correct can be determined.
Page 760 R9A02G015 CHAPTER 19 SAFETY FUNCTIONS 19.3.7.1 Timer input select register 0 (TIS0) The TIS0 register is used to select the timer input of channels 0 and 1 of the timer array unit 0 (TAU0). The TIS0 register can be set by an 8-bit memory manipulation instruction.
Page 761: A/D Test Function
R9A02G015 CHAPTER 19 SAFETY FUNCTIONS 19.3.8 A/D test function The IEC60730 standard mandates testing the A/D converter. The A/D test function is used to check whether the A/D converter is operating normally by executing A/D conversions of the positive reference voltage and negative reference voltage of the A/D converter, analog input channel (ANI), temperature sensor output voltage, and internal reference voltage.
Page 762 R9A02G015 CHAPTER 19 SAFETY FUNCTIONS Figure 19 - 15 Configuration of A/D Test Function • ADISS • ADS4 to 0 P20/ANI0/AV REFP P21/ANI1/AV REFM ANIxx • ADTES1 to 0 ANIxx Temperature sensor Internal reference voltage (1.45 V) A/D convertor + side reference voltage •...
Page 763: Digital Output Signal Level Detection Function For I/O Pins
R9A02G015 CHAPTER 19 SAFETY FUNCTIONS 19.3.9 Digital output signal level detection function for I/O pins In the IEC60730, it is required to check that the I/O function correctly operates. By using the digital output signal level detection function for I/O pins, the digital output level of the pin can be read when the port is set to output mode.
Page 764: Regulator
20.1 Regulator Overview R9A02G015 contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize the regulator output voltage, connect the REGC pin to V via a capacitor (0.47 to 1 μF). Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
Page 765: Option Byte
21.1 Functions of Option Bytes Addresses 000C0H to 000C3H of the flash memory of the R9A02G015 form an option byte area. Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H). Upon power application or resetting and starting, an option byte is automatically referenced and a specified function is set.
Page 766: On-Chip Debug Option Byte (000C3H/010C3H)
R9A02G015 CHAPTER 21 OPTION BYTE (3) 000C2H/010C2H Setting of flash operation mode Make the setting depending on the main system clock frequency (f ) and power supply voltage (V MAIN to be used. • HS (high-speed main) mode Setting of the frequency of the high-speed on-chip oscillator •...
Page 767: Format Of User Option Byte
R9A02G015 CHAPTER 21 OPTION BYTE 21.2 Format of User Option Byte The format of user option byte is shown below. Figure 21 - 1 Format of User Option Byte (000C0H/010C0H) Note 1 Address: 000C0H/010C0H WDTINT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1...
Page 768 R9A02G015 CHAPTER 21 OPTION BYTE Note 3. When the window open period is set to 75%, clearing the counter of the watchdog timer (writing ACH to WDTE) must proceed outside the corresponding period from among those listed below, over which clearing of the counter is prohibited (for example, confirming that the interval timer interrupt request flag (WDTIIF) of the watchdog timer is set).
Page 769 Remark 1. For details on the LVD circuit, see CHAPTER 18 VOLTAGE DETECTOR . Remark 2. The detection voltage is a typical value. For details, see 2.6.4 LVD circuit characteristics in the R9A02G015 Data Sheet (R19DS0101E). R19UH0112EJ0100 Rev.1.00 Page 769 of 825...
Page 770 Remark 1. For details on the LVD circuit, see CHAPTER 18 VOLTAGE DETECTOR . Remark 2. The detection voltage is a typical value. For details, see 2.6.4 LVD circuit characteristics in the R9A02G015 Data Sheet (R19DS0101E). R19UH0112EJ0100 Rev.1.00 Page 770 of 825...
Page 771 Remark 1. For details on the LVD circuit, see CHAPTER 18 VOLTAGE DETECTOR . Remark 2. The detection voltage is a typical value. For details, see 2.6.4 LVD circuit characteristics in the R9A02G015 Data Sheet (R19DS0101E). R19UH0112EJ0100 Rev.1.00 Page 771 of 825...
Page 772 Caution 2. After power is supplied, the reset state must be retained until the operating voltage becomes in the range defined in 2.4 AC Characteristics of the R9A02G015 Data Sheet (R19DS0101E). This is done by utilizing the voltage detection circuit or controlling the externally input reset signal. After the power...
Page 773 R9A02G015 CHAPTER 21 OPTION BYTE Figure 21 - 6 Format of Option Byte (000C2H/010C2H) Note 1 Address: 000C2H/010C2H CMODE1 CMODE0 FRQSEL4 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 Setting of flash operation mode CMODE1 CMODE0 Operating Frequency Operating Voltage Range Range (f MAIN...
Page 774: Format Of On-Chip Debug Option Byte
R9A02G015 CHAPTER 21 OPTION BYTE 21.3 Format of On-chip Debug Option Byte The format of on-chip debug option byte is shown below. Figure 21 - 7 Format of On-chip Debug Option Byte (000C3H/010C3H) Note Address: 000C3H/010C3H OCDENSET OCDERSD OCDENSET OCDERSD Control of on-chip debug operation Disables on-chip debug operation.
Page 775: Setting Of Option Byte
R9A02G015 CHAPTER 21 OPTION BYTE 21.4 Setting of Option Byte The user option byte and on-chip debug option byte can be set using the assembler linker option, in addition to describing in the source. When doing so, the contents set by using the link option take precedence, even if descriptions exist in the source, as mentioned below.
Page 776: Flash Memory
CHAPTER 22 FLASH MEMORY R9A02G015 incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory includes the “code flash memory”, in which programs can be executed, and the “data flash memory”, an area for storing data.
Page 777: Serial Programming Using Flash Memory Programmer
Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming The contents of the flash memory can be rewritten after R9A02G015 has been mounted on the target system. The connectors that connect the dedicated flash memory programmer must be mounted on the target system.
Page 778 R9A02G015 CHAPTER 22 FLASH MEMORY Table 22 - 1 Wiring Between R9A02G015 and Dedicated Flash Memory Programmer Pin No. Pin Configuration of Dedicated Flash Memory Programmer 32-pin Signal Name HVQFN (4 x 4) Pin Name E1, E2, E2 Lite, E20 on-...
Page 779: Programming Environment
R9A02G015 CHAPTER 22 FLASH MEMORY 22.1.1 Programming Environment The environment required for writing a program to the flash memory of R9A02G015 is illustrated below. Figure 22 - 1 Environment for Writing Program to Flash Memory E1, E2, PG-FP6 E2 Lite, E20...
Page 780: Serial Programming Using External Device (That Incorporates Uart)
22.2 Serial Programming Using External Device (that Incorporates UART) On-board data writing to the internal flash memory is possible by using R9A02G015 and an external device (a microcontroller or ASIC) connected to a UART. On the development of flash memory programmer by user, refer to the RL78 Microcontrollers (RL78 Protocol A) Programmer Edition Application Note (R01AN0815).
Page 781: Communication Mode
CHAPTER 22 FLASH MEMORY 22.2.2 Communication Mode Communication between the external device R9A02G015 is established by serial communication using the TOOLTxD and TOOLRxD pins via the dedicated UART of R9A02G015. Transfer rate: 1 M, 500 k, 250 k, 115.2 kbps...
Page 782: Connection Of Pins On Board
For details, refer to R9A02G015 Data Sheet (R19DS0101E). Remark 2. The SAU and IICA pins are not used for communication between R9A02G015 and dedicated flash memory programmer, because single-line UART (TOOL0 pin) is used.
Page 783: Port Pins
R9A02G015 CHAPTER 22 FLASH MEMORY 22.3.3 Port pins Example When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to...
Page 784: Programming Method
R9A02G015 CHAPTER 22 FLASH MEMORY 22.4 Programming Method 22.4.1 Serial programming procedure The following figure illustrates a flow for rewriting the code flash memory through serial programming. Figure 22 - 6 Code Flash Memory Manipulation Procedure Start Flash memory programming...
Page 785: Flash Memory Programming Mode
To enter the mode, set as follows. <When serial programming by using the dedicated flash memory programmer> Connect R9A02G015 to a dedicated flash memory programmer. Communication from the dedicated flash memory programmer is performed to automatically switch to the flash memory programming mode.
Page 786 R9A02G015 CHAPTER 22 FLASH MEMORY The supply voltage value applied to R9A02G015 during write operations and the setting information of the user option byte for setting of the flash memory programming mode determine which mode is selected. When a dedicated flash memory programmer is used for serial programming, setting the voltage on GUI selects the mode automatically.
Page 787: Selecting Communication Mode
R9A02G015 CHAPTER 22 FLASH MEMORY 22.4.3 Selecting communication mode Communication mode of R9A02G015 as follows. Table 22 - 6 Communication Modes Note 1 Standard Setting Communication Mode Pins Used Note 2 Port Speed Frequency Multiply Rate 1-line mode 115200 bps,...
Page 788: Communication Commands
R9A02G015 executes serial programming through the commands listed in Table 22 - 7. The signals sent from the dedicated flash memory programmer or external device to R9A02G015 are called commands, and programming functions corresponding to the commands are executed. For details, refer to the RL78 microcontroller (RL78 Protocol A) Programmer Edition Application Note (R01AN0815).
Page 789 R9A02G015 CHAPTER 22 FLASH MEMORY Product information (such as product name and firmware version) can be obtained by executing the “Silicon Signature” command. Tables 22 - 8 and 22 - 9 show signature data list and example of signature data list.
Page 790: Processing Time For Each Command When Pg-Fp6 Is In Use (Reference Value)
R9A02G015 CHAPTER 22 FLASH MEMORY 22.5 Processing Time for Each Command When PG-FP6 Is in Use (Reference Value) The following shows the processing time for each command (reference value) when PG-FP6 is used as a dedicated flash memory programmer. Table 22 - 10 Processing Time for Each Command When PG-FP6 Is in Use (Reference Value)
Page 791: Self-Programming
22.6 Self-Programming R9A02G015 supports a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the RL78 microcontroller self- programming library, it can be used to upgrade the program in the field.
Page 792: Self-Programming Procedure
R9A02G015 CHAPTER 22 FLASH MEMORY 22.6.1 Self-programming procedure The following figure illustrates a flow for rewriting the code flash memory by using a flash self-programming library. Figure 22 - 8 Flow of Self-Programming (Rewriting Flash Memory) Code flash memory control start...
Page 793: Boot Swap Function
1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmware of R9A02G015, so that boot cluster 1 is used as a boot area.
Page 794 R9A02G015 CHAPTER 22 FLASH MEMORY Figure 22 - 10 Example of Executing Boot Swapping Block number Erasing block 4 Erasing block 5 Erasing block 6 Erasing block 7 User program User program User program User program User program User program...
Page 795: Flash Shield Window Function
Figure 22 - 11 Flash Shield Window Setting Example (Target Devices: R9A02G015, Start Block: 04H, End Block: 06H) Methods by which writing can be performed...
Page 796: Security Settings
Security can be set by serial programming and self-programming. Each security setting can be used in combination. Table 22 - 12 shows the relationship between the erase and write commands when R9A02G015 security function is enabled. After the security settings are specified, releasing the security settings by the Security Release command is enabled by a reset.
Page 797 R9A02G015 CHAPTER 22 FLASH MEMORY Table 22 - 12 Relationship Between Enabling Security Function and Command (1) During serial programming Executed Command Valid Security Block Erase Write Prohibition of block erase Blocks cannot be erased. Note Can be performed. Prohibition of writing Blocks can be erased.
Page 798: Data Flash
R9A02G015 CHAPTER 22 FLASH MEMORY 22.8 Data Flash 22.8.1 Data flash overview An overview of the data flash memory is provided below. • The user program can rewrite the data flash memory by using the flash data library. For details, refer to RL78 Family Flash Data Library User’s Manual.
Page 799: Register Controlling Data Flash Memory
R9A02G015 CHAPTER 22 FLASH MEMORY 22.8.2 Register controlling data flash memory 22.8.2.1 Data flash control register (DFLCTL) This register is used to enable or disable accessing to the data flash. The DFLCTL register is set by a 1-bit or 8-bit memory manipulation instruction.
Page 800: Procedure For Accessing Data Flash Memory
R9A02G015 CHAPTER 22 FLASH MEMORY 22.8.3 Procedure for accessing data flash memory The data flash memory is initially stopped after a reset ends and cannot be accessed (read or programmed). To access the memory, perform the following procedure: <1> Write 1 to bit 0 (DFLEN) of the data flash control register (DFLCTL).
Page 801: On-Chip Debug Function
Serial communication is performed by using a single-line UART that uses the TOOL0 pin. Caution R9A02G015 has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Page 802: On-Chip Debug Security Id
On-Chip Debug Security ID R9A02G015 has an on-chip debug operation control bit in the flash memory at 000C3H (see CHAPTER 21 OPTION BYTE) and an on-chip debug security ID setting area at 000C4H to 000CDH, to prevent third parties from reading memory content.
Page 803 R9A02G015 CHAPTER 23 ON-CHIP DEBUG FUNCTION Figure 23 - 2 Memory Spaces Where Debug Monitor Programs Are Allocated Code flash memory Internal RAM Use prohibited SFR area 1FFFFH (512 bytes or Note 1 256 bytes Internal RAM Stack area for debugging...
Page 804: Bcd Correction Circuit
R9A02G015 CHAPTER 24 BCD CORRECTION CIRCUIT CHAPTER 24 BCD CORRECTION CIRCUIT 24.1 BCD Correction Circuit Function The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code with this circuit. The decimal correction operation result is obtained by performing addition/subtraction having the A register as the operand and then adding/ subtracting the BCD correction result register (BCDADJ).
Page 805: Bcd Correction Circuit Operation
R9A02G015 CHAPTER 24 BCD CORRECTION CIRCUIT 24.3 BCD Correction Circuit Operation The basic operation of the BCD correction circuit is as follows. (1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a BCD code value <1>...
Page 806 R9A02G015 CHAPTER 24 BCD CORRECTION CIRCUIT (2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using a BCD code value <1> The BCD code value from which subtraction is performed is stored in the A register.
Page 807: Instruction Set
R9A02G015 CHAPTER 25 INSTRUCTION SET CHAPTER 25 INSTRUCTION SET This chapter lists the instructions in the R9A02G015 instruction set. For details of each operation and operation code, refer to the separate document RL78 Family User’s Manual Software (R01US0015). 25.1 Conventions Used in Operation List 25.1.1...
Page 808: Description Of Operation Column
R9A02G015 CHAPTER 25 INSTRUCTION SET 25.1.2 Description of operation column The operation when the instruction is executed is shown in the “Operation” column using the following symbols. Table 25 - 2 Symbols in “Operation” Column Symbol Function A register; 8-bit accumulator...
Page 809: Description Of Flag Operation Column
R9A02G015 CHAPTER 25 INSTRUCTION SET 25.1.3 Description of flag operation column The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols. Table 25 - 3 Symbols in “Flag” Column...
Page 810: Operation List
R9A02G015 CHAPTER 25 INSTRUCTION SET 25.2 Operation List Table 25 - 5 Operation List (1/12) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 8-bit data r, #byte — r ← byte transfer PSW, #byte —...
Page 811 R9A02G015 CHAPTER 25 INSTRUCTION SET Table 25 - 5 Operation List (2/12) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 8-bit data [DE+byte], A — (DE + byte) ← A transfer A, ES:[DE+byte] A ← ((ES, DE) + byte) ES:[DE+byte], A —...
Page 812 R9A02G015 CHAPTER 25 INSTRUCTION SET Table 25 - 5 Operation List (3/12) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 8-bit data A, ES:[DE] — A ←→ (ES, DE) transfer A, [HL] — A ←→ (HL) A, ES:[HL] —...
Page 813 R9A02G015 CHAPTER 25 INSTRUCTION SET Table 25 - 5 Operation List (4/12) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 16-bit data MOVW AX, ES:[HL] AX ← (ES, HL) transfer ES:[HL], AX — (ES, HL) ← AX AX, [DE+byte] AX ←...
Page 814 R9A02G015 CHAPTER 25 INSTRUCTION SET Table 25 - 5 Operation List (5/12) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 8-bit A, saddr — A, C ← A + (saddr) × × × operation A, [HL] A, CY ←...
Page 815 R9A02G015 CHAPTER 25 INSTRUCTION SET Table 25 - 5 Operation List (6/12) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 8-bit SUBC A, [HL] A, CY ← A - (HL) - CY × ×...
Page 816 R9A02G015 CHAPTER 25 INSTRUCTION SET Table 25 - 5 Operation List (7/12) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY A ← A  (ES:HL) 8-bit A, ES:[HL] × operation A ← A  (HL + byte) A, [HL+byte] ×...
Page 817 R9A02G015 CHAPTER 25 INSTRUCTION SET Table 25 - 5 Operation List (8/12) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY 16-bit SUBW AX, #word — AX, CY ← AX - word × × ×...
Page 818 R9A02G015 CHAPTER 25 INSTRUCTION SET Table 25 - 5 Operation List (9/12) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY Increment/ DECW — rp ← rp - 1 decrement !addr16 — (addr16) ← (addr16) - 1 ES:!addr16 —...
Page 819 R9A02G015 CHAPTER 25 INSTRUCTION SET Table 25 - 5 Operation List (10/12) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY CY ← CY  bit XOR1 CY, A.bit — × manipulate CY ← CY  PSW.bit CY, PSW.bit...
Page 820 R9A02G015 CHAPTER 25 INSTRUCTION SET Table 25 - 5 Operation List (11/12) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY Call/return RETB — — ← (SP), PC ← (SP + 1), ← (SP + 2), PSW ← (SP + 3), SP ←...
Page 821 R9A02G015 CHAPTER 25 INSTRUCTION SET Table 25 - 5 Operation List (12/12) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note 1 Note 2 AC CY Conditional saddr.bit, $addr20 — PC ← PC + 4 + jdisp8 if (saddr).bit = 0...
Page 822 R9A02G015 CHAPTER 25 INSTRUCTION SET - V. 1.71 and later versions of the CA78K0R (Renesas Electronics compiler), for both C and assembly language source code - Service pack 1.40.3 and later versions of the EWRL78 (IAR compiler), for C language source code - GNURL78 (KPIT compiler), for C language source code Remark 1.
Page 823: Electrical Specifications
R9A02G015 CHAPTER 26 ELECTRICAL SPECIFICATIONS CHAPTER 26 ELECTRICAL SPECIFICATIONS R9A02G015 Data Sheet (R19DS0101E) For details, refer to R19UH0112EJ0100 Rev.1.00 Page 823 of 825 Mar 29, 2019...
Page 824: Package Drawings
R9A02G015 CHAPTER 27 PACKAGE DRAWINGS CHAPTER 27 PACKAGE DRAWINGS R9A02G015 Data Sheet (R19DS0101E) For details, refer to R19UH0112EJ0100 Rev.1.00 Page 824 of 825 Mar 29, 2019...
Page 825: Revision History
R9A02G015 REVISION HISTORY REVISION HISTORY R9A02G015 User’s Manual: Hardware Description Rev. Date Page Summary 0.10 Sep 28, 2018 — First Draft of the Preliminary User’s Manual 0.20 Dec 26, 2018 — The following chapters were newly added.  CHAPTER 5 CLOCK GENERATOR ...
Page 826 Colophon R9A02G015 User’s Manual: Hardware Publication Date: Rev.0.10 Sep 28, 2018 Rev.1.00 Mar 29, 2019 Published by: Renesas Electronics Corporation...
Page 827 Address List http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics Corporation TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan Renesas Electronics America Inc. 1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A. Tel: +1-408-432-8888, Fax: +1-408-434-5351...
Page 828 Back cover R9A02G015 R19UH0112EJ0100...

This manual is also suitable for:

R9a02g0150 R9a02g0151