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R9A02G0151
Renesas R9A02G0151 Manuals
Manuals and User Guides for Renesas R9A02G0151. We have
1
Renesas R9A02G0151 manual available for free PDF download: User Manual
Renesas R9A02G0151 User Manual (828 pages)
ASSP (USB Power Delivery Controller)
Brand:
Renesas
| Category:
Controller
| Size: 8 MB
Table of Contents
How to Use this Manual
4
Table of Contents
6
Outline
17
Features
17
Ordering Information
19
Pin Configuration (Top View)
20
32-Pin Product (with USB)
20
32-Pin Product (Without USB)
21
Pin Identification
22
Block Diagram
23
32-Pin Products
23
Outline of Functions
24
Pin Functions
26
Port Functions
26
32-Pin Products
26
Functions Other than Port Pins
28
Connection of Unused Pins
31
Pin Block Diagrams
32
Cpu Architecture
42
Memory Space
43
Internal Program Memory Space
45
Mirror Area
47
Internal Data Memory Space
48
Special Function Register (SFR) Area
49
Extended Special Function Register (2Nd SFR: 2Nd Special Function Register) Area
49
Data Memory Addressing
50
Processor Registers
51
Control Registers
51
General-Purpose Registers
53
And CS Registers
54
Special Function Registers (Sfrs)
55
Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)
59
Instruction Address Addressing
66
Relative Addressing
66
Immediate Addressing
66
Register Indirect Addressing
67
Addressing for Processing Data Addresses
68
Implied Addressing
68
Register Addressing
68
Direct Addressing
69
Short Direct Addressing
70
SFR Addressing
71
Register Indirect Addressing
72
Based Addressing
73
Based Indexed Addressing
76
Stack Addressing
77
Port Functions
80
Port Configuration
80
Port 0
80
Port 2
80
Port 4
81
Port 5
81
Port 6
81
Port 7
81
Port 12
81
Port 13
82
Registers Controlling Port Function
83
Port Mode Registers (Pmxx)
85
Port Registers (Pxx)
86
Pull-Up Resistor Option Registers (Puxx)
87
Port Input Mode Registers (Pimxx)
87
Port Output Mode Registers (Pomxx)
88
Port Mode Control Registers (Pmcxx)
88
Port Function Operations
89
Writing to I/O Port
89
Reading from I/O Port
89
Operations on I/O Port
89
Handling Different Potential (1.8 V, 2.5 V) by Using I/O Buffers
90
Register Settings When Using Alternate Function
92
Basic Concept When Using Alternate Function
92
Register Settings for Alternate Function Whose Output Function Is Not Used
93
Register Setting Examples for Used Port and Alternate Functions
94
Cautions When Using Port Function
99
Cautions on 1-Bit Manipulation Instruction for Port Register N (Pn)
99
Notes on Specifying the Pin Settings
100
Clock Generator
101
Functions of Clock Generator
101
Configuration of Clock Generator
103
Registers Controlling Clock Generator
105
Clock Operation Mode Control Register (CMC)
106
System Clock Control Register (CKC)
107
Clock Operation Status Control Register (CSC)
108
Oscillation Stabilization Time Counter Status Register (OSTC)
109
Oscillation Stabilization Time Select Register (OSTS)
111
Peripheral Enable Registers 0, 2 (PER0, PER2)
113
Subsystem Clock Supply Mode Control Register (OSMC)
115
High-Speed On-Chip Oscillator Frequency Select Register (HOCODIV)
116
High-Speed On-Chip Oscillator Trimming Register (HIOTRM)
117
PLL Control Register (DSCCTL)
118
Main Clock Control Register (MCKC)
120
USB Clock Selection Register (UCKSEL)
121
System Clock Oscillator
122
X1 Oscillator
122
High-Speed On-Chip Oscillator
125
Low-Speed On-Chip Oscillator
125
PLL (Phase Locked Loop)
125
Clock Generator Operation
126
Controlling Clock
128
Example of Setting High-Speed On-Chip Oscillator
128
Example of Setting X1 Oscillation Clock
130
Example of Setting PLL Circuit
131
CPU Clock Status Transition Diagram
133
Condition before Changing CPU Clock and Processing after Changing CPU Clock
138
Time Required for Switchover of CPU Clock and System Clock
140
Conditions before Clock Oscillation Is Stopped
141
Resonator and Oscillator Constants
142
Timer Array Unit
145
Functions of Timer Array Unit
146
Independent Channel Operation Function
146
Simultaneous Channel Operation Function
147
8-Bit Timer Operation Function (Channels 1 and 3 Only)
148
Configuration of Timer Array Unit
149
Timer Count Register Mn (Tcrmn)
155
Timer Data Register Mn (Tdrmn)
157
Registers Controlling Timer Array Unit
158
Peripheral Enable Register 0 (PER0)
159
Timer Clock Select Register M (Tpsm)
160
Timer Mode Register Mn (Tmrmn)
163
Timer Status Register Mn (Tsrmn)
168
Timer Channel Enable Status Register M (Tem)
169
Timer Channel Start Register M (Tsm)
170
Timer Channel Stop Register M (Ttm)
171
Timer Input Select Register 0 (TIS0)
172
Timer Output Enable Register M (Toem)
173
Timer Output Register M (Tom)
174
Timer Output Level Register M (Tolm)
175
Timer Output Mode Register M (Tomm)
176
Noise Filter Enable Register 1 (NFEN1)
177
Registers that Control Port Functions of Timer Input/Output Pins
179
Basic Rules of Timer Array Unit
180
Basic Rules of Simultaneous Channel Operation Function
180
Basic Rules of 8-Bit Timer Operation Function (Channels 1 and 3 Only)
182
Operation of Counter
183
Count Clock (F TCLK )
183
Start Timing of Counter
185
Operation of Counter
186
Channel Output (Tomn Pin) Control
191
Tomn Pin Output Circuit Configuration
191
Tomn Pin Output Setting
192
Cautions on Channel Output Operation
193
Collective Manipulation of Tomn Bit
198
Timer Interrupt and Tomn Pin Output at Operation Start
199
Timer Input (Timn) Control
200
Timn Input Circuit Configuration
200
Noise Filter
200
Cautions on Channel Input Operation
201
Independent Channel Operation Function of Timer Array Unit
202
Operation as Interval Timer/Square Wave Output
202
Operation as External Event Counter
207
Operation as Input Pulse Interval Measurement
211
Operation as Input Signal High-/Low-Level Width Measurement
215
Operation as Delay Counter
219
Simultaneous Channel Operation Function of Timer Array Unit
223
Operation as One-Shot Pulse Output Function
223
Operation as PWM Function
230
Operation as Multiple PWM Output Function
237
Cautions When Using Timer Array Unit
245
Cautions When Using Timer Output
245
Bit Interval Timer
246
Functions of 12-Bit Interval Timer
246
Configuration of 12-Bit Interval Timer
246
Registers Controlling 12-Bit Interval Timer
247
Peripheral Enable Register 2 (PER2)
247
Peripheral Reset Control Register 2 (PRR2)
248
Subsystem Clock Supply Mode Control Register (OSMC)
248
12-Bit Interval Timer Control Register (ITMC)
249
12-Bit Interval Timer Operation
250
12-Bit Interval Timer Operation Timing
250
Start of Count Operation and Re-Enter to HALT/STOP Mode after Returned from HALT/STOP Mode
251
Clock Output/Buzzer Output Controller
252
Functions of Clock Output/Buzzer Output Controller
252
Configuration of Clock Output/Buzzer Output Controller
254
Registers Controlling Clock Output/Buzzer Output Controller
254
Clock Output Select Registers N (Cksn)
254
Registers Controlling Port Functions of Pins to be Used for Clock or Buzzer Output
256
Operations of Clock Output/Buzzer Output Controller
257
Operation as Output Pin
257
Cautions of Clock Output/Buzzer Output Controller
257
Watchdog Timer
258
Functions of Watchdog Timer
258
Configuration of Watchdog Timer
259
Register Controlling Watchdog Timer
260
Watchdog Timer Enable Register (WDTE)
260
Operation of Watchdog Timer
261
Controlling Operation of Watchdog Timer
261
Setting Overflow Time of Watchdog Timer
262
Setting Window Open Period of Watchdog Timer
263
Setting Watchdog Timer Interval Interrupt
264
A/D Converter
265
Function of A/D Converter
265
Configuration of A/D Converter
268
Registers Controlling A/D Converter
270
Peripheral Enable Register 0 (PER0)
271
A/D Converter Mode Register 0 (ADM0)
272
A/D Converter Mode Register 1 (ADM1)
278
A/D Converter Mode Register 2 (ADM2)
279
10-Bit A/D Conversion Result Register (ADCR)
281
8-Bit A/D Conversion Result Register (ADCRH)
282
Analog Input Channel Specification Register (ADS)
283
Conversion Result Comparison Upper Limit Setting Register (ADUL)
285
Conversion Result Comparison Lower Limit Setting Register (ADLL)
285
A/D Test Register (ADTES)
286
10.3.11 Registers Controlling Port Function of Analog Input Pins
286
A/D Converter Conversion Operations
287
Input Voltage and Conversion Results
289
A/D Converter Operation Modes
290
Software Trigger Mode (Select Mode, Sequential Conversion Mode)
290
Software Trigger Mode (Select Mode, One-Shot Conversion Mode)
291
Software Trigger Mode (Scan Mode, Sequential Conversion Mode)
292
Software Trigger Mode (Scan Mode, One-Shot Conversion Mode)
293
Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)
294
Operation Timing
294
Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode)
295
Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)
296
Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode)
297
Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
298
Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)
299
Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)
300
Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode)
301
A/D Converter Setup Flowchart
302
Setting up Software Trigger Mode
302
Setting up Hardware Trigger No-Wait Mode
303
Setting up Hardware Trigger Wait Mode
304
Setup When Using Temperature Sensor (Example for Software Trigger Mode and One-Shot Conversion Mode)
305
Setting up Test Mode
306
SNOOZE Mode Function
307
How to Read A/D Converter Characteristics Table
311
Conversion Time
313
Sampling Time
313
10.10 Cautions for A/D Converter
314
Serial Array Unit
318
Functions of Serial Array Unit
319
3-Wire Serial I/O (CSI00, CSI01)
319
Uart (Uart0)
320
Simplified I 2 C (IIC00, IIC01)
321
Configuration of Serial Array Unit
322
Shift Register
325
Lower 8/9 Bits of the Serial Data Register Mn (Sdrmn)
325
Registers Controlling Serial Array Unit
327
Peripheral Enable Register 0 (PER0)
328
Peripheral Reset Control Register 0 (PRR0)
329
Serial Clock Select Register M (Spsm)
330
Serial Mode Register Mn (Smrmn)
332
Serial Communication Operation Setting Register Mn (Scrmn)
333
Serial Data Register Mn (Sdrmn)
336
Serial Flag Clear Trigger Register Mn (Sirmn)
337
Serial Status Register Mn (Ssrmn)
338
Serial Channel Start Register M (Ssm)
340
Serial Channel Stop Register M (Stm)
341
Serial Channel Enable Status Register M (Sem)
342
Serial Output Enable Register M (Soem)
343
Serial Output Register M (Som)
344
Serial Output Level Register M (Solm)
345
Serial Standby Control Register M (Sscm)
347
Noise Filter Enable Register 0 (NFEN0)
349
11.3.17 Registers Controlling Port Functions of Serial Input/Output Pins
350
Operation Stop Mode
351
Stopping the Operation by Units
351
Stopping the Operation by Channels
352
Operation of 3-Wire Serial I/O (CSI00, CSI01) Communication
353
Master Transmission
355
Register Setting
356
Operation Procedure
357
Master Reception
363
Master Transmission/Reception
371
Slave Transmission
379
Slave Reception
387
Slave Transmission/Reception
393
SNOOZE Mode Function
401
Calculating Transfer Clock Frequency
405
Procedure for Processing Errors that Occurred During 3-Wire Serial I/O (CSI00, CSI01) Communication
407
Operation of UART (UART0) Communication
408
UART Transmission
410
Register Setting
411
Operation Procedure
413
UART Reception
419
Processing Flow
424
SNOOZE Mode Function
426
Calculating Baud Rate
434
Procedure for Processing Errors that Occurred During UART (UART0) Communication
438
Operation of Simplified I 2 C (IIC00, IIC01) Communication
439
Address Field Transmission
441
Register Setting
442
Processing Flow
444
Data Transmission
446
Data Reception
449
Stop Condition Generation
453
Calculating Transfer Rate
454
Procedure for Processing Errors that Occurred During Simplified I 2 C (IIC00, IIC01) Communication
456
Serial Interface Iica
457
Functions of Serial Interface IICA
457
Configuration of Serial Interface IICA
460
Registers Controlling Serial Interface IICA
463
Peripheral Enable Register 0 (PER0)
464
IICA Control Register N0 (Iicctln0)
464
IICA Status Register N (Iicsn)
469
IICA Flag Register N (Iicfn)
471
IICA Control Register N1 (Iicctln1)
473
IICA Low-Level Width Setting Register N (Iicwln)
475
IICA High-Level Width Setting Register N (Iicwhn)
475
Port Mode Registers 6, 7 (PM6, PM7)
476
I 2 C Bus Mode Functions
477
Pin Configuration
477
Setting Transfer Clock by Using Iicwln and Iicwhn Registers
478
I 2 C Bus Definitions and Control Methods
480
Start Conditions
480
Addresses
481
Transfer Direction Specification
481
Acknowledge (ACK)
482
Stop Condition
483
Wait
484
Canceling Wait
486
Interrupt Request (Intiican) Generation Timing and Wait Control
487
Address Match Detection Method
488
12.5.10 Error Detection
488
12.5.11 Extension Code
489
12.5.12 Arbitration
490
12.5.13 Wakeup Function
492
12.5.14 Communication Reservation
495
12.5.15 Cautions
499
12.5.16 Communication Operations
500
Timing of I C Interrupt Request (Intiican) Occurrence
508
Timing Charts
529
Usb 2.0 Host/Function Module (Usb)
544
Functions of USB 2.0 Host/Function Module
544
Configuration of USB 2.0 Host/Function Module
546
Registers Used in USB 2.0 Host/Function Module
549
System Configuration Control Register (SYSCFG), System Configuration Control Register 1 (SYSCFG1)
551
System Configuration Status Register N (Sysstsn) (N = 0, 1)
554
Device State Control Register N (Dvstctrn) (N = 0, 1)
555
CFIFO Port Register (CFIFOM), Dnfifo Port Register (Dnfifom) (N = 0, 1)
560
CFIFO Port Select Register (CFIFOSEL), Dnfifo Port Select Register (Dnfifosel) (N = 0, 1)
562
CFIFO Port Control Register (CFIFOCTR), Dnfifo Port Control Register (Dnfifoctr) (N = 0, 1)
566
Interrupt Enable Register 0 (INTENB0)
570
Interrupt Enable Register N (Intenbn) (N = 1, 2)
572
BRDY Interrupt Enable Register (BRDYENB)
575
NRDY Interrupt Enable Register (NRDYENB)
575
BEMP Interrupt Enable Register (BEMPENB)
576
SOF Output Configuration Register (SOFCFG)
577
Interrupt Status Register 0 (INTSTS0)
578
Interrupt Status Register N (Intstsn) (N = 1, 2)
581
BRDY Interrupt Status Register (BRDYSTS)
586
NRDY Interrupt Status Register (NRDYSTS)
586
BEMP Interrupt Status Register (BEMPSTS)
587
Frame Number Register (FRMNUM)
587
USB Address Register (USBADDR)
588
USB Request Type Register (USBREQ)
589
USB Request Value Register (USBVAL)
589
USB Request Index Register (USBINDX)
590
USB Request Length Register (USBLENG)
590
DCP Configuration Register (DCPCFG)
591
DCP Maximum Packet Size Register (DCPMAXP)
592
DCP Control Register (DCPCTR)
593
Pipe Window Select Register (PIPESEL)
596
Pipe Configuration Register (PIPECFG)
597
Pipe Maximum Packet Size Register (PIPEMAXP)
599
Pipe Cycle Control Register (PIPEPERI)
600
Pipen Control Registers (Pipenctr) (N = 4 to 7)
601
Pipen Transaction Counter Enable Registers (Pipentre) (N = 4, 5)
608
Pipen Transaction Counter Registers (Pipentrn) (N = 4, 5)
609
BC Control Register N (Usbbcctrln) (N = 0, 1)
610
BC Option Control Register N (Usbbcoptn) (N = 0, 1)
614
USB Clock Selection Register (UCKSEL)
618
USB Module Control Register (USBMC)
619
Device Address N Configuration Registers (Devaddn) (N = 0 to 5)
620
Operation
621
System Control
621
Starting Operation
621
Interrupt Sources
626
Interrupts
630
Overcurrent Interrupt
639
Pipe Control
642
Transfer Types
643
FIFO Buffer Memory
647
Control Transfers (DCP)
651
Bulk Transfers (PIPE4, PIPE5)
653
Interrupt Transfers (PIPE6, PIPE7)
653
SOF Interpolation Function
654
13.4.10 Pipe Schedule
655
13.4.11 Controlling Battery Charging Detection
656
13.4.12 Battery Charging Connection Detection Optional Functions
658
13.4.13 Battery Charging Detection Processing
661
Interrupt Functions
666
Interrupt Function Types
666
Interrupt Sources and Configuration
666
Registers Controlling Interrupt Functions
671
Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)
674
Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
676
Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H)
677
External Interrupt Rising Edge Enable Register (EGP0, EGP1), External Interrupt Falling Edge Enable Register (EGN0, EGN1)
679
Program Status Word (PSW)
681
Interrupt Servicing Operations
682
Maskable Interrupt Request Acknowledgment
682
Software Interrupt Request Acknowledgment
685
Multiple Interrupt Servicing
685
Interrupt Servicing During Division Instruction
689
Interrupt Request Hold
691
Standby Function
692
Registers Controlling Standby Function
693
Standby Function Operation
694
HALT Mode
694
STOP Mode
698
SNOOZE Mode
703
Reset Function
706
Timing of Reset Operation
708
Register for Confirming Reset Source
712
Reset Control Flag Register (RESF)
712
Peripheral Reset Control Register 0 (PRR0)
715
Peripheral Reset Control Register 2 (PRR2)
716
Power-On-Reset Circuit
717
Functions of Power-On-Reset Circuit
717
Configuration of Power-On-Reset Circuit
718
Operation of Power-On-Reset Circuit
718
Voltage Detector
722
Functions of Voltage Detector
722
Configuration of Voltage Detector
724
Registers Controlling Voltage Detector
724
Voltage Detection Register (LVIM)
725
Voltage Detection Level Register (LVIS)
726
Operation of Voltage Detector
730
When Used as Reset Mode
730
When Used as Interrupt Mode
732
When Used as Interrupt and Reset Mode
734
Changing of LVD Detection Voltage Setting
739
Changing of LVD Detection Voltage Setting in LVD Reset Mode
740
Changing of LVD Detection Voltage Setting in LVD Interrupt Mode
741
Cautions for Voltage Detector
743
Safety Functions
745
Overview of Safety Functions
745
Registers Used by Safety Functions
746
Operation of Safety Functions
746
Flash Memory CRC Operation Function (High-Speed CRC)
746
CRC Operation Function (General-Purpose CRC)
750
RAM Parity Error Detection Function
753
RAM Guard Function
755
SFR Guard Function
756
Invalid Memory Access Detection Function
757
Frequency Detection Function
759
A/D Test Function
761
Digital Output Signal Level Detection Function for I/O Pins
763
Regulator
764
Regulator Overview
764
Option Byte
765
Functions of Option Bytes
765
User Option Byte (000C0H to 000C2H/010C0H to 010C2H)
765
On-Chip Debug Option Byte (000C3H/010C3H)
766
Format of User Option Byte
767
Format of On-Chip Debug Option Byte
774
Setting of Option Byte
775
Flash Memory
776
Serial Programming Using Flash Memory Programmer
777
Programming Environment
779
Communication Mode
779
Serial Programming Using External Device (that Incorporates UART)
780
Programming Environment
780
Communication Mode
781
Connection of Pins on Board
782
P40/TOOL0 Pin
782
RESETB Pin
782
Port Pins
783
REGC Pin
783
X1 and X2 Pins
783
Power Supply
783
Programming Method
784
Serial Programming Procedure
784
Flash Memory Programming Mode
785
Selecting Communication Mode
787
Communication Commands
788
Processing Time for each Command When PG-FP6 Is in Use (Reference Value)
790
Self-Programming
791
Self-Programming Procedure
792
Boot Swap Function
793
Flash Shield Window Function
795
Security Settings
796
Data Flash
798
Data Flash Overview
798
Register Controlling Data Flash Memory
799
Procedure for Accessing Data Flash Memory
800
On-Chip Debug Function
801
Connecting E1 On-Chip Debugging Emulator
801
On-Chip Debug Security ID
802
Securing of User Resources
802
Bcd Correction Circuit
804
BCD Correction Circuit Function
804
Registers Used by BCD Correction Circuit
804
BCD Correction Result Register (BCDADJ)
804
BCD Correction Circuit Operation
805
Instruction Set
807
Conventions Used in Operation List
807
Operand Identifiers and Specification Methods
807
Description of Operation Column
808
Description of Flag Operation Column
809
PREFIX Instruction
809
Operation List
810
Electrical Specifications
823
Package Drawings
824
Revision History
825
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