Renesas R61509V Specification
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Renesas R61509V Specification

Renesas R61509V Specification

260k-color, 240rgb x 432-dot graphics liquid crystal controller driver for amorphous-silicon tft panel
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R61509V
260k-color, 240RGB x 432-dot graphics liquid crystal
controller driver for Amorphous-Silicon TFT Panel
Description ......................................................................................................... 6
Features
......................................................................................................... 7
Power Supply Specifications .............................................................................. 8
Differences Between R61509 and R61509V...................................................... 9
Block Diagram .................................................................................................... 10
Block Function.................................................................................................... 11
1. System Interface.....................................................................................................................................................11
2. External Display Interface (RGB, VSYNC interfaces)........................................................................................12
3. Address Counter (AC) ...........................................................................................................................................12
4. Graphics RAM (GRAM)........................................................................................................................................13
5. Grayscale Voltage Generating Circuit..................................................................................................................13
6. Liquid Crystal Drive Power Supply Circuit..........................................................................................................13
7. Timing Generator ..................................................................................................................................................13
8. Oscillator (OSC).....................................................................................................................................................13
9. Liquid crystal driver Circuit ..................................................................................................................................13
10. Internal Logic Power Supply Regulator...............................................................................................................13
Pin Function ........................................................................................................ 14
Pad Arrangement ................................................................................................ 19
Pad coordinate..................................................................................................... 21
Bump Arrangement............................................................................................. 36
Connection Example........................................................................................... 37
GRAM Address Map .......................................................................................... 38
Instruction ......................................................................................................... 40
Rev. 0.11 April 25, 2008, page 1 of 181
Target Spec
REJxxxxxxx-xxxx
Rev.0.11
April 25, 2008

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  • Page 1 April 25, 2008 Description ......................6 Features ......................7 Power Supply Specifications ................8 Differences Between R61509 and R61509V............9 Block Diagram ....................10 Block Function....................11 1. System Interface..............................11 2. External Display Interface (RGB, VSYNC interfaces)..................12 3. Address Counter (AC) ............................12 4.
  • Page 2 R61509V Target Spec Outline ..................................40 Instruction Data Format..............................40 Index (IR) ..................................41 Display control ................................41 Device code read (R000h) ............................41 Driver Output Control (R001h)..........................41 LCD Drive Wave Control (R002h).........................42 Entry Mode (R003h) ...............................42 Display Control 1 (R007h) .............................45 Display Control 2 (R008h) .............................46 Display Control 3 (R009h) .............................48...

  • Page 3: Table Of Contents

    NVM Access Control 1 (R6F0h), NVM Access Control 2 (R6F1h), NVM Access Control 3 (R6F2h)....90 Instruction List ....................92 Reset Function ....................93 Basic Mode Operation of the R61509V.............. 95 Interface and Data Format .................. 96 System Interface....................99 80-System 18-bit Bus Interface ...........................100 80-System 16-bit Bus Interface ...........................101...
  • Page 4 R61509V Target Spec Partial Display Function ..................139 Liquid Crystal Panel Interface Timing ............... 140 Internal Clock Operation.............................140 RGB Interface Operation.............................141 γ Correction Function..................142 γ Correction Function..............................142 γ Correction Circuit..............................142 γ Correction Registers ..............................143 Reference level adjustment registers...........................143 Interpolation Registers..............................145 Frame Memory Data and the Grayscale Voltage.......................148...
  • Page 5 R61509V Target Spec Clock Characteristics .............................172 80-system 18-/16-/9-/8-bit Bus interface Timing Characteristics .................172 Clock Synchronous Serial Interface Timing Characteristics.................173 RGB Interface Timing Characteristics........................173 LCD Driver Output Characteristics........................174 Reset Timing Characteristics ..........................174 Notes to Electrical Characteristics ..........................175 Test Circuits..................................176 Timing Characteristics..............................177 80-system Bus Interface............................177...
  • Page 6 The power supply circuit incorporates step-up circuit and voltage follower circuit to generate TFT liquid crystal panel drive voltages. The R61509V’s power management functions such as 8-color display and shut down and so on make this LSI an ideal driver for the medium or small sized portable products with color display systems such as digital cellular phones or small PDAs, where long battery life is a major concern.
  • Page 7 R61509V Target Spec Features • A single-chip controller driver incorporating a gate circuit and a power supply circuit for a maximum 240RGB x 432dots graphics display on amorphous TFT panel in 262k colors • System interface – High-speed interfaces via 8-, 9-, 16-, 18-bit parallel ports –...

  • Page 8: Power Supply Specifications

    R61509V Target Spec Power Supply Specifications Table 1 Item R61509V TFT data lines 720 output TFT gate lines 432 output TFT display storage capacitance Cst only (Common VCOM formula) Liquid crystal S1~S720 V0 ~ V63 grayscales drive output G1~G432 VGH-VGL...
  • Page 9 R281h VCOM High Voltage 1 VCM1[4-0] Defines VCOMH 1level VCM1[4-0] NVM specification changed. VCM bit is moved to R280h. Deleted. (Because the R61509V supports both NVM write and erase R282h VCOM High Voltage 2 Defines VCOMH 2level VCMSEL VCM2 functions).

  • Page 10: Block Diagram

    R61509V Target Spec Block Diagram Index Control Register (IR) AGND Register Address (CR) Counter IOVCC System IM2-1, IM0_ID interface Write data Graphic RAM 18 bit latch 16 bit (GRAM) WR_SCL 9 bit 233,280byte 8 bit Read data Serial latch DB17-0...
  • Page 11 The data is read via RDR from the internal GRAM. Therefore, invalid data is sent to the data bus when the R61509V performs the first read operation from the internal GRAM. Valid data is read out when the R61509V performs the second and subsequent read operation.
  • Page 12 Setting disabled External Display Interface (RGB, VSYNC interfaces) The R61509V supports RGB and VSYNC interfaces as the external interface to display moving picture. When the RGB interface is selected, the display operation is synchronized with externally supplied synchronous signals (VSYNCX, HSYNCX, and DOTCLK). In RGB interface operation, data (DB17-0) is written in synchronization with these signals when the polarity of enable signal (ENABLE) allows write operation in order to prevent flicker when updating display data.
  • Page 13 Liquid crystal driver Circuit The liquid crystal driver circuit of the R61509V consists of a 720-output source driver (S1 ~ S720) and a 432-output gate driver (G1~G432). The display pattern data is latched when all of 240RGB data are inputted.
  • Page 14 Chip selection signal. (Amplitude: IOVCC-GND) Host Low: The R61509V is selected and accessible. IOVCC processor High: The R61509V is not selected and not accessible. Register selection signal. (Amplitude: IOVCC-GND) Host IOVCC Low: Index register is selected. processor High: Control register is selected.
  • Page 15 ― Note 1: 65,536 colors in one-transfer operation. Note 2: 65,536 colors in two-transfer operation. Host Reset pin. The R61509V is reset when RESETX is low. Make processor RESETX sure to execute a power on reset after turning power on.
  • Page 16 R61509V Target Spec Reset protect pin. The R61509V enters a reset protect status by fixing PROTECT to GND level disabling hardware reset. With Host this, erroneous operations caused by noise are prevented. PROTECT IOVCC processor Low: Hardware reset is disabled (Reset protect status) High: Hardware reset is enabled.
  • Page 17 R61509V Target Spec Table 8 LCD drive When not in Signal Connect to Function VREG1OUT O Stabilizing Output voltage generated from the reference voltage VCIR. The factor capacitor is determined by instruction (VRH bits). VREG1OUT is used for (1) source driver grayscale reference voltage ―...
  • Page 18 R61509V Target Spec Table 9 Others (test, dummy pins) When not in Signal Connect to Function VTEST Open Test pin. Leave open. Open VREFC Test pin. Make sure to fix to the GND level. VREFD Open Test pin. Leave open.
  • Page 19 R61509V Pad Arrangement Rev 0.6 Rev0.00 2007.12.13 First virsion Rev0.10 2007.12.27 R61517's VCOMA, VCOMB --> R61509V's VCOM Rev0.20 2008.02.13　Rev Mark 1 PAD No. 24～28, 71, 72, 208-217 changed to NC1-NC17 Rev0.21 2008.02.14　Rev Mark 2 NC's application voltage decided. Rev0.30 2008.02.19　Rev Mark 4 VPP3C-->VPP3B, VPP2-->VPP1 Rev0.31 2008.02.27 Rev Mark 5 NC1-5-->DUMMYA...
  • Page 20 R61509V Target Spec ●Chip size: 19.03mm x 0.76mm ●Chip thickness: 280μm (typ) ●Pad coordinates: Pad center ●Coordinate origin: Chip center ●Au bump size 1. 50μm x 90μm (I/O side: No.1-262) 2. 15μm x 100μm (LCD output side: No.263-1434) ●Au bump pitch: See pad coordinate ●Au bump height:12μm...
  • Page 21 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name pad No pad name 1 DUMMYR1 -9135.0 -269.0 51 TS5 -5635.0 -269.0 2 DUMMYR2 -9065.0 -269.0 52 TS4 -5565.0 -269.0 3 AGNDDUM1 -8995.0 -269.0 53 TS3 -5495.0 -269.0 4 VPP3B -8925.0...
  • Page 22 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name pad No pad name 101 GNDDUM8 -2135.0 -269.0 151 GND 1365.0 -269.0 102 DB3 -2065.0 -269.0 152 GND 1435.0 -269.0 103 DB2 -1995.0 -269.0 153 GND 1505.0 -269.0 104 DB1 -1925.0...
  • Page 23 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name pad No pad name 201 VCI 4865.0 -269.0 251 C21M 8365.0 -269.0 202 VCI 4935.0 -269.0 252 C21M 8435.0 -269.0 203 VCI 5005.0 -269.0 253 C21P 8505.0 -269.0 204 VCI 5075.0...
  • Page 24 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name pad No pad name 301 G70 8827.5 157.0 351 G170 8077.5 157.0 302 G72 8812.5 276.0 352 G172 8062.5 276.0 303 G74 8797.5 157.0 353 G174 8047.5 157.0 304 G76 8782.5...
  • Page 25 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name pad No pad name 401 G270 7327.5 157.0 451 G370 6577.5 157.0 402 G272 7312.5 276.0 452 G372 6562.5 276.0 403 G274 7297.5 157.0 453 G374 6547.5 157.0 404 G276 7282.5...
  • Page 26 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name pad No pad name 501 S704 5632.5 276.0 551 S654 4882.5 276.0 502 S703 5617.5 157.0 552 S653 4867.5 157.0 503 S702 5602.5 276.0 553 S652 4852.5 276.0 504 S701 5587.5...
  • Page 27 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name pad No pad name 601 S604 4132.5 276.0 651 S554 3382.5 276.0 602 S603 4117.5 157.0 652 S553 3367.5 157.0 603 S602 4102.5 276.0 653 S552 3352.5 276.0 604 S601 4087.5...
  • Page 28 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name pad No pad name 701 S504 2632.5 276.0 751 S454 1882.5 276.0 702 S503 2617.5 157.0 752 S453 1867.5 157.0 703 S502 2602.5 276.0 753 S452 1852.5 276.0 704 S501 2587.5...
  • Page 29 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name pad No pad name 801 S404 1132.5 276.0 851 TESTO12 -457.5 276.0 802 S403 1117.5 157.0 852 TESTO13 -472.5 157.0 803 S402 1102.5 276.0 853 S360 -487.5 276.0 804 S401 1087.5...
  • Page 30 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name pad No pad name 901 S312 -1207.5 276.0 951 S262 -1957.5 276.0 902 S311 -1222.5 157.0 952 S261 -1972.5 157.0 903 S310 -1237.5 276.0 953 S260 -1987.5 276.0 904 S309 -1252.5...
  • Page 31 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name pad No pad name 1001 S212 -2707.5 276.0 1051 S162 -3457.5 276.0 1002 S211 -2722.5 157.0 1052 S161 -3472.5 157.0 1003 S210 -2737.5 276.0 1053 S160 -3487.5 276.0 1004 S209 -2752.5...
  • Page 32 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name pad No pad name 1101 S112 -4207.5 276.0 1151 S62 -4957.5 276.0 1102 S111 -4222.5 157.0 1152 S61 -4972.5 157.0 1103 S110 -4237.5 276.0 1153 S60 -4987.5 276.0 1104 S109 -4252.5...
  • Page 33 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name pad No pad name 1201 S12 -5707.5 276.0 1251 G359 -6652.5 157.0 1202 S11 -5722.5 157.0 1252 G357 -6667.5 276.0 1203 S10 -5737.5 276.0 1253 G355 -6682.5 157.0 1204 S9 -5752.5...
  • Page 34 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name pad No pad name 1301 G259 -7402.5 157.0 1351 G159 -8152.5 157.0 1302 G257 -7417.5 276.0 1352 G157 -8167.5 276.0 1303 G255 -7432.5 157.0 1353 G155 -8182.5 157.0 1304 G253 -7447.5...
  • Page 35 R61509V Pad Coordinate （Unit：μm） 2008.04.21 rev0.1 pad No pad name Alignment mark 1401 G59 -8902.5 157.0 -9381.0 -251.0 1402 G57 -8917.5 276.0 9381.0 -251.0 1403 G55 -8932.5 157.0 1404 G53 -8947.5 276.0 1405 G51 -8962.5 157.0 1406 G49 -8977.5 276.0 Rev0.1 2008.04.21...
  • Page 36 R61509V Target Spec Bump Arrangement S=1,500um Unit : um S=4,500um Unit : um Figure 3 Rev. 0.11 April 25, 2008, page 36 of 181...
  • Page 37 R61509V, make sure that the R61517's VCOMA and VCOMB for VCOM drive mode are same polarity. The R61509V does not have VCOM output pin on the output 1uF/6V/B side (the area is just flat surface). When supplying voltage to panel from four corners of it, draw wires from VCOM pins on the I/O side.
  • Page 38 R61509V Target Spec GRAM Address Map Table 11 GRAM address and display position on the panel (SS = 0, BGR = 0) S/G pin ・・・・・ GS=0 GS=1 WD[17:0] WD[17:0] WD[17:0] WD[17:0] WD[17:0] WD[17:0] WD[17:0] WD[17:0] ・・・・・ G432 h00000 h00001 h00002...
  • Page 39 R61509V Target Spec Table 12 GRAM address and display position on the panel (SS = 1, BGR = 1) S/G pin ・・・・・ GS=0 GS=1 WD[17:0] WD[17:0] WD[17:0] WD[17:0] ・・・・・ WD[17:0] WD[17:0] WD[17:0] WD[17:0] G432 h00000 h00001 h00002 h00003 h000EC h000ED...
  • Page 40 The R61509V adopts 18-bit bus architecture in order to interface to high-performance microcomputer in high speed. The R61509V starts internal processing after storing control information (18, 16, 9, 8, 1 bit(s)), sent from the microcomputer, in the instruction register (IR) and the data register (DR). Since the internal...
  • Page 41 R61509V Target Spec Index (IR) IB15 IB14 IB13 IB12 IB11 IB10 [10] The index register specifies the indexes of control register or RAM control to be accessed. It is prohibited to access registers and instruction bits to which no index register is assigned.
  • Page 42 GRAM of the R61509V. AM: Sets either horizontal or vertical direction in updating the address counter automatically as the R61509V writes data to the internal GRAM. AM = “0”, sets the horizontal direction. AM = “1”, sets the vertical direction.
  • Page 43 R61509V Target Spec BGR: Reverses the order from RGB to BGR in writing 18-bit pixel data in the GRAM. BGR = 0: Write data in the order of RGB to the GRAM. BGR = 1: Reverse the order from RGB to BGR in writing data to the GRAM.
  • Page 44 R61509V Target Spec ID1-0 = 01 ID1-0 = 10 ID1-0 = 11 ID1-0 = 00 ORG = 0 Horizontal: Increment Horizontal: Decrement Horizontal: Increment Horizontal: Decrement Vertical: Decrement Vertical: Increment Vertical: Increment Vertical: Decrement AM = 0 17'h00000 17'h00000 17'h00000...
  • Page 45 IB15 IB14 IB13 IB12 IB11 IB10 Default BASEE: Base image display enable bit. BASEE = 0: No base image is displayed. The R61509V drives the LCD at non-lit display level or displays partial images. BASEE = 1: A base image is displayed.
  • Page 46 R61509V Target Spec Display Control 2 (R008h) IB15 IB14 IB13 IB12 IB11 IB10 Default FP[7:0]: Sets the number of lines for front porch period (a blank period made after the end of display). BP[7:0]: Sets the number of lines for back porch period (a blank period made before the beginning of display).
  • Page 47 R61509V Target Spec VSYNCX Back porch Display Area Front porch Note: The output timing to the panel is delayed by 2 line period from the synchronous signal (VSYNCX) input. Figure 5 Front and Back Porch Periods Note on Setting BP and FP: Set the BP and FP bits as follows in the following operation modes, respectively.
  • Page 48 R61509V Target Spec Display Control 3 (R009h) IB15 IB14 IB13 IB12 IB11 IB10 PTV PTS Default PTS: Sets the source output level to drive non-display area. PTS also selects operation of grayscale amplifier and step-up clock frequency. Table 15 Non-lit display area...
  • Page 49 IB11 IB10 Default value COL: When COL = 1, the R61509V enters the eight-color display mode. RAM data rewrite operation is not required when setting the eight-color display mode. Set the 8-color mode instruction according to the 8-color mode sequence.
  • Page 50 Default RIM: Sets the interface format when RGB interface is selected by RM and DM bits. Set RIM bit before starting display operation via the external display interface. Do not change the setting while the R61509V performs display operation. Table 18...
  • Page 51 R61509V Target Spec ENC[2:0]: Sets the RAM write cycle via RGB interface. Table 21 ENC[2:0] RAM Write Cycle (frame periods) 3’h0 1 frame 3’h1 2 frames 3’h2 3 frames 3’h3 4 frames 3’h4 5 frames 3’h5 6 frames 3’h6 7 frames 3’h7...
  • Page 52 R61509V Target Spec External Display Interface Control 2 (R00Fh) IB15 IB14 IB13 IB12 IB11 IB10 VSPL HSPL Default value DPL: Sets the signal polarity of DOTCLK pin. DPL = 0: input data on the rising edge of DOTCLK DPL = 1: input data on the falling edge of DOTCLK EPL: Sets the signal polarity of ENABLE pin.
  • Page 53 RTNI RTNI RTNI RTNI RTNI Default RTNI[4:0]: Sets 1H (line) period. This setting is valid when the R61509V’s display operation is synchronized with internal clock signal. Table 22 Clocks per Line (Internal Clock Operation) RTNI[4:0] Clocks per Line RTNI[4:0] Clocks per Line 5’h00-5’h0F...
  • Page 54 R61509V Target Spec Frame Frequency Calculation fosc Frame frequency = [Hz] Clocks per line x division ratio x (line + BP + FP) fosc : RC oscillation frequency Line: Number of lines to drive the LCD (NL bits) Division ratio: DIVI Clocks per line: RTNI Rev.
  • Page 55 SDTI SDTI I[2] I[1] I[0] Default NOWI[2:0]: Sets the non-overlap period of adjacent gate outputs. The setting is enabled when the R61509V’s display operation is synchronized with internal clock signals. Table 24 NOWI[2:0] Non-overlap period NOWI[2:0] Non-overlap period *see note...
  • Page 56 R61509V Target Spec Panel Interface Control 3 (R012h) IB15 IB14 IB13 IB12 IB11 IB10 WI[2] WI[1] WI[0] WI[2] WI[1] WI[0] Default value VEQWI[2:0]: Sets VCOM equalize period. The VCOM equalize operation is executed from VCOM alternating point defined by MCPI [2:0] for the period defined by VEQWI [2:0]. This function is disabled when RGB interface is selected.
  • Page 57 R61509V Target Spec SEQWI[2:0]: Sets source equalize period. SEQWI setting is enabled only when the R61509V executes display operation in synchronization with internal clock. Table 27 SEQWI[2:0] Source Equalize Period 3'h0 0 clocks 3'h1 1 clock 3'h2 2 clocks 3'h3...
  • Page 58 R61509V Target Spec Panel Interface Control 4 (R013h) IB15 IB14 IB13 IB12 IB11 IB10 IB9 PI[2] Default MCPI: Defines VCOM alternating timing. This bit is enabled when displaying in synchronization with internal clock. MCP cannot be used in RGB interface operation.
  • Page 59 R61509V Target Spec Panel Interface Control 5 (R014h) IB15 IB14 IB13 IB12 IB11 IB10 Default PCDIVH[2:0], PCDIVL[2:0]: When DM=1 and RGB I/F is selected, display operation is executed using DOTCLKD. PCDIVH and PCDIVL define division ratio of DOTCLK to generate DOTCLKD.
  • Page 60 DOTCLK, the frequency of which is divided by the division ratio set by DIVE[1:0]. This setting is enabled while the R61509V’s display operation is synchronized with RGB interface signals. Table 31 Division Ratio of DOTCLK (RGB interface operation)
  • Page 61 R61509V Target Spec RTNE[5:0]: Sets RTNE in combination with PCDIVH and PCDIVL to decide the number of DOTCLK in 1H (1 line) period according to the following formula. RTNE is enabled when RGB interface is selected. DOTCLKD x RTNE (Number of clock) ≤ DOTCLK in 1H period.
  • Page 62 1 clock = (number of data transfer/pixel) x DIVE (division ratio) x (PCDIVL + PCDIVH) [DOTCLK] SDTE[2:0]: Sets the source output delay period from the reference point when the R61509V’s display operation is synchronized with DOTCLK (DM = 2’h1). For the relationships between signals, see Liquid Crystal Panel Interface Timing.
  • Page 63 R61509V Target Spec Panel Interface Control 8 (R022h) IB15 IB14 IB13 IB12 IB11 IB10 IB9 Default VEQWE[2:0]: Sets low power VCOM drive period. The setting is enabled when RGB interface is selected. Table 35 VEQWE[2:0] Source output delay period VEQWE[2:0]...
  • Page 64 R61509V Target Spec SEQWE[2:0]: Sets source equalize period. SEQWE setting is enabled when the R61509V executes display operation via RGB interface. Table 36 SEQWE[2:0] Source Equalize Period 3'h0 0 clocks 3'h1 1 clock 3'h2 2 clocks 3'h3 3 clocks 3'h4...
  • Page 65 R61509V Target Spec Panel Interface Control 9 (R023h) IB15 IB14 IB13 IB12 IB11 IB10 IB9 Default MCPE [2:0]: Specifies VCOM alternating point. MCPE is enabled when RGB interface is selected. Table 37 MCPE [2:0] VCOM alternating point 3’h0 Setting inhibited 3’h1...
  • Page 66 R61509V Target Spec Frame Marker Control (R090h) IB15 IB14 IB13 IB12 IB11 IB10 Default FMI[2:0]: Sets FMARK output interval by FMI register setting according to the update period of display data and transfer rate. Set FMKM = 1 if FMARK signal is output from FMARK pin. See “FMARK Interface”...
  • Page 67 IB15 IB14 IB13 IB12 IB11 IB10 IB9 Default DSTB: When DSTB = 1, the R61509V enters the shut down mode. In shut down mode, the internal logic power supply is turned off to reduce power consumption. The GRAM data and instruction setting are not maintained when the R61509V is in the shut down mode.
  • Page 68 R61509V Target Spec BT[2:0]: Sets the factor used in the step-up circuits. Select the optimal step-up factor for the operating voltage. To reduce power consumption, set a smaller factor. Table 41 Step-Up Factor for Step-Up Circuits BT[2:0] DDVDH 3’h0 Setting inhibited -(VCI1+DDVDH x 2) 3’h1...
  • Page 69 R61509V Target Spec Power Control 2 (R101h) IB15 IB14 IB13 IB12 IB11 IB10 IB9 Default DC1 [2:0]: Sets step-up clock frequency for Step-up Circuit 2. The step-up clock is in synchronization with internal clock. Table 42 Step-up Frequency (Step-up Circuit 1)
  • Page 70 R61509V Target Spec DC0 [2:0]: Sets step-up clock frequency for Step-up Circuit 1. The step-up clock is in synchronization with internal clock. Table 43 Step-up Frequency (Step-up Circuit 2) Step-up Circuit 1 DC0[2:0] Step-up frequency (fDCDC1) 3’h0 Step-up circuit 1 halts 3’h1...
  • Page 71 R61509V Target Spec VC[2:0]: Sets VCI voltage level. VC[2:0] VCI1 voltage (Reference voltage for step-up operation) 3’h0 Setting inhibited 3’h1 0.94 x VCILVL 3’h2 0.89 x VCILVL 3’h3 Setting inhibited 3’h4 Setting inhibited 3’h5 0.76 x VCILVL 3’h6 Setting inhibited 3’h7...
  • Page 72 ■DC0ｘ Value and DCDC1 Step-up Clock Signal Waveform Example DCDC1 performs charge operation and boost operation with the step-up clock generated from the timing generator. The DCDC1 step-up clock frequency is adjusted by setting the division ratio of the reference clock frequency with DC0x register. (To prevent flickering, the DCDC1 step-up clock signal is synchronized with the reference point of display operation in unit of lines.) Note: Set DC0x and RTNx so that (DCDC1 step-up clock frequency) ≧...
  • Page 73 R61509V Target Spec Power Control3 (R102h) IB15 IB14 IB13 IB12 IB11 IB10 IB9 PSON PON R/W R/W R/W R/W R/W R/W R/W Default Note: True values of PSON and PON are not read when instruction read is executed. PON, PSON: Turn power supply ON. PON and PSON must be written to power supply ON and start the internal power supply operation.
  • Page 74 R61509V Target Spec Power Control 4 (R103h) IB15 IB14 IB13 IB12 IB11 IB10 IB9 Default VDV[4:0]: Selects the factor of VREG1OUT to set the amplitude of VCOM alternating voltage from 0.70 to 1.32. Table 46 VDV[4:0] VCOM amplitude VDV[4:0] VCOM amplitude 5’h0...
  • Page 75 AD[16:0]: Sets a GRAM address in the AC (Address Counter) which is automatically updated according to the combination of AM, ID[1:0] settings as the R61509V writes data to the internal GRAM. Data can be written consecutively without resetting the address in the AC. The address is not automatically updated after reading data from the internal GRAM.
  • Page 76 RAM write data WD[17:0] is transferred via different data bus in different interface operation. interface WD[17:0]: The R61509V develops data into 18 bits internally in write operation. The format to develop data into 18 bits is different in different interface operation.
  • Page 77 When the R61509V reads data from the GRAM to the microcomputer, the first word read immediately after RAM address set is not outputted. Therefore, data on the data bus is invalid. Valid data is sent to the data bus when the R61509V reads out the second and subsequent words.
  • Page 78 R61509V Target Spec NVM Data Read / NVM Data Write (R280h) IB15 IB14 IB13 IB12 IB11 IB10 IB9 280h Default UID[3:0]: Used to temporarily store NVM data such as used identification code. The write data is loaded to NVM data write register (NVDAT [7:0]) and then is written to NVM.
  • Page 79 R61509V Target Spec Table 48 VCM [6:0] VCOMH voltage VCM [6:0] VCOMH voltage 7’h00 VREG1OUT x 0.492 7’h40 VREG1OUT x 0.748 7’h01 VREG1OUT x 0.496 7’h41 VREG1OUT x 0.752 7’h02 VREG1OUT x 0.500 7’h42 VREG1OUT x 0.756 7’h03 VREG1OUT x 0.504 7’h43...
  • Page 80 R61509V Target Spec 7’h38 VREG1OUT x 0.716 7’h78 VREG1OUT x 0.972 7’h39 VREG1OUT x 0.720 7’h79 VREG1OUT x 0.976 7’h3A VREG1OUT x 0.724 7’h7A VREG1OUT x 0.980 7’h3B VREG1OUT x 0.728 7’h7B VREG1OUT x 0.984 7’h3C VREG1OUT x 0.732 7’h7C VREG1OUT x 0.988...
  • Page 81 R61509V Target Spec Window Address Control Window Horizontal RAM Address Start (R210h), Window Horizontal RAM Address End (R211h) Window Vertical RAM Address Start (R212h), Window Vertical RAM Address End (R213h) IB15 IB14 IB13 IB12 IB11 IB10 IB9 Default Default Default...
  • Page 82 R61509V Target Spec γ Control γ Control 1 ~ 14 (R300h to R309h) IB15 IB14 IB13 IB12 IB11 IB10 IB9 PR0P PR0P PR0P 00[4] 00[3] 00[2] Default PR0P PR0P PR0P 02[4] 02[3] 02[2] Default PR0P PR0P 05[3] 05[2] Default PR0P...
  • Page 83 R61509V Target Spec PR0P00[4:0] Adjusts reference level for positive polarity output R0 PR0N00[4:0] Adjusts reference level for negative polarity output R0 PR0P01[4:0] Adjusts reference level for positive polarity output R1 PR0N01[4:0] Adjusts reference level for negative polarity output R1 PR0P02[4:0]...
  • Page 84 NDL setting is enabled in non-lit display area in partial display operation. VLE: Vertical scroll display enable bit. When VLE = 1, the R61509V starts displaying the base image from the line (of the physical display) determined by VL[8:0] bits. VL[8:0] sets the amount of scrolling, which is the number of lines to shift the start line of the display from the first line of the physical display.
  • Page 85 Base image Fixed Scrolling enabled REV: Grayscale level of a image is inverted when REV = 1. This enables the R61509V to display the same image from the same set of data both on normally black and white panels. Table 51...
  • Page 86 R61509V Target Spec Table 53 NL [5:0] Number of drive line NL [5:0] Number of drive line 6’h00 Setting inhibited 6’h1C 232 lines 6’h01 16 lines 6’h1D 240 lines 6’h02 24 lines 6’h1E 248 lines 6’h03 32 lines 6’h1F 256 lines 6’h04...
  • Page 87 R61509V Target Spec Table 54 Gate scan start position SCN[5:0] SM=0 SM=1 GS=0 GS=1 GS=0 GS=1 6’h00 G(N) G(2N-432) 6’h01 G(N+8) G(2N-416) 6’h02 G(N+16) G(2N-400) 6’h03 G(N+24) G(2N-384) 6’h04 G(N+32) G(2N-368) 6’h05 G(N+40) G(2N-352) 6’h06 G(N+49) G(2N-336) 6’h07 G(N+56) G113 G(2N-320) 6’h08...
  • Page 88 R61509V Target Spec Partial Display Control Partial Image 1: Display Position (R500h), RAM Address 1 (Start Line Address) (R501h), RAM Address 1 (End Line Address) (R502h) IB15 IB14 IB13 IB12 IB11 IB10 P [8] P [7] P [6] P [5]...
  • Page 89 R61509V Target Spec Pin Control Test Register (Software Reset) (R600h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 TRSR Default value TRSR: When TRSR = 1, test registers are initialized. When TRSR = 0, initialization of test registers halts.
  • Page 90 R61509V Target Spec NVM Control NVM Access Control 1 (R6F0h), NVM Access Control 2 (R6F1h), NVM Access Control 3 (R6F2h) IB15 IB14 IB13 IB12 IB11 IB10 6F0h Default 6F1h [15] [14] [11] [10] [4]] [2]] [13] [12] Default 6F2h Default EOP [1:0]: Writes data on R280h to NVM or halts the write operation.
  • Page 91 R61509V Target Spec Write “1” to NVDAT[15]. R6F1h Write data to NVM (NVM) Read data from NVM R280h Figure 11 NVVRF: Enables erase verify. This bit is used only in the NVM erase sequence. See “NVM Erase Sequence” for details.
  • Page 92 ●R61509V　Instruction List Rev 0.50 2008. 04. 22 Major category Middle category Minor category Upper Code Lower Code Note Index Command IB15 IB14 IB13 IB12 IB11 IB10 Upper Index Index － Index ID10 ID21 Device Code ALMID1[7] ALMID1[6] ALMID1[5] ALMID1[4] ALMID1[3]...

  • Page 93: Reset Function

    Target Spec Reset Function The R61509V is initialized by the RESETX input. During reset period, the R61509V is in a busy state and instruction from the microcomputer and GRAM access are not accepted. The R61509V’s internal power supply circuit unit is initialized also by the RESETX input. The RESET period must be secured for at least 1ms.
  • Page 94 Target Spec 5 When a RESETX input is entered into the R61509V while it is in shutdown mode, the R61509V starts up the inside logic regulator and makes a transition to the initial state. During this period, the state of the interface pins may become unstable.
  • Page 95 R61509V Target Spec Basic Mode Operation of the R61509V The basic operation modes of the R61509V are shown in the following diagram. When making a transition from one mode to another, refer to instruction setting sequence. Initial setting Display Reset...
  • Page 96 RAM. The R61509V operates in either one of the following four modes according to the state of the display. The operation mode is set in the external display interface control register (R0Ch). When switching from one mode to another, make sure to follow the relevant sequence in setting instruction bits.
  • Page 97 RAM area when it is written and enables the R61509V to display a moving picture and the data in other than the moving picture RAM area simultaneously.
  • Page 98 The internal display operation is synchronized with the frame synchronous signal (VSYNCX) in this mode. This mode enables the R61509V to display a moving picture via system interface by writing data in the internal RAM at faster than the calculated minimum speed via system interface from the falling edge of frame synchronous (VSYNCX).
  • Page 99 Target Spec System Interface The following are the kinds of system interfaces available with the R61509V. The interface operation is selected by setting the IM2/1/0 pins. The system interface is used for instruction setting and RAM access. Table 57 IM Bit Settings and System Interface...

  • Page 100: System 18-Bit Bus Interface

    R61509V Target Spec 80-System 18-bit Bus Interface IM[2:0] = 000 HOST R61509V PROCESSOR (RDX) (RDX) D31-0 DB17-0 Figure 14 18-bit Interface Instruction write Input Instruction Instruction code Device code read / Instruction read Device code Output Instruction code Figure 15 18-bit Interface Data Format (Instruction Write / Device Code Read / Instruction Read)
  • Page 101 R61509V Target Spec 80-System 16-bit Bus Interface IM[2:0] = 010 HOST R61509V PROCESSOR (RD ) (RD ) D15-0 DB17-10, 8-1 Figure 17 16-bit Interface Instruction Input Instruction Instruction code Device code read / Instruction read Device code Output Instruction code Note: Device code cannot be read in 2 transfer mode.
  • Page 102 R61509V Target Spec (EPE=2'h0) RAM data write (1-transfer mode: TRI = 0) Input 1 pixel Note: 65,536 colors are available. RAM data write (2-transfer mode: TRI = 0, DFM = 0) First transfer Second transfer Input pins GRAM write data...
  • Page 103 Target Spec Data Transfer Synchronization in 16-bit Bus Interface Operation The R61509V supports data transfer synchronization function to reset the counters for upper 16-/2-bit and lower 2-/16-bit transfers in 16-bit 2-transfer mode. When a mismatch occurs in upper and lower data transfers due to noise and so on, the 000H instruction is written four times consecutively to reset the upper and lower counters in order to restart the data transfer from upper 2/16 bits.
  • Page 104 R61509V Target Spec 80-System 9-bit Bus Interface When transferring 16-bit instruction, it is divided into upper and lower 8 bits, and the upper 8 bits are transferred first (the LSB is not used). The RAM write data is also divided into upper and lower 9 bits, and the upper 9 bits are transferred first.
  • Page 105 Data Transfer Synchronization in 9-bit Bus Interface Operation The R61509V supports data transfer synchronization function to reset the counters for upper and lower 9- bit transfers in 9-bit bus transfer mode. When a mismatch occurs in upper and lower data transfers due to noise and so on, the 00H instruction is written four times consecutively to reset the upper and lower counters in order to restart the data transfer from upper 9 bits.
  • Page 106 R61509V Target Spec 80-System 8-bit Bus Interface When transferring 16-bit instruction, it is divided into upper and lower 8 bits, and the upper 8 bits are transferred first. The RAM write data is also divided into upper and lower 8 bits, and the upper 8 bits are transferred first.
  • Page 107 R61509V Target Spec RAM data write (2-transfer mode: TRI = 0) Second transfer First transfer Input 1 pixel Note: Normal display in 65,536 colors. RAM data write (3-transfer mode: TRI = 1, DFM = 1) First transfer Second transfer Third transfer...
  • Page 108 Data Transfer Synchronization in 8-bit Bus Interface operation The R61509V supports data transfer synchronization function to reset the counters for upper and lower 8- bit transfers in 8-bit bus transfer mode. When a mismatch occurs in upper and lower data transfers due to noise and so on, the 00H instruction is written four times consecutively to reset the upper and lower counters in order to restart the data transfer from upper 8 bits.
  • Page 109 When writing data to the GRAM via serial interface, the data is written to the GRAM after it is transferred in two bytes. The R61509V writes data to the GRAM in units of 18 bits by adding the same bits as the MSBs to the LSB of R and B dot data.
  • Page 110 R61509V Target Spec Instruction First transfer (upper) Sec on d t ransfer (lower) Input Instruction Instruction code RAM data write First tran sfer (upper) Sec on d t ransfer (lower) Input GRAM write data 1 pixel Note: 65,536-color display in SPI Figure 31 Serial Interface Data Format Rev.
  • Page 111 Lower 8 bits Start Note: Valid data is not sent until the R61509V reads five bytes from the GRAM after start byte input . The R61509V sends valid data when it reads the sixth and subsequent bytes. (d) Instruction read...
  • Page 112 VSYNCX signal. The display data is written in the internal RAM so that the R61509V rewrites the data only within the moving picture area and minimize the number of data transfer required for moving picture display.
  • Page 113 > 240 × 432 / {((14 + 432 - 2) lines × 23 clocks) × 1/726 kHz} = 7.4 MHz Notes: 1. In this example, it is assumed that the R61509V starts writing data in the internal RAM on the falling edge of VSYNCX.

  • Page 114: Notes To Vsync Interface Operation

    R61509V Target Spec VSYNCX write RC oscillation [line] Back porch Display ±7% operation (14 lines) FP = 2H Main panel RAM write Moving picture 7.4 MHz Display display operation (432 lines) [ms] 16.67 Front porch (2 lines) BP = 14H...
  • Page 115 R61509V Target Spec The front porch period continues from the end of one frame period to the next VSYNCX input. The instructions to switch from internal clock operation (DM1-0 = 00) to VSYNC interface operation modes and vice versa are enabled from the next frame period.
  • Page 116 R61509V Target Spec FMARK Interface In the FMARK interface operation, data is written to internal RAM via system interface synchronizing with the frame mark signal (FMARK), realizing tearing less video image while using conventional system interface. FMARK output position is set in units of line using FMP bit. Set the bit considering data transfer speed.
  • Page 117 > 240 × 320 / {((2+14 + 320 – 2) lines × 16 clocks) × 1/726 kHz} = 7.4 MHz Notes: 1. In this example, it is assumed that the R61509V starts writing data in the internal RAM on the rising edge of FMARK.
  • Page 118 The microcomputer detects FMARK signal outputted at the position defined by FMP bit. The R61509V outputs an FMARK pulse when the R61509V is driving the line specified by FMP bits. The FMARK signal can be used as a trigger signal to write display data in synchronization with display operation by detecting the address where data is read out for display operation.
  • Page 119 R61509V Target Spec Table 60 Table 61 FMP[8:0] FMARK output position FMI[2] FMI[1] FMI[0] FMARK Output interval 9’h000 One frame period 9’h001 line 2 frame periods 9’h002 line 4 frame periods 6 frame periods 9’h1BD line Other setting Setting disabled 9’h1BE...

  • Page 120: Fmp Setting Example

    R61509V Target Spec FMP Setting Example FMP=9’h008 NL=6’h35 (432 lines) FMARK output position FP=4’h8 Line address FMP=9’h008 BP=4’h8 0 (1st line) VL=8’h00 1 (2nd line) 2 (3rd line) 3 (4th line) Back porch 4 (5th line) 5 (6th line) RAM physical line address...

  • Page 121: Rgb Interface

    R61509V Target Spec RGB Interface The R61509V supports the RGB interface. The interface format is set by RM[1:0] bits. The internal RAM is accessible via RGB interface. Table 62 RGB interface RGB Interface DB Pin 18-bit RGB interface DB17-0 16-bit RGB interface...
  • Page 122 R61509V Target Spec Polarities of VSYNCX, HSYNCX, ENABLE, and DOTCLK Signals The polarities of VSYNCX, HSYNCX, ENABLE, and DOTCLK signals can be changed by setting the DPL, EPL, HSPL, and VSPL bits, respectively for convenience of system configuration. Valid data period...
  • Page 123 R61509V Target Spec Setting Example of Display Control Clock in RGB Interface Operation Register The display operation via DPI is performed in synchronization with the internal clock (PCLKD) that is generated by dividing PCLK frequency. PCDIVH[3:0]: When PCLKD is High, the number of clocks is set in unit of 1 clock.
  • Page 124 R61509V Target Spec RGB Interface Timing The timing relationship of signals in RGB interface operation is as follows. 16-/18-Bit RGB Interface Timing One frame Back porch period Front porch period VSYNCX HSYNCX DOTCLK ENABLE DB17-0 1H or more VSYNCX 1CLK...

  • Page 125: Ram Access Via System Interface In Rgb Interface Operation

    RAM access via system interface in RGB interface operation The R61509V allows RAM access via system interface in RGB interface operation. In RGB interface operation, data is written to the internal RAM in synchronization with DOTCLK while ENABLE is “Low”.
  • Page 126 R61509V Target Spec 16-Bit RGB Interface The 16-bit RGB interface is selected by setting RIM = 1. The display operation is synchronized with VSYNCX, HSYNCX, and DOTCLK signals. The display data is transferred to the internal RAM in synchronization with the display operation via 16-bit ports while data enable signal (ENABLE) allows RAM access via RGB interface.
  • Page 127 R61509V Target Spec 18-bit RGB Interface The 18-bit RGB interface is selected by setting RIM = 0. The display operation is synchronized with VSYNCX, HSYNCX, and DOTCLK signals. The display data is transferred to the internal RAM in synchronization with the display operation via 18-bit ports (DB17-0) while data enable signal (ENABLE) allows RAM access via RGB interface.

  • Page 128: Notes To Rgb Interface Operation

    R61509V Target Spec Notes to RGB Interface Operation 1. The following functions are not available in RGB interface operation. Table 64 Functions Not Available in RGB Interface operation Function RGB Interface Internal Display Operation Partial display Not available Available Scroll function...
  • Page 129 Target Spec RAM Address and Display Position on the Panel The R61509V has memory to store display data of 240RGB x 432 lines. The R61509V incorporates a circuit to control partial display, which allows switching driving method between full-screen display mode and partial display mode.
  • Page 130 R61509V Target Spec RAM write Base image Panel display Display data Partial image address RAM address position output position RAM address (HSA,HEA) Partial 9’h000 image PTSA0 PTDP Scan PTEA0 direction Base Window image Address (VSA,VEA) 9’h1AF Figure 50 RAM Address, Display Position and Drive Position Restrictions in Setting Display Control Instruction There are restrictions in coordinates setting for display data, display position and partial display.
  • Page 131 Figure 51 Display RAM Address and Panel Display Position Note: This figure shows the relationship between RAM line address and the display position on the panel. In the R61509V’s internal operation, the data is written in the RAM area specified by the window address setting.

  • Page 132: Instruction Setting Example

    R61509V Target Spec Instruction Setting Example The followings are examples of settings for 240(RGB) x 432(lines) panel. Full screen display (no partial display) The following is an example of settings for full screen display. Table 67 Base image display instruction...
  • Page 133 R61509V Target Spec Partial only The following is an example of settings for displaying partial image 1 only and turning off the base image. The partial image 1 is displayed at the position specified by PTDP0 bit. Table 68 Base image display instruction...
  • Page 134 The AM and ID bits set the transition direction of RAM address (either increment or decrement, horizontal or vertical, respectively). Setting these bits enables the R61509V to write data including image data consecutively without taking the data wrap position into account.
  • Page 135 Target Spec Scan Mode Setting The R61509V can set the gate pin assignment and the scan direction in the following 4 different ways by setting SM and GS bits to realize various connections between the R61509V and the LCD panel.
  • Page 136 Target Spec 8-Color Display Mode The R61509V has a function to display in eight colors. In this display mode, only V0 and V63 are used and power supplies to other grayscales (V1 to V62) are turned off to reduce power consumption.
  • Page 137 By changing the DIVI and RTNI settings, the R61509V can operate at high frame frequency when displaying a moving picture, which requires the R61509V to rewrite data in high speed, and it can operate at low frame frequency when displaying a still picture.
  • Page 138 R61509V Target Spec Under the above conditions, the frame frequency can be changed according to the table shown below. Table 69 Frame Frequency Setting (NL = 432 lines, BP = 14 lines, FP = 2 lines, fosc = 678 kHz) RTNI[4:0] DIVI = 2’h0...
  • Page 139 Target Spec Partial Display Function The partial display function allows the R61509V to drive lines selectively to display partial images by setting partial display control registers. The lines not used for displaying partial images are driven at non- lit display level to reduce power consumption.

  • Page 140: Internal Clock Operation

    R61509V Target Spec Liquid Crystal Panel Interface Timing The relationships between RGB interface signals and liquid crystal panel control signals in internal operation and RGB interface operations are as follows. Internal Clock Operation One Frame reference reference reference reference reference...

  • Page 141: Rgb Interface Operation

    R61509V Target Spec RGB Interface Operation One frame VSYNCX HSYNCX DOTCLK ENABLE See note 5DOTCLK Reference Reference point point FMARK (FMP=BP-1) NOWE G432 SDTE S(3n+1) S(3n+2) S(3n+3) n=0 to 239 Third line 432nd line FIrst line Second line VCOM Note: Transfer RGB data in one transfer via 16-bit port Figure 59 Rev.
  • Page 142 Target Spec γ Correction Function γ Correction Function The R61509V supports γ-correction function to make the optimal colors according to the characteristics of the panel. The R61509V has registers for positive and negative polarities. γ Correction Circuit The following figure shows the γ-correction circuit. According to the settings of variable resistors R0 to R8, the voltage level, the difference between VREG1OUT and VGS, is evenly divided into 8 grayscale reference voltages (V0, V1, V8, V20, V43, V55, V62, and V63).
  • Page 143 R61509V Target Spec γ Correction Registers The γ-correction registers include 42 bits for each of R, G, and B dots and 8-bit interpolation adjustment registers. Reference level adjustment registers Table 70 Reference level adjustment registers Gamma Control Resistor Positive Negative...
  • Page 144 R61509V Target Spec Table 71 Reference Level Adjustment Registers and Resistors Register Register Resistor Resistance Resistor Resistance Name Value Name Valie 5'h00 4'h0 5'h01 4'h1 PR0*00[4:0] 5'h02 PR0*05[3:0] 4'h2 5'h1F 4'hF 5'h00 5'h00 5'h01 5'h01 PR0*01[4:0] PR0*06[4:0] 5'h02 5'h02 5'h1F...
  • Page 145 R61509V Target Spec Interpolation Registers Table 72 Interpolation Registers Gamma Control Interpolation Positive Negative adjustment polarity polarity PI0P0[1:0] PI0N0[1:0] V2~V7 PI0P1[1:0] PI0N1[1:0] PI0P2[1:0] PI0N2[1:0] V56~V61 PI0P3[1:0] PI0N3[1:0] Table 73 Interpolation factor for V2 to V7 (See “Grayscale Voltage Calculation Formula” for IPV* level)
  • Page 146 R61509V Target Spec Table 74 Interpolation Factor for V56 to V61 PI0*3[1:0] PI0*2[1:0] IPV56 IPV57 IPV58 IPV59 IPV60 IPV61 2'h0 2'h1 2'h0 2'h2 2'h3 2'h0 2'h1 2'h1 2'h2 2'h3 2'h0 2'h1 2'h2 2'h2 2'h3 2'h0 2'h1 2'h3 2'h2 2'h3 Note: * indicates P/N.
  • Page 147 R61509V Target Spec Table 75 Grayscale Voltage Calculation Formula Grayscale Grayscale Formula Formula voltage voltage ΔV ｘ Σ（R1～R8)/SUMR V43 + (V20 - V43) x 11/23 ΔV ｘ Σ（R2～R8)/SUMR V43 + (V20 - V43) x 10/23 V8 + (V1 - V8) x IPV2...
  • Page 148 R61509V Target Spec Frame Memory Data and the Grayscale Voltage Table 76 Grayscale Voltage Grayscale Voltage Frame memory Frame memory REV = 1 REV = 0 REV = 1 REV = 0 data data Positive Negative Positive Negative Positive Negative...
  • Page 149 R61509V Target Spec Power Supply Generating Circuit The following figures show the configurations of liquid crystal drive voltage generating circuit of the R61509V. Power Supply Circuit Connection Example 1 (VCI1 = VCIOUT) In the following example, the VCI1 level can be adjusted.
  • Page 150 R61509V Target Spec Power Supply Circuit Connection Example 2 (VCI1 = VCI Direct Input) In the following example, the electrical potential VCI is directly applied to VCI1. In this case, the VCIOUT level cannot be adjusted internally but step-up operation becomes more effective. Make sure that VCI≤...
  • Page 151 R61509V Target Spec Specifications of Power-supply Circuit External Elements The specifications of external elements connected to the power-supply circuit of the R61509V are as follows. Table 77 Capacitor Capacitance Voltage proof Pin Connection (1) VREG1OUT, (3) VCI1, (4) C11P, C11M, (5) C12P, C12M, (7) C13P, C13M, (14) VCL, (16) VCOMH, (17) VCOML 1µF...
  • Page 152 R61509V Target Spec Voltage Setting Pattern Diagram The following are the diagrams of voltage generation in the R61509V and the TFT display application voltage waveforms and electrical potential relationship. Internal reference voltage (VCIR) VCILVL(2.5~3.3V) DDVDH VREG1OUT VCC(2.5~3.3V) VREG1OUT VCM/VCOMR IOVCC(1.65~3.3V)
  • Page 153 R61509V Target Spec Liquid Crystal Application Voltage Waveform and Electrical Potential VREG1OUT VCOMH VCOM VCOML Sn (source driver output) Gn (panel interface output) Figure 64 Rev. 0.11 April 25, 2008, page 153 of 181...
  • Page 154 When adjusting the VCOMH voltage by setting VCM[6:0] (R280h, internal VCOMH level adjustment circuit), follow the sequence below. The R61509V can retain permanently the VREG1OUT and VCOMH level adjustment setting values in NVM. To write data to NVM, see “NVM Control” and NVM Write Sequence”.
  • Page 155 R61509V Target Spec NVM Control The R61509V incorporates 16-bit NVM for user’s use. • 7 bits are for VCOM adjustment (VCM register value is stored). • 8 bits are for UID. • 1 bit is for a dummy bit. To write, read and erase data from/to the NVM, follow the sequences below. Data on the NVM is loaded to internal registers automatically when the sequences are performed.
  • Page 156 R61509V Target Spec NVM Load (Register Resetting) Sequence Data on the NVM is loaded either automatically or by setting a command. During the following sequence, the data written to the NVM is automatically loaded to the internal register. Except for the shutdown mode TE = 1’b0...
  • Page 157 R61509V Target Spec NVM Write Sequence Defined 16 bit data is written to the selected address. When “0” is written to these bits, the bits are set to “0”. If the data is erased from the bit, the bit is returned to ”1”. The bit to which data is not written should be set to “1”.
  • Page 158 R61509V Target Spec NVM Erase Sequence The data written to the selected 16 bits is erased all together. The bits from which data is erased are set to “1”. To erase data from NVM, make sure VGL < VPP3A, and follow the sequence below after power supply ON sequence.
  • Page 159 Notes: 1. Set VCMR to 1 when using internal electric volume. 2. When NVM is in the status that the R61509V is shipped out, set the instruction register (R280h: VCM[6:0], and UID[7:0]). If writing values to VCM[6:0] and UID[7:0] has been completed, setting this instruction register is unnecessary.
  • Page 160 R61509V Target Spec Power Supply OFF Sequence (B) Liquid crystal power supply ON (DCDC ON) state Display OFF state R102h: PON=0 PSON=0 5 frames or more (A) Liquid crystal power supply OFF (DCDC OFF) Display OFF state Power supply (VCC, VCI, IOVCC) OFF IOVCC VCI →...
  • Page 161 Note Internal operation of the R61509V is unstable until VCC rises. If IOVCC rose before VCC rises, the R61509V may be in “output” status. In this case, do not send or receive any data before power supply is completed. Changing order of voltage input will not cause troubles such as latchup or destruction of the LSI.
  • Page 162 Instruction Setting Sequence and Refresh Sequence Display ON/OFF Sequences and Refresh Sequence In setting instruction in the R61509V, follow the sequences below. To reduce malfunction caused by noise, execute refresh sequence 1 regularly. To exit shutdown mode, execute refresh sequence 2.

  • Page 163: Shutdown Mode Sequences

    R61509V Target Spec Shutdown Mode Sequences Shutdown Sequence (Exit shutdown mode by inputting CSX = “Low”) 18-/16-/9-/8-bit interface operation Display OFF sequence Set shutdown mode Set shutdown mode R100h: DSTB=1 CSX=”Low” (1) CSX=”Low” (2) VDD startup, Oscillation startup period Exit shutdown mode or more Input CSX = “Low”...
  • Page 164 R61509V Target Spec Shutdown Sequence (Exit shutdown mode by inputting CSX = “Low” and WRX = “Low” (Index Write)) (1) 18-/16-bit interface operation Display OFF sequence Set shutdown mode Set shutdown mode R100h: DSTB=1 Index Write (Data=16’h0000) Index Write (Data=16’h0000)
  • Page 165 R61509V Target Spec (2) 9-/8-bit interface operation Display OFF sequence Set shutdown mode Set shutdown mode R100h: DSTB=1 Index Write (Data=8’h00) Index Write (Data=8’h00) VDD startup, Oscillation startup period Exit shutdown mode or more Index Write (Data=8’h00) Initialize the Index Write (Data=8’h00) R61509V.

  • Page 166: Color Mode Setting

    R61509V Target Spec 8-Color Mode Setting 262,144 color to 8 color mode 8 color to 262,144 color mode 262,144-color mode 8-color mode display display R00Bh: COL=0 R00Bh: COL=1 262,144-color mode display 8-color mode display Figure 75 Partial Display Setting Partial Display Setting Sequence...

  • Page 167: Absolute Maximum Ratings

    R61509V Target Spec Absolute Maximum Ratings Table 82 Items Symbol Unit Value Note Power supply voltage 1 VCC, IOVCC -0.3 ~ +4.6 1, 2 Power supply voltage 2 VCI – AGND -0.3 ~ +4.6 1, 3 Power supply voltage 3 DDVDH –...

  • Page 168: Electrical Characteristics

    R61509V Target Spec Electrical Characteristics DC Characteristics (VCC= 2.50V~3.30V, VCI=2.50V~3.30V, IOVCC=1.65V~3.30V, Ta= -40°C~+85°C * See note 1 Table 83 Items Symbol Unit Test condition Min. Typ. Max. Notes 0.80× Input high-level voltage IOVCC 2, 3 IOVCC=1.65V～3.30V － IOVCC 0.20× Input low-level voltage -0.3...
  • Page 169 R61509V Target Spec IOVCC=1.8V, VCC=VCI=2.8V, 64-line partial, fFLM=40Hz, Ta=25℃, Frame memory data: 18’h00000, REV=0, BC0=0, FP[7:0]=8’h8, BP[7:0]=8’h8, VC[2:0]=3’h1, BT[2:0]=3’h2, VRH[4:0]=5’h18, VCM[6:0]=7’h7F, VDV[4:0]=5’h11, AP[1:0]=2’h3, DC0[2:0]=3’h3, DC1[2:0]=3’h4, PR*P00=PR*N00=5’h00, LCD power supply current (VCI-GND) PR*P01=PR*N01=5’h02, 8-color, 64-line partial display Ici2 5, 6 PR*P02=PR*N02=5’h04, －...

  • Page 170: Step-Up Circuit Characteristics

    R61509V Target Spec Step-up Circuit Characteristics Table 84 Item Unit Test condition Min. Typ. Max. Note Step-up IOVCC=VCC=VCI=2.80[V], fosc=678[kHz], Ta=25℃, VC=3’h1, AP=3’h3, BT=3’h2, DC0=3’h4 (div. 1/8), output DC1=3’h2 (div. 1/4), COL=0, D=2’h0, DDVDH voltage C11=C12=C13=C21=C22=1[uF]/B characteristics, DDVDH=VGH=VGL=VCL=1[uF]/B characteristics, Iload1=-3 [mA], No load on the panel.
  • Page 171 R61509V Target Spec Power Supply Voltage Range (Ta= -40°C~+85°C, GND=AGND=0V) Table 86 Item Symbol Unit Min. Typ. Max. Condition Power Supply Voltage IOVCC 1.65 1.80/2.80 3.30 Power Supply Voltage 2.50 2.80 3.30 Power Supply Voltage 2.50 2.80 3.30 Write Power Supply Voltage...
  • Page 172 R61509V Target Spec AC Characteristics (VCC= 2.50V~3.30V, IOVCC=1.65V~3.30V, Ta= -40°C~+85°C * See note 1 Clock Characteristics Table 88 Item Symbol Unit Test condition Min. Typ. Max. Note Oscillation clock VCC=IOVCC=3.0V 80-system 18-/16-/9-/8-bit Bus interface Timing Characteristics (1-/2-/3-transfer, IOVCC=1.65V~3.30V) TBD Table 89...
  • Page 173 R61509V Target Spec Clock Synchronous Serial Interface Timing Characteristics (IOVCC=1.65V~3.30V) TBD Table 90 Item Symbol Unit Test condition Min. Typ. Max. Serial clock cycle Write (receive) Figure B 20,000 － SCYC (TBD) time Read (transmit) Figure B 20,000 － SCYC...
  • Page 174 R61509V Target Spec LCD Driver Output Characteristics Table 92 Item Symbol Unit Test condition Min. Typ. Max. Note VCC=IOVCC =2.80V, VC[2:0]=3’h7 VRH[4:0]=5’h1F, fosc=678kHz (432-line drive), Ta=25°C, PR*P00=PR*N00=5’h00, PR*P01=PR*N01=5’h02, PR*P02=PR*N02=5’h04, PR*P03=PR*N03=4’h8, PR*P04=PR*N04=4’hF, PR*P05=PR*N05=4’h8, Source driver PR*P06=PR*N06=5’h04, tdds µs － － (TBD) output delay time PR*P07=PR*N07=5’h02,...
  • Page 175 R61509V Target Spec Notes to Electrical Characteristics Note 1. The DC/AC electrical characteristics of bare die and wafer products are guaranteed at 85℃. Note 2. The following figures illustrate the configurations of input, I/O, and output pins. Pins: FMARK, SDO...
  • Page 176 R61509V Target Spec Note 3: Test 1, 2 and 3 pins must be grounded. The VDDTEST and VREFC must be fixed to AGND. The IM0_ID pin must be fixed to IOVCC or be grounded. Note 4: This excludes the current in the output drive MOS.
  • Page 177 R61509V Target Spec Timing Characteristics 80-system Bus Interface Note 1 PWLW PWLR PWHW PWHR tWRr tWRf tCYCW tCYCR tDSW Note 2 Write Data DB17-0 tDDR tDHR Note 2 DB17-0 Read Data Note 1: PWLW and PWLR are defined by the overlap period when CSX is "Low" and either of WRX or RDX is "Low".
  • Page 178 R61509V Target Spec Clock Synchronous Serial Interface Start: S End: P tSCYC tscr tscf tCSU tSCH tSCL tSISU tSISH Input Data Input Data tSOD tSOH VOH1 VOH1 Output Data Output Data VOL1 VOL1 Figure B Clock Synchronous Serial Interface Timing...
  • Page 179 R61509V Target Spec RGB Interface trgbf trgbr tSYNCS VSYNCX HSYNCX tENS tENH ENABLE trgbf trgbr PWDL PWDH DOTCLK tCYCD tPDS tPDH DB17-0 Write Data Figure D RGB Interface Timing LCD Driver and VCOM Output Characteristics tDDv Target voltage 35mV VCOM...
  • Page 180 (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officiers, directors, and employees against any and all damages...

  • Page 181: Revision Record

    R61509V Target Spec Revision Record Rev. Date Page No. Contents of Modification Drawn Approved by 0.11 2008/04/25 First issue Rev. 0.11 April 25, 2008, page 181 of 181...

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