Tektronix 7B10 Instruction Manual page 31

Theory
of
Operation
-7B10
TRIGGER
MODE
SWITCHING
Integrated
circuit
U220
controls the
NORM,
AUTO,
and
SINGLE
SWP MODE
and
also
generates
control signals
used
in
the
10.
HE
SYNC
operation
is
described
in
the
Trigger
Generator
circuit
description
(diagram
2).
Normal
Mode
The
NORM MODE
is
provided
when
U220-pin 12
is
LO.
In
the
NORM
MODE,
only
an
appropriate trigger signal
can
initiate
a
sweep
gate
to
the
Ramp
Generator
(diagram
4).
Integrated
circuit
U220
controls
sweep
lockout
and
hold
off
functions.
Auto
Mode
An
internal control stage (within
U220) produces
a free-
running reference
trace (bright
base
line) in
the
absence
of
a trigger signal.
The HF
SYNC mode
defaults
logic to
the auto
mode.
A
HI level
from
MODE
switch
S230
is
inverted by
Q230
to
U220-pin 19
LO,
which
selects
AUTO
MODE
operation
In
the presence
of a trigger
pulse from the
Trigger
Generator (diagram
2),
a HI level at
U220-pin
1
discharges an
internal control stage
which
inhibits
the
auto sense
signal
from U220-pin
3.
In
the
absence
of a
trigger pulse,
the
LO
level at
U220-pin
1
enables
this
internal control
stage with
a
time delay generated by
R228, C228, and
other
circuitry internal to
U220-pin
2.
After
the time
delay,
an auto
sense
signal
is
initiated
from U220-pin 3
to
the Trigger
Generator (diagram
2).
Single
Sweep Mode
The
SINGLE
SWP MODE
provides display
of
only
one
sweep. After
one
sweep
has
run,
all
other
sweeps
are
inhibited
until
the
SINGLE
SWP-RESET
push
button
is
pressed.
The
READY
light
indicates
when
the
sweep
is
ready
to
accept a trigger.
After
completion
of
one
sweep,
the hold
off start
pulse
at
U220-pin 16 causes
the
sweep
disable out
at
pin
17
to
rise HI.
A
HI level at
U220-pin 12
initiates
single-sweep
operation
and
holds the
sweep
disable out
at
U220-pin
17 HI after
completion
of
the
sweep.
Momentary
contact
of
the
RESET
push
button places
a
LO
at
U220-pins 14
and
15,
which removes
the
sweep
disable out
from
pin
17 and allows the
Ramp
Generator (diagram
4) to
accept
a trigger. Interface
connector
B15
provides
a
remote
single-sweep
reset input
from compatible mainframes.
HOLD
OFF TIMING
The
hold
off
stages prevent the
Ramp
Generator (diagram
4)
from
being retriggered
until
the
sweep
timing
capacitors are discharged.
At the
end
of
each sawtooth
waveform from
the
Ramp
Generator (diagram
4),
a
sweep
stop
comparator
pulse
(HI)
is
coupled
to
U220-pin
16.
This pulse enables the
hold
off
timing
circuits
at
U220-pin
8,
which
sets
the
sweep
disable out
at
U220-pin 17
HI
and
the hold
off
signal
at
pin
10
LO
for
the duration
of
the hold
off cycle.
Hold
off
timing (U220-pin
8)
is
provided by capacitors
C212
through
R215
and
resistors
R212
through R14.
Transistors
0203
and
0204
prevent the
sweep
disable
out pulse
at
U220-pin 17 from
falling
LO
until
the holdoff
timing capacitors have
discharged. Transistors
0210
and
0214
and
front-panel
HOLD
OFF
control
R210
provide
variable current
to
the timing
components
to
change
the
hold
off
time
period.
LOCKOUT
BUFFER
AMPLIFIER
A
lockout
pulse
(HI)
may
be
initiated at
interface
connector
pin
B8
by
mainframe
switching functions
A
HI
level,
coupled from
interface
connector
B8
through
the
Lockout Buffer Amplifier (0201, 0202, and 0206)
to
the
lockout input
at
U220-pin
18, initiates a
sweep
disable
pulse
at
U220-pin 17 thereby
disabling the
sweep. The
lockout pulse
(HI)
is
also applied
through
Q358
(diagram
4) to
the hold
off
start
input
at
U220-pin
1
6
to
enable the
hold
off
cycle.
HOLD
OFF
OUTPUT
AMPLIFIER
The
Hold
Off
Output
Amplifier inverts
and
amplifies the
hold
off
signal
from
U220-pin 10
for
use
by the
mainframe.
Transistor
0272
inverts the hold
off signal
from
U220-
pin
10
to
provide
a
HI
level
when
hold
off
is
present.
The
inverted signal
is
coupled through
emitter follower
0274
to
interface
connector
B4.
SWEEP GENERATOR
The
Sweep
Generator produces
a linear
ramp waveform
for
the
mainframe
when
gated by the Trigger Generator
A
sweep
gate (unblanking)
is
also
generated
in this
circuit
block
The
linear
sweep ramp waveform
is
produced by
charging
a
capacitor
from
a
constant current source The
slope
of
the
ramp determines
the
sweep
rate of the
displayed
trace
TIMING
CURRENT SOURCE
The
Timing Current Source
stages generate
a
constant
current
for
the
Ramp
Generator
stages.
A
reference
voltage source
is
established by the <^50 volt supply
and
R306, R305, R304, and
R300
(front-panel
SWP
CAL
adjustment)
The
reference voltage
is
applied
to
operational amplifier
U314 which
provides
unity voltage
gain
and low
output
impedance.
The
output
of
U314
is
connected through
Q322
and
Q324
to
the timing
resistors
(R392
through
R399 and
R328).
Timing
current
is
the
result of the
voltage drop across the timing
resistors
and
flows
through
the collector
of
Q324
to
the
Ramp
Generator
stages.
3-8