Tektronix 7B10 Instruction Manual page 29

Theory
of
Operation
-7B10
FRONT-PANEL WIRING
The
Front-Panel Wiring diagram
shows
the
interconnections
between
front-panel functions
(controls,
connectors,
and
indicators)
and
circuit
boards within
this
instrument
<§>
TRIGGER
GENERATOR
The
Trigger
Generator
provides
a stable display by
starting
the
Sweep
Generator (diagram
4) at
a selected
point
on
the input
waveform. The
triggering point
can be
varied by the
LEVEL
control
and
may
be on
either the
positive or
negative slope
of
the
waveform. The
triggering
signal source
may
be from
either
the
signal
being
displayed
(INT),
a signal
from an
external
source
(EXT), or
a
sample
of
the power-line voltage
(LINE).
EXTERNAL TRIGGER
AMPLIFIER
The
external trigger signal
is
connected
to
the Trigger
Generator through
EXT
TRIG
IN
connector J90. Push-
button switch
S90
selects either
1
MQ
or
50
O
input
impedance The 0
2
amp
fuse protects the 50
fJ
load
from
signal overload.
Pushing
in
the
EXT
push button
of
SOURCE
switch (S50)
allows external
trigger
signals
to
pass from the External
Trigger Amplifier
to
U124
for amplification. Field-effect
transistor
Q98
conducts
in
the
DC COUPLING mode
only
and
0108
is
on
in
all
coupling
modes
except
AC
LF REJ.
Components
U110, 0114, and
0118
compose
an
operational amplifier
whose
gain
is
approximately
1/4
determined
by feedback
resistors
R93
and R74.
Integrated
circuit
U110
provides dc
stability
Diodes
CR74, CR76, and
CR77
protect the trigger amplifier from
possible overload caused by high amplitude external
signals
A
portion
of
the dc leveling voltage from
R67
is
applied
to
U1 10
to
provide
additional
level
range
in
the
EXr
triggering
mode. Pressing the INT button
causes
Q118
to
saturate
which
interrupts signal flow
to
the
external amplifier
of
U124
When
the
AC
HF REJ
button
is
pressed, signals
in
the
frequency range
of 5
Hz
to
30
kHz pass from
U64A
to
U64B
and then
to
U1 24's Level
Input. Also, U1 24's
Ext In
amplifier
is
disabled
and U124's
low-frequency
amplifier
IS
enabled, allowing only
filtered
signals
from
U64B
to
be
amplified.
TRIGGER
AMPLIFIER
AND
SOURCE
SELECTOR
The
time base
trigger
source
is
selected by the
SOURCE
switch (S50)
which
enables
the appropriate amplifier
in
U124
A
dc voltage from
the
LEVEL
control
is
applied
to
pins 6
and
8
of
U1 24
to
provide
internal amplifier voltage
offset.
The
amplifiers'
outputs are
summed
and
applied to
pins
14 and 16
to
drive
the following Trigger
Generator
stage
The
internal trigger signal
from the
trigger
source
selector
of
the
mainframe
is
connected
to
U12
via
interface
connector pins
A20
and
B20. Integrated
circuit
U12
provides
common
mode
rejection
for
frequencies up
to
100
kHz; T1
provides
cmr above 100
kHz. Ac-coupled
trigger
signals enter
U124
at
pin 3
and are terminated
in
50
Q
at
pin
4.
Integrated
circuit
U38
provides
a
path
for
low-frequency trigger signals
which
are fed
to pin
5
of
U64B. These
signals
then
arrive
at
the
level port of
U124
(pin 6)
where
they are
summed
with
the high-frequency
signals
to
provide
wide-band
triggering
in
the
AC
and
DC
COUPLING
modes
Pressing the
front-panel
AC
LF
REJ
push
button breaks the
low-frequency
signal path
allowing only high-frequency
trigger signals
to
appear
at
the output
of
U124.
When
the
AC
HF REJ
push
button
is
pressed, the internal signal amplifier
is
disabled
and
the
low-frequency
amplifier
is
enabled allowing only low-
frequency
signals
to
pass.
In
the
HF
SYNC
mode, the output
of
U138A
drives the
level
input
of
U124.
A
voltage
appears
at
the output
of
U138A when
a
voltage difference
is
detected
at
its
input.
Thus,
when
an unbalanced
trigger condition occurs,
U138A
provides
automatic dc
leveling of
U124
so
that
U144
will
always have
a
balanced
signal input
in
the
HF
SYNC mode
Transistor
Q142
is
turned
off in
the
HF
SYNC
mode
providing
a
path through
CR145
for
voltage
from
the
LEVEL
control.
This enables
the
LEVEL
control
to
adjust the hysteresis
of
Trigger
Generator
U144
to
almost
zero,
causing very small signals
to trigger
U144
SLOPE SELECTOR
AND
TRIGGER
GENERATOR
Integrated circuit
U144
converts the
differential trigger
signal
from the Trigger Amplifier
and Source
Selector
block
to a differential
gate
waveform
for
use
by the
Gate
Generator
stage.
SLOPE
switch SI
40
is
connected
to
U1 44-pin
3
to
determine
whether
the display
is
triggered
on
the
positive going
or
negative-going
slope.
When
the
SLOPE
switch
is
set to
+,
a
positive-going signal
on
pin 5
produces
a
positive-going gate on
pin
15
and
a negative-
going gate
on
pin
16
When
the
SLOPE
switch
is
set to -
a negative-going signal
on
pm
5
produces
a positive-
going gate
on
pin
15
and
a
negative-going gate on
pin
16 Trigger Generator
sensitivity
is
controlled
by
R147.
The delay
mode
control input
at
U1 44-pin 4
provides
control
when
the
unit
is
operating as
a
delayed
sweep
unit
in
the B
horizontal
compartment
of a
mainframe
with
2
horizontal
compartments.
When
the
unit
is
operating
in
the
independent
or triggerable after
delay
time
modes
(as
determined
by the delaying
sweep
time-
base
unit
in
the
A
horizontal
compartment), there
is
no
effect
on the Trigger
Generator
circuits.
However,
when
the
unit
is
operating
in
the
B
starts after
delay time
mode, U1
44-pin
4
is
HI,
causing the
trigger
disable signal
at
pin
2
to initiate a trigger
gate pulse
at
U1 44-pins 15
and
16.
3-6