Gigabyte GA-8N-SLI Quad Royal User Manual page 102

Intel pentium processor extreme edition, intel pentium d / pentium 4 lga775 processor motherboard
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POST (hex)
1Dh
1Fh
21h
23h
25h
26h
27h
29h
2Bh
2Dh
33h
3Ch
3Eh
40h
43h
47h
49h
4Eh
GA-8N-SLI QUAD Royal Motherboard
Initial EARLY_PM_INIT switch.
Load keyboard matrix (notebook platform)
HPM initialization (notebook platform)
1. Check validity of RTC value:
e.g. a value of 5Ah is an invalid value for RTC minute.
2. Load CMOS settings into BIOS stack. If CMOS checksum fails,
use default value instead.
3. Prepare BIOS resource map for PCI & PnP use. If ESCD is
valid, take into consideration of the ESCD¡¦s legacy information.
4. Onboard clock generator initialization. Disable respective clock
resource to empty PCI & DIMM slots.
5.Early PCI initialization:
-Enumerate PCI bus number
-Assign memory & I/O resource
-Search for a valid VGA device & VGA BIOS, and put it
into C000:0.
PCI Bus Initialization
Init clock Generator
Initialize INT 09 buffer
1. Program CPU internal MTRR (P6 & PII) for 0-640K memory address.
2. Initialize the APIC for Pentium class CPU.
3. Program early chipset according to CMOS setup. Example: onboard IDE
controller.
4. Measure CPU speed
Invoke video BIOS.
1. Initialize multi-language
2. Put information on screen display, including Award title, CPU type,
CPU speed ......
Reset keyboard except Winbond 977 series Super I/O chips.
Test 8254
Test 8259 interrupt mask bits for channel 1.
Test 8259 interrupt mask bits for channel 2.
Test 8259 functionality.
Initialize EISA slot
1. Calculate total memory by testing the last double word of each 64K page.
2. Program write allocation for AMD K5 CPU 64K page.
1. Program MTRR of M1 CPU
2. Initialize L2 cache for P6 class CPU & program CPU with proper
cacheable range.
3. Initialize the APIC for P6 class CPU.
4. On MP platform, adjust the cacheable range to smaller one in case the
cacheable ranges between each CPU are not identical.
- 102 -
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