Cqm1 Interrupt Functions; Types Of Interrupts - Omron CPM1 Programming Manual

CQM1 Interrupt Functions

1-5

CQM1 Interrupt Functions

1-5-1

Types of Interrupts

Interrupt Processing
1,2,3...
Pulse Output Instructions
and Interrupts
38
This section explains the settings and methods for using the CQM1 interrupt
functions.
The CQM1 has three types of interrupt processing, as outlined below.
Input interrupts:
Interrupt processing is executed when an input from an external source turns
ON one of CPU bits 00000 to 00003.
Interval timer interrupts:
Interrupt processing is executed by an interval timer with a precision of
0.1 ms.
High-speed counter interrupts:
Interrupt processing is executed according to the present value (PV) of a built-
in high-speed counter. All CQM1 CPU Units are equipped with high-speed
counter 0, which counts pulse inputs to one of CPU bits 00004 to 00006. Two-
phase pulses up to 2.5 kHz can be counted.
The CQM1-CPU43/44-EV1 CPU Units can also count inputs to ports 1 and 2:
CQM1-CPU 43-EV1: High-speed counters 1 and 2 count high-speed pulse
inputs to ports 1 and 2. Two-phase pulses up to 25 kHz can be counted.
CQM1-CPU44-EV1: High-speed counters 1 and 2 count absolute rotary
encoder codes input to ports 1 and 2.
When an interrupt is generated, the specified interrupt processing routine is
executed. Interrupts have the following priority ranking. (Input interrupt 0 has
the highest priority and high-speed counter interrupt 0 has the lowest.)
1. Input interrupt 0 > Input interrupt 1 > Input interrupt 2 > Input interrupt 3
2. High-speed counter interrupt 1 > High-speed counter interrupt 2
3. Interval timer interrupt 0 > Interval timer interrupt 1 > Interval timer interrupt
2 (Interval timer interrupt 2 is high-speed counter interrupt 0.)
When an interrupt with a higher priority is received during interrupt process-
ing, the current processes will be stopped and the newly received interrupt will
be processed instead. After that routine has been completely executed, then
processing of the previous interrupt will be resumed.
When an interrupt with a lower or equal priority is received during interrupt
processing, then the newly received interrupt will be processed as soon as the
routine currently being processed has been completely executed.
Just as with ordinary subroutines, interrupt processing routines are defined
using SBN(92) and RET(93) at the end of the main program.
When interrupt processing routines are executed, a specified range of input
bits can be refreshed.
When an interrupt processing routine is defined, a "no SBS error" will be gen-
erated during the program check but execution will proceed normally. If this
error occurs, check all normal subroutines to be sure that SBS(91) has been
programmed before proceeding.
With the CQM1-CPU43/44-EV1 CPU Units, the following instructions cannot
be executed in an interrupt subroutine when an instruction that controls pulse
I/O or high-speed counters is being executed in the main program: (25503
turns ON)
Section 1-5