Supermicro X12DPD-A6M25 User Manual
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Supermicro X12DPD-A6M25 User Manual

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X12DPD-A6M25
USER'S MANUAL
Revision 1.00

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Summary of Contents for Supermicro X12DPD-A6M25

  • Page 1 X12DPD-A6M25 USER'S MANUAL Revision 1.00...
  • Page 2 State of California, USA. The State of California, County of Santa Clara shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for all claims will not exceed the price paid for the hardware product.
  • Page 3 Preface About This Manual This manual is written for system integrators, IT technicians, and knowledgeable end users. It provides information for the installation and use of the X12DPD-A6M25 motherboard. About This Motherboard The Supermicro motherboard X12DPD-A6M25 supports the Intel Xeon Scalable Family 3rd ®...
  • Page 4 Super X12DPD-A6M25 User's Manual Contacting Supermicro Headquarters Address: Super Micro Computer, Inc. 980 Rock Ave. San Jose, CA 95131 U.S.A. Tel: +1 (408) 503-8000 Fax: +1 (408) 503-8008 Email: marketing@supermicro.com (General Information) support@supermicro.com (Technical Support) Website: www.supermicro.com Europe Address: Super Micro Computer B.V.

  • Page 5: Table Of Contents

    Preface Table of Contents Chapter 1 Introduction 1.1 Important Links ........................7 1.2 Processor and Chipset Overview ..................16 1.3 Special Features ........................17 1.4 System Health Monitoring ....................17 1.5 ACPI Features ........................18 1.6 Power Supply ........................18 1.7 Serial Port ...........................18 ® 1.8 Intel Optane™...
  • Page 6 4.5 BMC ..........................164 4.6 Security ..........................167 4.7 Boot ..........................171 4.8 Save & Exit ........................173 Appendix A BIOS POST Codes A.1 BIOS POST Codes ......................175 Appendix B Software B.1 Microsoft Windows OS Installation ...................176 B.2 Driver Installation ......................178 B.3 SuperDoctor 5 .........................179 ®...

  • Page 7: Introduction

    Chapter 1 Introduction Congratulations on purchasing your computer motherboard from an industry leader. Supermicro motherboards are designed to provide you with the highest standards in quality and performance. 1.1 Important Links For your system to work properly, please follow the links below to download all necessary drivers/utilities and the user’s manual for your computer.
  • Page 8 Super X12DPD-A6M25 User's Manual Figure 1-1. X12DPD-A6M25 Motherboard Image Note: All graphics shown in this manual were based upon the latest PCB revision available at the time of publication of the manual. The motherboard you received may or may not look exactly the same as the graphics shown in this manual.
  • Page 9 Chapter 1: Introduction Figure 1-2. X12DPD-A6M25 Motherboard Layout (not drawn to scale) COM1 JUSB2 PRESS FIT PRESS FIT JSFP1 JSFP0 JVGA1 JUIB1 JRK1 BMC_LAN JUSB1 JPL1 JDBG JPFR1 JLAN2 JM21 JM22 JP_MX1 LEDBMC M.2-H SLOT1 M.2-H SLOT2 JLAN1 LAN2 JLAN0...
  • Page 10 Super X12DPD-A6M25 User's Manual LED_L0 M.2 SLOT1 JP_MX1 M.2 SLOT2 JPL1 LED_L1 JSFP1 JUSB1 JSFP0 JLAN2 JVGA1 JRK1 JUIDB1 COM1 COM1 JUSB2 JUSB2 PRESS FIT PRESS FIT JSFP1 JSFP0 JVGA1 JUIB1 JPFR1 LEDM1 JRK1 BMC_LAN JUSB1 JPL1 JDBG JPFR1 JLAN2...
  • Page 11 Onboard 25G LAN SFP+ JLAN2 Dedicated BMC LAN port Chassis Intrusion header Note: For detailed instructions on how to configure VROC RAID settings, please refer to the VROC RAID Configuration User's Guide posted on the web page under the link: http://www.supermicro.com/manuals/.
  • Page 12 Super X12DPD-A6M25 User's Manual PCIe 4.0 x8 SlimSAS ports with support of 12 NVMe connections on six ports JNVME1~JNVME6 (JNVME1~JNVME6) JPI2C1(JPI²C1) Power System Management Bus (SMB) I²C header JPWR1 14-pin main power connector JPWR2, JPWR3 8-pin 12V DC power connectors...
  • Page 13 Note: Intel Optane PMem 200 Series is supported by the 3rd Gen Intel Xeon Scalable Processors (83xx/63xx/53xx/4314) only DIMM Size • Up to 256GB at 1.2V per slot Note: For the latest CPU/memory updates, please refer to our website at http://www.supermicro.com/products/ motherboard. Chipset • Intel PCH C621A (LBG-R) Expansion Slots •...
  • Page 14 Note 1: The CPU maximum thermal design power (TDP) is subject to chassis and heatsink cooling restrictions. For proper thermal management, please check the chas- sis and heatsink specifications. Note 2: For BMC configuration instructions, please refer to the Embedded BMC Con- figuration User's Guide available at http://www.supermicro.com/support/manuals/.
  • Page 15 Chapter 1: Introduction Figure 1-3. System Block Diagram DIMMB1 DIMMB1 DIMMA1 DIMMA1 DIMMD1 DIMMD1 DIMMC1 10.4/11.2G DIMMC1 DIMMF1 IMC0/1 IMC0/1 DIMMF1 DIMME1 DIMME1 DIMMH1 DIMMH1 CPU1 CPU2 DIMMG1 DIMMG1 IMC2/3 IMC2/3 DMI3 DMI3 PCIe X16 PCIe X8 SlimSAS PCIe X16 PCIe X16 NVMe4 x8 NVMe6 x8...

  • Page 16: Processor And Chipset Overview

    1.2 Processor and Chipset Overview Built upon the functionality and capability of the 3rd Gen Intel Xeon Scalable Processors (Socket P) and the Intel C621A chipset, the X12DPD-A6M25 motherboard provides system performance, energy efficiency, and feature sets optimized for high-performance computing, artificial intelligence (AI), deep learning (DL), big data, and enterprise applications.

  • Page 17: Special Features

    Chapter 1: Introduction 1.3 Special Features Recovery from AC Power Loss The Basic I/O System (BIOS) provides a setting that determines how the system will respond when AC power is lost and then restored to the system. You can choose for the system to remain powered off (in which case you must press the power switch to turn it back on), or for it to automatically return to the power-on state.

  • Page 18: Acpi Features

    It is even more important for processors that have high CPU clock rates where noisy power transmission is present. The X12DPD-A6M25 motherboard accommodates a 14-pin ATX power supply. Although most power supplies generally meet the specifications required by the CPU, some are inadequate.

  • Page 19: Intel ® Optane™ Persistent Memory (Pmem) 200 Series Overview

    Chapter 1: Introduction 1.8 Intel Optane™ Persistent Memory (PMem) 200 Series ® Overview The 3rd Gen Intel Xeon Scalable Processors support the new Intel Optane Persistent ® Memory (PMem) 200 Series technology. PMem offers data persistence with higher capacity at similar latencies to the existing memory modules and provides hyper-speed storage capability for high performance computing platforms with flexible configuration options.

  • Page 20: Chapter 2 Installation

    Super X12DPD-A6M25 User's Manual Chapter 2 Installation 2.1 Static-Sensitive Devices Electrostatic Discharge (ESD) can damage electronic com ponents. To avoid damaging your motherboard, it is important to handle them very carefully. The following measures are generally sufficient to protect your equipment from ESD.

  • Page 21: Processor And Heatsink Installation

    Thermal grease is pre-applied on a new heatsink. No additional thermal grease is needed. • Refer to the Supermicro website for updates on processor and memory support. • All graphics in this manual are for illustrations only. Your components may look different.
  • Page 22 Super X12DPD-A6M25 User's Manual 1. The 3rd Gen Intel Xeon Scalable Processor CPU Key Pin 1 = Pin 1 = CPU Key = Cutout Processor Top View...
  • Page 23 Chapter 2: Installation 2. The Processor Carrier Carrier Bottom View...
  • Page 24 Super X12DPD-A6M25 User's Manual 3. Heatsink Note: Exercise extreme care when handling the heatsink. Pay attention to the edges of heatsink fins which can be sharp! To avoid damaging the heatsink, please do not apply excessive force on the fins when handling the heatsink.
  • Page 25 Chapter 2: Installation Overview of the CPU Socket The CPU socket is protected by a plastic protective cover. Plastic Protective Cover CPU Socket...
  • Page 26 Super X12DPD-A6M25 User's Manual Overview of the Processor Carrier Assembly The processor carrier assembly contains a 3rd Gen Intel Xeon Scalable processor and a processor carrier. Carefully follow the instructions given in the installation section to place a processor into the carrier to create a processor carrier.
  • Page 27 Chapter 2: Installation Overview of the Processor Heatsink Module The Processor Heatsink Module (PHM) contains a heatsink, a processor carrier, and a 3rd Gen Intel Xeon Scalable processor. 1. Heatsink (with Thermal Grease) 2. Processor Carrier 3. The 3rd Gen Intel Xeon Scalable Processor Bottom View 4.
  • Page 28 Super X12DPD-A6M25 User's Manual Creating the Processor Carrier Assembly The processor carrier assembly contains a 3rd Gen Intel Xeon Scalable Family processor and a processor carrier. To create the processor carrier assembly, please follow the steps below: Note: Before installation, be sure to follow the instructions given on Page 1 and Page 2 of this chapter to properly prepare yourself for installation.
  • Page 29 Chapter 2: Installation 3. Locate the lever on the CPU socket and press the lever down as shown below. Lever 4. Using Pin 1 as a guide, carefully align the CPU keys (A and B) on the processor against the CPU keys on the carrier (a and b) as shown in the drawing below. 5.
  • Page 30 Super X12DPD-A6M25 User's Manual Creating the Processor Heatsink Module (PHM) After creating the processor carrier assembly, please follow the instructions below to mount the processor carrier into the heatsink to form the processor heatsink module (PHM). Note: If this is a new heatsink, the thermal grease has been pre-applied on the un- derside.
  • Page 31 Chapter 2: Installation Preparing the CPU Socket for Installation This motherboard comes with a plastic protective cover installed on the CPU socket. Remove it from the socket by following the instructions given in the drawings below. Removing the plastic protective cover from the socket 1.
  • Page 32 Super X12DPD-A6M25 User's Manual Preparing to Install the Processor Heatsink Module (PHM) into the CPU Socket After assembling the Processor Heatsink Module (PHM), you are ready to install it into the CPU socket. To ensure the proper installation, please follow the procedures below: 1.
  • Page 33 Chapter 2: Installation Installing the Processor Heatsink Module (PHM) 1. Align peek nut "A", which is next to the triangle (Pin 1) on the heatsink, against threaded fastener "a" on the CPU socket. Then align peek nuts "B", "C", and "D" on the heatsink against threaded fasteners "b", "c", and "d"...
  • Page 34 Super X12DPD-A6M25 User's Manual Removing the Processor Heatsink Module from the CPU Socket Before removing the processor heatsink module (PHM) from the motherboard, unplug the AC power cord from all power supplies after shutting down the system. Then follow the steps below: 1.
  • Page 35 Chapter 2: Installation Removing the Processor Carrier Assembly from the Processor Heatsink Module (PHM) To remove the processor carrier assembly from the PHM, please follow the steps below: 1. Detach four plastic clips (marked a, b, c, d) on the processor carrier assembly from the four corners of heatsink (marked A, B, C, D) in the drawings below.
  • Page 36 Super X12DPD-A6M25 User's Manual Removing the Processor from the Processor Carrier Assembly Once you have removed the processor carrier assembly from the PHM, you are ready to remove the processor from the processor carrier by following the steps below. 1. Unlock the lever from its locking position and push the lever upwards to disengage the processor from the processor carrier as shown in the right drawing below.

  • Page 37: Motherboard Installation

    JLAN0 LAN1 LED1 JPNCSI2 JDBG1 JIF1 JAIOM CPU1 AIOM PCI-E 4.0 X16 JPWR4 JSATA2 JSATA1 S-SATA0~3 I-SATA0~7 SAN MAC X12DPD-A6M25 MAC CODE DESIGNED IN USA REV:1.01 JNVME1 BAR CODE BIOS P2-NVMe0 x8 LICENSE CPU2 CPU1 JNVME6 JNVME4 P2-NVMe3 x8 P2-NVMe2 x8...
  • Page 38 Super X12DPD-A6M25 User's Manual Installing the Motherboard 1. Install the I/O shield into the back of the chassis, if applicable. 2. Locate the mounting holes on the motherboard. See the previous page for the location. 3. Locate the matching mounting holes on the chassis. Align the mounting holes on the motherboard against the mounting holes on the chassis.

  • Page 39: Memory Support And Installation

    Memory Support The X12DPD-A6M25 supports up to 4TB of 3DS LRDIMM/LRDIMM/3DS RDIMM/RDIMM DDR4 ECC memory with speeds of 3200/2933/2666 MHz in 16 memory slots and up to 4TB of Intel Optane PMem 200 Series memory with speeds of up to 3200 MHz. (See the notes below.)
  • Page 40 Super X12DPD-A6M25 User's Manual Memory Population Table for the 3rd Gen Intel Scalable Processor Note 1: The following memory population table supports Supermicro X12DP moth- erboards with 16 DIMM memory slots onboard, such as X12DPFR-AN6, X12DPD-L/ M256, X12DAi-N6, X12DPG-QT6, X12DDW-A6, and X12DPT-PT6.
  • Page 41 Chapter 2: Installation PMem 200 Series Population Table for X12DP Motherboards (with 16 Slots) ® Note: The Intel Optane Persistent Memory (PMem) 200 Series are supported by the 3rd Gen Intel Xeon Scalable (83xx/63xx/53xx/4314 Series) Processors. PMem 200 Series Population Table for X12DP 16-DIMM Motherboards (within 1 CPU socket) DDR4+PMem Mode AD Interleave...
  • Page 42 Super X12DPD-A6M25 User's Manual DIMM Installation COM1 JUSB2 PRESS FIT PRESS FIT JSFP1 JSFP0 JUIB1 JVGA1 JRK1 BMC_LAN JPL1 JUSB1 JDBG JPFR1 JLAN2 JP_MX1 JM21 JM22 LEDBMC 1. Insert the desired number of DIMMs into the memory slots based M.2-H SLOT1 M.2-H SLOT2...
  • Page 43 Chapter 2: Installation DIMM Removal Press both release tabs on the ends of the DIMM module to unlock it. Once the DIMM module is loosened, remove it from the memory slot. Warning! Please do not use excessive force when pressing the release tabs on the ends of the DIMM socket to avoid causing any damage to the DIMM module or the DIMM socket.

  • Page 44: Rear I/O Ports

    Super X12DPD-A6M25 User's Manual 2.5 Rear I/O Ports See the figure below for the locations and descriptions of the various I/O ports on the rear of the motherboard. COM1 JUSB2 PRESS FIT PRESS FIT JSFP1 JSFP0 JVGA1 JUIB1 JRK1 BMC_LAN...
  • Page 45 JLAN0 LAN1 LED1 JPNCSI2 JDBG1 JIF1 JAIOM CPU1 AIOM PCI-E 4.0 X16 JPWR4 JSATA2 JSATA1 S-SATA0~3 I-SATA0~7 SAN MAC X12DPD-A6M25 MAC CODE DESIGNED IN USA REV:1.01 JNVME1 BAR CODE BIOS P2-NVMe0 x8 LICENSE CPU2 CPU1 JNVME6 JNVME4 P2-NVMe3 x8 P2-NVMe2 x8...
  • Page 46 Super X12DPD-A6M25 User's Manual LAN Ports (LAN1/LAN2 and BMC LAN) Two Ethernet LAN ports (LAN1/LAN2) and an BMC dedicated LAN (BMC LAN) are located on the rear I/O panel. LAN1/LAN2 ports support 25G SFP+ LAN connection. The BMC dedicated LAN (BMC_LAN1), provides LAN support for the BMC (Baseboard Management Controller).
  • Page 47 JLAN0 LAN1 LED1 JPNCSI2 JDBG1 JIF1 JAIOM CPU1 AIOM PCI-E 4.0 X16 JPWR4 JSATA2 JSATA1 S-SATA0~3 SAN MAC I-SATA0~7 X12DPD-A6M25 MAC CODE DESIGNED IN USA REV:1.01 JNVME1 BAR CODE BIOS P2-NVMe0 x8 LICENSE CPU2 CPU1 JNVME6 JNVME4 P2-NVMe2 x8 P2-NVMe3 x8...
  • Page 48 Super X12DPD-A6M25 User's Manual UID (Unit Idenfication)/BMC Reset Switch and UID/BMC Reset LED Indicators A UID LED/BMC Reset switch (JUIDB1) is located on the rear side of the motherboard. This switch has dual functions. It can be used to identify a system unit that is in need of service, and it can also be used to reset the BMC settings.

  • Page 49: Front Control Panel

    Reset Button can change to UID function by JP2. These connectors are designed specifically for use with Supermicro chassis. See the figure below for the descriptions of the front control panel buttons and LED indicators.
  • Page 50 Super X12DPD-A6M25 User's Manual Front Control Panel LEDs Power Button Ground Reset Button Ground Power Fail (for LED6) 3.3V Red+ Blue+ (Blue LED_Cathode_UID) (Red OH/Fan Fail/PWR Fail for LED5/Blue UID LED) NIC2 (Activity) LED NIC2 (Link) LED NIC1 (Link) LED NIC1 (Activity) LED ID_UID/3.3V Stby...
  • Page 51 Chapter 2: Installation Power On and BMC/BIOS Status LED Button The Power On and BMC/BIOS Status LED button is located on pins 1 and 2 of JF1. Momentarily contacting both pins will power on/off the system or display BMC/BIOS status. Refer to the tables below for more information.
  • Page 52 Super X12DPD-A6M25 User's Manual Power Fail LED The Power Fail LED connection is located on pins 5 and 6 of JF1. When this LED turns solid red, it indicates a power failure. Refer to the table below for pin definitions.
  • Page 53 Chapter 2: Installation NIC1/NIC2 (LAN1/LAN2) The NIC (Network Interface Controller) LED connection for LAN port 1 is located on pins 11 and 12 of JF1, and LAN port 2 is on pins 9 and 10. Refer to the tables below for pin definitions. LAN1/LAN2 LED LAN1/LAN2 LED Pin Definitions (JF1)
  • Page 54 Super X12DPD-A6M25 User's Manual FP Power LED The Front Panel Power LED connection is located on pins 15 and 16 of JF1. Refer to the table below for pin definitions. FP Power LED Pin Definitions (JF1) Pins Definition 3.3V FP PWR LED NMI Button The non-maskable interrupt (NMI) button header is located on pins 19 and 20 of JF1.

  • Page 55: Connectors

    1. JPWR1 (14-pin) JIF1 JAIOM CPU1 AIOM PCI-E 4.0 X16 2. JPWR2 (8-pin JPWR4 JSATA2 JSATA1 S-SATA0~3 SAN MAC I-SATA0~7 X12DPD-A6M25 MAC CODE 3. JPWR3 (8-pin) DESIGNED IN USA REV:1.01 JNVME1 BAR CODE BIOS P2-NVMe0 x8 LICENSE 4. JPWR4 (4-pin)
  • Page 56 Super X12DPD-A6M25 User's Manual Headers Fan Headers There are six 4-pin fan headers (FAN1~FAN6 ) located on the front panel (see locations below). All these 4-pin fan headers are backwards compatible with the traditional 3-pin fans. Fan Header Pin Definitions...
  • Page 57 The JTPM1 header is used to connect a Trusted Platform Module (TPM)/Port 80, which is available from Supermicro (optional). A TPM/Port 80 connector is a security device that supports encryption and authentication in hard drives. It allows the motherboard to deny access if the TPM associated with the hard drive is not installed in the system.
  • Page 58 Super X12DPD-A6M25 User's Manual VROC RAID Key Header A VROC RAID Key (RAID_KEY) header is located at JRK1 on the motherboard. Install a VROC RAID Key on JRK1 for NVMe RAID support as shown in the illustration below. Please refer to the layout below for the location of JRK1.
  • Page 59 JLAN0 LAN1 LED1 JPNCSI2 JDBG1 JIF1 JAIOM CPU1 AIOM PCI-E 4.0 X16 JPWR4 JSATA2 JSATA1 S-SATA0~3 I-SATA0~7 SAN MAC X12DPD-A6M25 MAC CODE DESIGNED IN USA REV:1.01 JNVME1 BAR CODE BIOS P2-NVMe0 x8 LICENSE CPU2 CPU1 JNVME4 JNVME6 P2-NVMe3 x8 P2-NVMe2 x8...
  • Page 60 Super X12DPD-A6M25 User's Manual Chassis Intrusion A Chassis Intrusion header is located at JL1 on the motherboard. Attach the appropriate cable from the chassis to inform you when the chassis is opened. Refer to the table below for pin definitions.
  • Page 61 Chapter 2: Installation M.2 Slots The X12DPD-A6M25 has one PCIe 3.0 x4 (SATA M.2 Slot1) and one PCIe 3.0 x1 (SATA M.2 Slot2). M.2 was formerly Next Generation Form Factor (NGFF) and serves to replace mini PCIe. M.2 allows for a variety of card sizes, increased functionality, and spatial efficiency.
  • Page 62 Super X12DPD-A6M25 User's Manual I-SATA 3.0 and S-SATA 3.0 Ports This motherboard has 8 I-SATA 3.0 ports (I-SATA0~7) and 4 S-SATA ports (S-SATA0~3). These SATA ports, supported by the C621A chipset, provide serial-link signal connections. 1. S-SATA0~3 2. I-SATA0~7 COM1...
  • Page 63 5. JNVME5 LED1 6. JNVME6 JPNCSI2 JDBG1 JIF1 JAIOM CPU1 AIOM PCI-E 4.0 X16 JPWR4 JSATA2 JSATA1 S-SATA0~3 SAN MAC I-SATA0~7 X12DPD-A6M25 MAC CODE DESIGNED IN USA REV:1.01 BIOS JNVME1 BAR CODE P2-NVMe0 x8 LICENSE CPU2 CPU1 JNVME6 JNVME4 P2-NVMe3 x8...

  • Page 64: Jumper Settings

    Super X12DPD-A6M25 User's Manual 2.8 Jumper Settings How Jumpers Work To modify the operation of the motherboard, jumpers can be used to choose between optional settings. Jumpers create shorts between two pins to change the function of the connector. Pin 1 is identified with a square solder pad on the printed circuit board. See the diagram below for an example of jumping pins 1 and 2.
  • Page 65 Chapter 2: Installation CMOS Clear JBT1 is used to clear CMOS, which will also clear any passwords. Instead of pins, this jumper consists of contact pads to prevent accidentally clearing the contents of CMOS. To Clear CMOS 1. First power down the system and unplug the power cord(s). 2.
  • Page 66 Super X12DPD-A6M25 User's Manual LAN Port Enable/Disable Jumper JPL1 allows the user to enable the onboard LAN Port1/LAN Port2. The default setting is pins 1-2 to enable the connection. Refer to the table below for jumper settings. LAN Enable/Disable Jumper Settings...
  • Page 67 JLAN0 LAN1 LED1 JPNCSI2 JDBG1 JIF1 JAIOM CPU1 AIOM PCI-E 4.0 X16 JPWR4 JSATA2 JSATA1 S-SATA0~3 I-SATA0~7 SAN MAC X12DPD-A6M25 MAC CODE DESIGNED IN USA REV:1.01 JNVME1 BAR CODE BIOS P2-NVMe0 x8 LICENSE CPU2 CPU1 JNVME4 JNVME6 P2-NVMe2 x8 P2-NVMe3 x8...
  • Page 68 Super X12DPD-A6M25 User's Manual Watchdog Watchdog (JWD1) is a system monitor that can reboot the system when a software application hangs. Close pins 1-2 to reset the system if an application hangs. Close pins 2-3 to generate a non-maskable interrupt (NMI) signal for the application that hangs. Refer to the table below for jumper settings.

  • Page 69: Led Indicators

    JLAN0 LAN1 LED1 JPNCSI2 JDBG1 JIF1 JAIOM CPU1 AIOM PCI-E 4.0 X16 JPWR4 JSATA2 JSATA1 S-SATA0~3 SAN MAC I-SATA0~7 X12DPD-A6M25 MAC CODE DESIGNED IN USA REV:1.01 JNVME1 BAR CODE BIOS P2-NVMe0 x8 LICENSE CPU2 CPU1 JNVME6 JNVME4 P2-NVMe2 x8 P2-NVMe3 x8...
  • Page 70 Super X12DPD-A6M25 User's Manual BMC Heartbeat LED A BMC Heartbeat LED is located at LEDM1 on the motherboard. When LEDM1 is blinking, the BMC is functioning normally. Refer to the table below for more information. BMC Heartbeat LED Indicator LED Color...
  • Page 71 JLAN0 LAN1 LED1 JPNCSI2 JDBG1 JIF1 JAIOM CPU1 AIOM PCI-E 4.0 X16 JPWR4 JSATA2 JSATA1 S-SATA0~3 SAN MAC I-SATA0~7 X12DPD-A6M25 MAC CODE DESIGNED IN USA REV:1.01 BIOS JNVME1 BAR CODE P2-NVMe0 x8 LICENSE CPU2 CPU1 JNVME4 JNVME6 P2-NVMe3 x8 P2-NVMe2 x8...

  • Page 72: Chapter 3 Troubleshooting

    Super X12DPD-A6M25 User's Manual Chapter 3 Troubleshooting 3.1 Troubleshooting Procedures Use the following procedures to troubleshoot your system. If you have followed all of the procedures below and still need assistance, refer to the ‘Technical Support Procedures’ and/ or ‘Returning Merchandise for Service’ section(s) in this chapter. Always disconnect the AC power cord before adding, changing or installing any non hot-swap hardware components.
  • Page 73 Chapter 3: Troubleshooting No Video 1. If the power is on, but you have no video, remove all add-on cards and cables. 2. Use the speaker to determine if any beep codes are present. Refer to Appendix A for details on beep codes. 3.
  • Page 74 Super X12DPD-A6M25 User's Manual Losing the System's Setup Configuration 1. Make sure that you are using a high-quality power supply. A poor-quality power supply may cause the system to lose the CMOS setup information. Refer to Chapter 2 for details on recommended power supplies.
  • Page 75 Chapter 3: Troubleshooting 4. Identifying bad components by isolating them: If necessary, remove a component in question from the chassis, and test it in isolation to make sure that it works properly. Replace a bad component with a good one. 5.

  • Page 76: Technical Support Procedures

    Before contacting Technical Support, please take the following steps. Also, please note that as a motherboard manufacturer, Supermicro also sells motherboards through its channels, so it is best to first check with your distributor or reseller for troubleshooting services. They should know of any possible problems with the specific system configuration that was sold to you.

  • Page 77: Frequently Asked Questions

    RMA Department at Supermicro for repair. Note 2: For BIOS update and recovery instructions, please refer to the Firmware Up- date and Recovery Instructions for Supermicro's X12 Series Motherboard User's Guide posted on our website at http://www.supermicro.com/support/manuals/.

  • Page 78: Battery Removal And Installation

    Super X12DPD-A6M25 User's Manual 3.4 Battery Removal and Installation Battery Removal To remove the onboard battery, follow the steps below: 1. Power off your system and unplug your power cable. 2. Locate the onboard battery as shown below. 3. Using a tool such as a pen or a small screwdriver, push the battery lock outwards to unlock it.

  • Page 79: Returning Merchandise For Service

    For faster service, you can also request a RMA authorization online (http://www.supermicro. com/RmaForm/). This warranty only covers normal consumer use and does not cover damages incurred in shipping or from failure due to the alternation, misuse, abuse or improper maintenance of products.

  • Page 80: Chapter 4 Uefi Bios

    UEFI BIOS 4.1 Introduction This chapter describes the AMIBIOS™ setup utility for the X12DPD-A6M25 motherboard. The BIOS is stored on a chip and can be easily upgraded using the BMC WebUI or the SUM utility. Note: Due to periodic changes to the BIOS, some settings may have been added or deleted and might not yet be recorded in this manual.

  • Page 81: Main Setup

    Note: The time is in the 24-hour format. For example, 5:30 P.M. appears as 17:30:00. The date's default value is the BIOS build date after the RTC (Real Time Clock) reset. Supermicro X12DPD-A6M25 BIOS Version This feature displays the version of the BIOS ROM used in the system.
  • Page 82 Super X12DPD-A6M25 User's Manual Memory Information Total Memory This feature displays the total size of memory available in the system.

  • Page 83: Advanced Setup Configurations

    Chapter 4: UEFI BIOS 4.3 Advanced Setup Configurations Use the arrow keys to select the Advanced submenu and press <Enter> to access the submenu items: Warning: Take Caution when changing the Advanced settings. An incorrect value may cause the system to malfunction. When this occurs, restore the setting to the manufacturer default setting. Boot Feature ...
  • Page 84 Super X12DPD-A6M25 User's Manual Wait For 'F1' If Error Select Enabled to force the system to wait until the <F1> key is pressed if an error occurs. The options are Enabled and Disabled. Interrupt 19 Capture Interrupt 19 is the software interrupt that handles the boot disk function. When this feature is set to Immediate, the ROM BIOS of the host adaptors will "capture"...
  • Page 85 Chapter 4: UEFI BIOS Restore on AC Power Loss Use this feature to set the power state after a power outage. Select Power Off for the system power to remain off after a power loss. Select Power On for the system power to be turned on after a power loss.
  • Page 86 Super X12DPD-A6M25 User's Manual CPU Configuration  Warning: Setting the wrong values in the following sections may cause the system to malfunc- tion. Processor Configuration  The following CPU information will be displayed: • Processor BSP Revision • Processor Socket •...
  • Page 87 Chapter 4: UEFI BIOS CPU1 Core Disable Bitmap/CPU2 Core Disable Bitmap  The following features will display: Available Bitmap: The available Bitmap will displayed. Core Disable Bitmap (Hex) Enter 0 to enable all CPU cores. Enter FFFFFFFFFFF to disable all CPU cores. Please note that at least one core per CPU must be enabled.
  • Page 88 Super X12DPD-A6M25 User's Manual Select Enable to enable the Intel Vanderpool Technology for Virtualization platform support, which will allow multiple operating systems to run simultaneously on the same computer to maximize system resources for performance enhancement. The options are Disable and Enable.
  • Page 89 Chapter 4: UEFI BIOS ---------------------------------------------------------------- Software Guard Extension (SGX) -------------------------------------------------------------- Note: For SGX to work properly, please use the CPUs that support this feature and be sure to install one CPU per channel. SGX Factory Reset (Available when TME-MT is set to Enabled and the SGX feature is supported by the CPU used in the system) Select Enabled to reset the factory default setting for SGX (Software Guard Extension).
  • Page 90 Super X12DPD-A6M25 User's Manual ENERGY_PERF_BIAS_CFG Mode (ENERGY PERFORMANCE BIAS CONFIGURATION Mode) (Available when "Power Performance Tuning" is set to BIOS Controls EPB) Use this feature to configure the proper operation setting for your machine by achieving the desired system performance level and energy saving (efficiency) level at the same time.
  • Page 91 Chapter 4: UEFI BIOS Activate SST-BF (Speed Select Technology-Base Frequency) Select Enable for Intel Speed Select Technology-Base Frequency support. The options are Disable and Enable. Configure SST-BF (Available when Activate SST-BF is set to Enable) When this feature is set to Enable, the system BIOS will configure SST-BF High Priority Core settings so that system software does not have to configure these settings.
  • Page 92 Super X12DPD-A6M25 User's Manual Frequency Prioritization  RAPL Prioritization Select Enable to prioritize RAPL (Running Average Power Limit) which sets the power consumption limit for a processor to save energy. The options are Enable and Disable. CPU C State Control ...
  • Page 93 Chapter 4: UEFI BIOS CPU T State Control Available when "Power Technology" is set to  Custom) Software Controlled T-States If this feature is set to Enable, CPU throttling will be controlled by the OS, which will reduce the speed of CPU. The options are Enable and Disable. T-State Throttle Level (Available when "Software Controlled T-States"...
  • Page 94 Super X12DPD-A6M25 User's Manual Chipset Configuration  Warning: Setting the wrong values in the following items may cause the system to malfunction. North Bridge  This feature allows the user to configure Intel North Bridge parameters. Uncore Configuration  This section allows the user to configure the following Uncore settings: •...
  • Page 95 Chapter 4: UEFI BIOS Degrade Precedence Use this feature to select the degrading precedence option for Ultra Path Interconnect (UPI) connections. Select Topology Precedent to degrade UPI features if the system options are in conflict. Select Feature Precedent to degrade UPI topology if system options are in conflict.
  • Page 96 Super X12DPD-A6M25 User's Manual generate snoops (instead of memory lockups) for WCiLF (Cores). The options are Disable, Auto, Enable for Remote InvItoM Hybrid Push, InvItoM AllocFlow, Enable for Remote InvItoM Hybrid AllocNonAlloc, and Enable for Remote InvItoM and Remote WViLF.
  • Page 97 Chapter 4: UEFI BIOS LLC Dead Line Alloc Select Enable to opportunistically fill the deadlines in the LLC. The options are Enable, Disable, and Auto. Memory Configuration  This feature allows the user to configure the Integrated Memory Controller (iMC) settings. STEP DRAM Test Select Enable to support Samsung TestBIOS and Enhanced PPR (Post Package Repair) DRAM Test.
  • Page 98 Super X12DPD-A6M25 User's Manual eADR Support (Available when a BPS device is detected & is supported by the hardware design of the motherboard) Select Enable for Extended ADR (Async DIMM Module Self-Refresh) support to enhance memory performance. The options are Disable, Enable, and Auto.
  • Page 99 Chapter 4: UEFI BIOS Memory RAS (Reliability_Availability_Serviceability) Configuration  Use this submenu to configure the following Memory RAS settings. Enable Pcode WA (Workaround) for SAI (Security Attribute of the Initiator) PG (Policy Group) Pcode, a register transfer language designed for reverse engineering, translates individual processor instructions into a sequence of Pcode operations in order to facilitate the construction of data-flow graphs and disassembling of processor instructions for machine application.
  • Page 100 Super X12DPD-A6M25 User's Manual Patrol Scrub Patrol Scrubbing is a process that allows the CPU to correct correctable memory errors detected in a memory module and send the corrections to the requestor (the original source). When this feature is set to Enable, the IO hub will read and write back one cache line every 16K cycles if there is no delay caused by internal processing.
  • Page 101 Chapter 4: UEFI BIOS IOU3 (IIO PCIe Port 4) Use this feature to configure the PCIe Bifurcation setting for a PCIe port specified by the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto. IOU4 (IIO PCIe Port 5) Use this feature to configure the PCIe Bifurcation setting for a PCIe port specified by the user.
  • Page 102 Super X12DPD-A6M25 User's Manual Relaxed Ordering Select Yes to allow certain transactions to be processed and completed before other transactions that have already been enqueued. The options are Yes and No. Intel VT for Directed I/O (VT-d)  Intel VT for Directed I/O (VT-d) ®...
  • Page 103 Chapter 4: UEFI BIOS Intel VMD for Volume Management Device on CPU1 ® (Available when  NVMe Mode Switch is set to Manual only) VMD Configuration for PCH Ports Enable/Disable VMD Select Enable to enable Intel Volume Management Device Technology support for the root port specified by the user.
  • Page 104 Super X12DPD-A6M25 User's Manual Hot Plug Capable Select Enable to enable Hot Plug support for the root ports specified by the user, which will allow the user to change the devices on those root ports without shutting down the system.
  • Page 105 Chapter 4: UEFI BIOS Intel VMD for Volume Management Device on CPU2 ® (Available when  NVMe Mode Switch is set to Manual only) VMD Configuration for IOU 0 Enable/Disable VMD Select Enable to enable Intel Volume Management Device Technology support for the root port specified by the user.
  • Page 106 Super X12DPD-A6M25 User's Manual *If Enable/Disable VMD is set to Enable to a port specified by the user, the following items will display the following items for the port selected. CPU1 NVMe1D VMD/VMD Port 4B/VMD Port 4C/VMD Port 4D Select Enable to enable Intel Volume Management Device Technology support for the root port specified.
  • Page 107 Chapter 4: UEFI BIOS *If this feature is set to On Fatal Error/On Fatal and Non-Fatal Errors, the following features will be displayed: IIO eDPC Interrupt (Available when "IIO eDPC Support" is set to On Fatal Error/On Fatal and Non-Fatal Errors) Select Enable to enable IIO eDPC Interrupt support.
  • Page 108 Super X12DPD-A6M25 User's Manual Server ME (Management Engine) Configuration  This feature displays the following general ME configuration settings: • General ME Configuration • Oper. (Operation) Firmware Version • Backup Firmware Version • Recovery Firmware Version • ME Firmware Status #1/ME Firmware Status #2 •...
  • Page 109 Chapter 4: UEFI BIOS SATA Configuration  PCH SATA Configuration SATA Controller This feature enables or disables the onboard SATA controller supported by the Intel PCH chip. The options are Enable and Disable. Configure SATA as (Available when "SATA Controller" is set to Enable) Select AHCI to configure a SATA drive specified by the user as an AHCI drive.
  • Page 110 Super X12DPD-A6M25 User's Manual SATA RAID Option ROM/UEFI Driver (Available when "Configure SATA as" is set to RAID) Select EFI to load the EFI driver for system boot. Select Legacy to load a legacy driver for system boot. The options are Disable, EFI, and Legacy.
  • Page 111 Chapter 4: UEFI BIOS sSATA Configuration  PCH sSATA Configuration sSATA Controller This feature enables or disables the onboard sSATA controller supported by the Intel PCH. The options are Enable and Disable. Configure sSATA as (Available when "sSATA Controller" is set to Enable) Select AHCI to configure an sSATA drive specified by the user as an AHCI drive.
  • Page 112 Super X12DPD-A6M25 User's Manual sSATA RAID Option ROM/UEFI Driver (Available when "Configure sSATA as" is set to RAID) Select EFI to load the EFI driver for system boot. Select Legacy to load a legacy driver for system boot. The options are Disable, EFI, and Legacy.
  • Page 113 Chapter 4: UEFI BIOS Network Stack Configuration  Network Stack Select Enabled to enable PXE (Preboot Execution Environment) or UEFI (Unified Extensible Firmware Interface) for network stack support. The options are Enabled and Disabled. *If "Network Stack" is set to Enabled, the following items will display: IPv4 PXE Support Select Enabled to enable IPv4 PXE boot support.
  • Page 114 Super X12DPD-A6M25 User's Manual Media Detect Time Use this feature to select the wait time (in seconds) for the BIOS ROM to detect the presence of a LAN media either via the Internet connection or via a LAN port. The default is 1.
  • Page 115 Chapter 4: UEFI BIOS MAC:3CECEF80AD1B - IPv6 Network Configuratio  Note: The Interface ID "MAC: 3CECEF80AD1A" is for illustration only. It is unique per system. When you select this menu and press <Enter>, the following items will display: Enter Configuration Menu ...
  • Page 116 Super X12DPD-A6M25 User's Manual MAC:3CECEF80AD1A - IPv4 Network Configuration  Note: The Interface ID "MAC: 3CECEF80AD1A" is for illustration only. It is unique per system. Configured Select Enabled to show whether the network address has been successfully configured or not. The options are Enabled and Disabled.
  • Page 117 Chapter 4: UEFI BIOS MAC:3CECEF80AD1B - IPv6 Network Configuratio  Note: The Interface ID "MAC: 3CECEF80AD1B" is for illustration only. It is unique per system. When you select this menu and press <Enter>, the following items will display: Enter Configuration Menu ...
  • Page 118 Super X12DPD-A6M25 User's Manual MAC:3CECEF80AD1B - IPv4 Network Configuration  Note: The Interface ID "MAC: 3CECEF80AD1B" is for illustration only. It is unique per system. Configured Select Enabled to show whether the network address has been successfully configured or not. The options are Enabled and Disabled.
  • Page 119 Chapter 4: UEFI BIOS KMIP Server Configuration  This feature displays the configuration settings for the KMIP (Key Management Interoperability Protocol) server, which will allow the client machines to ask a server to encrypt or decrypt data without a direct access key. KMIP Key Management Interoperability Protocol) Server IP Address This feature displays the IP address for the KMIP server.
  • Page 120 Super X12DPD-A6M25 User's Manual Client UserName Use this feature to enter a Username for the KMIP server. Client Password Use this feature to enter a password for the KMIP server. KMS TLS Certificate | Size This feature displays the Transport Layer Security (TLS) Certificate and its size.
  • Page 121 Chapter 4: UEFI BIOS PCIe/PCI/PnP Configuration  The following PCI information will be displayed: • PCI Bus Driver Version • PCI Devices Common Settings Above 4G Decoding (Available if the system supports 64-bit PCI decoding) Select Enabled to decode a PCI device that supports 64-bit in the space above 4G Address. The options are Enabled and Disabled.
  • Page 122 Super X12DPD-A6M25 User's Manual Consistent Device Name Support Select Enabled for ACPI_DSM device name support for onboard devices and slots. The options are Disabled and Enabled. MMIO High Base Use this feature to select the base memory size according to memory-address mapping for the IO hub.
  • Page 123 Chapter 4: UEFI BIOS Onboard LAN1 Option ROM (Available when Onboard LAN Devices is set to Enabled) Select EFI to boot up your system using an EFI (Extensible Firmware Interface) device installed on the LAN 1 port. The default setting for LAN 1 port is EFI. Onboard NVMe1 Option ROM ~ Onboard NVMe12 Option ROM Select EFI to boot up your system using an EFI (Extensible Firmware Interface) device installed on the LAN 1 port.
  • Page 124 Super X12DPD-A6M25 User's Manual Super IO Configuration  Super IO Chip AST2600  Serial Port 1 Configuration Serial Port 1 Select Enabled to enable Serial Port 1. The options are Enabled and Disabled. Device Settings (Available when "Serial Port 1" is set to Enabled) This feature displays the base I/O port address and the Interrupt Request address of Serial Port 1.
  • Page 125 Chapter 4: UEFI BIOS  Serial Port 2 Configuration Serial Port Select Enabled to enable Serial Port 2. The options are Enabled and Disabled. Device Settings (Available when "Serial Port 2" is set to Enabled) This feature displays the base I/O port address and the Interrupt Request address of Serial Port 2.
  • Page 126 Super X12DPD-A6M25 User's Manual Serial Port Console Redirection  COM 1 Console Redirection Select Enabled to enable COM Port 1 for Console Redirection, which will allow a client machine to be connected to a host machine at a remote site for networking. The options are Enabled and Disabled.
  • Page 127 Chapter 4: UEFI BIOS Data Bits Use this feature to set the data transmission size for Console Redirection. The options are 7 (Bits) and 8 (Bits). Parity A parity bit can be sent along with regular data bits to detect data transmission errors. Select Even if the parity bit is set to 0, and the number of 1's in data bits is even.
  • Page 128 Super X12DPD-A6M25 User's Manual Redirection After BIOS Post Use this feature to enable or disable Legacy Console Redirection after BIOS POST. When the option - Bootloader is selected, Legacy Console Redirection is disabled before booting the OS. When the option - Always Enable is selected, Legacy Console Redirection remains enabled upon OS bootup.
  • Page 129 Chapter 4: UEFI BIOS mark as a parity bit to be sent along with the data bits. Select Space to add a Space as a parity bit to be sent with your data bits. The options are None, Even, Odd, Mark and Space. Stop Bits A stop bit indicates the end of a serial data packet.
  • Page 130 Super X12DPD-A6M25 User's Manual Serial Port for Out-of-Band Management/Windows Emergency Management Services (EMS) The feature allows the user to configure Console Redirection settings to support Out-of- Band Serial Port management. Console Redirection (for EMS) Select Enabled to use a COM port specified by the user for EMS Console Redirection. The options are Enabled and Disabled.
  • Page 131 Chapter 4: UEFI BIOS ACPI Settings  System ACPI Parameters Use this feature to configure Advanced Configuration and Power Interface (ACPI) power management settings and parameters for your system. NUMA Select Enabled to enable Non-Uniform Memory Access support to enhance system performance.
  • Page 132 Super X12DPD-A6M25 User's Manual Trusted Computing (Available when a TPM device is installed  and detected by the BIOS) When a TPM (Trusted-Platform Module) device is detected in your machine, the following information will display: • TPM 2.0 Device Found: •...
  • Page 133 Chapter 4: UEFI BIOS SHA-1 PCR Bank Select Enabled to enable SHA-1 PCR Bank support to enhance system integrity and data security. The options are Enabled and Disabled. SHA256 PCR Bank Select Enabled to enable SHA256 PCR Bank support to enhance system integrity and data security.
  • Page 134 Super X12DPD-A6M25 User's Manual PH (Platform Hierarchy) Randomization (for TPM Version 2.0 and above) Select Enabled for Platform Hierarchy Randomization support, which is used only during the platform developmental stage. This feature cannot be enabled in the production platforms. The options are Disabled and Enabled.
  • Page 135 Chapter 4: UEFI BIOS HTTP Boot Configuration When this submenu is selected, the following items will display: HTTP Boot Configuration HTTP Boot Policy Use this feature to set the HTTP Boot policy. The options are Apply to all LANs, Apply to Each LAN, and Boot Priority #1 instantly.
  • Page 136 Super X12DPD-A6M25 User's Manual Boot URI (Uniform Research Identifier) Enter a Boot URI with 128 characters or shorter. This Boot URI determines how IPv4 Boot Option & IPv6 Boot Option will be created. This feature is only supported on Dual or EFI Boot Mode.
  • Page 137 Chapter 4: UEFI BIOS TLS Authenticate Configuration  When this submenu is selected, the following items will display: Server CA Configuration This feature allows the user to configure the client certificate that is to be used by the server. Enroll Certification ...
  • Page 138 Super X12DPD-A6M25 User's Manual Delete Certification  This feature is used to delete the certificate if a certificate has been enrolled in the system. Client Certification Configuration This feature allows the user to configure the client certificate to be used by the server.
  • Page 139 Chapter 4: UEFI BIOS SMC PMem Configuration When this submenu is selected, the following items will display: SMCI PMem Information Select this submenu and press <Enter>, the following items will display: • PMem UEFI Drive Version • All Initialized DIMMs •...
  • Page 140 Super X12DPD-A6M25 User's Manual • DIMM [1] FW (Firmware) Version • DIMM [1] Capacity • DIMM [1] APP Direct Capacity • DIMM [1] Unconfigured Capacity • DIMM [1] Reserved Capacity • DIMM [1] Inaccessible Capacity • DIMM [2] Handle •...
  • Page 141 Chapter 4: UEFI BIOS • DIMM [3] UID (Unit ID) • DIMM [3] Serial Number • DIMM [3] FW (Firmware) Version • DIMM [3] Capacity • DIMM [3] APP Direct Capacity • DIMM [3] Unconfigured Capacity • DIMM [3] Reserved Capacity •...
  • Page 142 Super X12DPD-A6M25 User's Manual SMCI PMem Settings Select this submenu and press <Enter>, the following items will display: Create Goal Config (Configuration): Persistent: The default setting is [Do Nothing]. Memory Type Reserved [%] All PMem DIMMs have (the) same security state User Security Policy Use this feature to set the User Security Policy.
  • Page 143 Chapter 4: UEFI BIOS Intel Optane™ Persistent Memory Configuration ®  When you select this submenu and press <Enter>, the following screen will display: Intel Optane™ Persistent Memory Configuration ®  When you select this submenu and press <Enter>, the following screen will display: •...
  • Page 144 Super X12DPD-A6M25 User's Manual PMem Modules  This submenu allows the user to view and configure the following settings for the PMem memory modules installed in the system: Select a specific DIMM that you want to view. Note: The following section, which describes the status of PMem memory, is for illustra- tion only.
  • Page 145 Chapter 4: UEFI BIOS • DIMM UID: This feature displays the unique ID of the PMem module. • DIMM Handle: This feature displays the unique handle assigned to the PMem module. • DIMM Physical ID: This feature displays the physical ID of the PMem module. •...
  • Page 146 Super X12DPD-A6M25 User's Manual • Firmware Activation Quiece Required: This feature indicates whether Firmware Activation Quiesce is required for the PMem module. • Firmware Activation Time: This feature indicates the time needed to activate the firmware. • Manufacturer: This feature indicates the manufacturer of the PMem module.
  • Page 147 Chapter 4: UEFI BIOS • Total Width [b] • Speed [MHz] • Channel ID • Channel Position • Revision ID • Form Factor • Manufacturer ID • Controller Revision ID • IS New • Memory Capacity • APP Direct Capacity •...
  • Page 148 Super X12DPD-A6M25 User's Manual • Package Sparing Capable • Package Sparing Enabled • Package Spares Available • Configuration Status • SKU Violation • Population Violation • ARS Status • Overwrite PMem Module Status • Last Shutdown Time • Average Power Reporting Time Constant [ms] •...
  • Page 149 Chapter 4: UEFI BIOS • Poison Error Clear Counter • Media Temperature Injections Counter • Software Triggers Counter • Max Media Temperature [C] • Media Temperature Injection Enabled • Master Passphrase Enabled • Average Power • Average Power 12V • Average Power 1.2V •...
  • Page 150 Super X12DPD-A6M25 User's Manual Monitor Health  This submenu displays the following health information on a memory module being monitored. • Current Alarm Threshold Status Controller Temperature: (within the alarm threshold on all PM modules) • Controller Temperature: (within the alarm threshold on all PM modules).
  • Page 151 Chapter 4: UEFI BIOS Update Firmware  Use this feature to select the firmware image to be loaded on the PMem module. After loading the firmware image, please reboot the system and select Update for the firmware to take effect. The following items will display: Current Firmware Version This feature displays the current firmware version.
  • Page 152 Super X12DPD-A6M25 User's Manual Configure Security  Use this feature to configure the security settings for all onboard PMem modules. State Select Enabled to configure the security settings for the PMem modules installed in the system. The options are Disabled and Enabled.
  • Page 153 Chapter 4: UEFI BIOS Configure Data Policy  Use this feature to configure the data policy settings for all onboard PMem modules. Average Power Reporting Time Constant [ms] This feature specified the constant average power reporting time. Modify Average Power Reporting Time Constant Use this feature to modify the constant average power reporting time.
  • Page 154 Super X12DPD-A6M25 User's Manual Regions  Current Configuration Region ID 1  When this submenu is selected, the following items will display: • Region ID: This feature displays the Region ID of the PMem module. • DIMM ID: This feature displays the DIMM ID of the PMem module.
  • Page 155 Chapter 4: UEFI BIOS Provisioning  This submenu configures the memory allocation goal for the onboard PMem memory modules. Create Goal Configuration  When this submenu is selected, the following items will display: Create Goal Configuration for • Use this feature to select the target to create goal configuration for the PMem modules. The options are Platform and Socket.
  • Page 156 Super X12DPD-A6M25 User's Manual Delete Goal Configuration  Back to Previous Menu  Select this feature and press <Enter> to go back to the previous menu. Back to Main Menu  Select this feature and press <Enter> to go back to the Intel Optane™...
  • Page 157 Chapter 4: UEFI BIOS Back to Namespaces Back to Main Menu  Select this feature and press <Enter> to go back to the Intel Optane™ Persistent Memory ® Configuration menu. Create Namespace  Use this submenu to create a namespace. The following information will display: Name Region ID This feature displays the Region ID of the PMem module.
  • Page 158 Super X12DPD-A6M25 User's Manual Total Capacity  This feature allows the user to set the total PMem resource capacity allocated across all segments in the host server. PMem Module Capacities This section displays the following information: • Volatile: This feature specifies Volatile information of the PMem module.
  • Page 159 Chapter 4: UEFI BIOS Diagnostics  Perform Diagnostic Tests on DIMMs When you select this submenu and press <enter>, the following items will display: Choose Diagnostics Type: Use this feature to choose the type of diagnostics test to be performed on the PMem module installed in the system Quick Diagnostics Select Enabled for the quick diagnostics test to be performed on the PMem module installed...
  • Page 160 Super X12DPD-A6M25 User's Manual Preferences  View and/or modify user preferences Default DIMM ID This feature allows the user to view and to modify the default DIMM ID as displayed on the screen. The options are Handle and UID. Capacity Units This feature allows the user to view and to set the default capacity unit of the selected PMem to be displayed on the screen.
  • Page 161 Chapter 4: UEFI BIOS Driver Health This feature displays the following health information of the drivers installed in your system, including LAN controllers, as detected by the BIOS. Note: This section is provided for reference only, for the driver health status will dif- fer depending on the drivers installed in your system.

  • Page 162: Event Logs

    Super X12DPD-A6M25 User's Manual 4.4 Event Logs Use this feature to configure Event Log settings. Note: After you've made any changes on a setting below, please reboot the system for the changes you've made to take effect. Change SMBIOS Event Log Settings...
  • Page 163 Chapter 4: UEFI BIOS SMBIOS Event Log Standard Settings Log System Boot Event Select Enabled to log system boot events. The options are Enabled and Disabled. MECI (Multiple Event Count Increment) Enter the increment value for the multiple event counter. Enter a number between 1 to 255. The default setting is 1.

  • Page 164: Bmc

    Super X12DPD-A6M25 User's Manual 4.5 BMC This submenu displays the status of the Baseboard Management Controller (BMC), and allows the user to configure the following BMC settings. • BMC Firmware Revision: This feature indicates the BMC firmware used in your system.
  • Page 165 Chapter 4: UEFI BIOS When SEL is Full This feature allows the user to determine what the BIOS should do when the system event log is full. Select Erase Immediately to erase all events in the log when the system event log is full.
  • Page 166 Super X12DPD-A6M25 User's Manual ********************************* Configure IPv6 Support ********************************* • IPv6 Address Status: This feature displays the status of IPv6 addresses. • IPv6 Support: Select Enabled for IPv6 support. The options are Enabled and Disabled. • Configuration Address Source Use this feature to select the source of the IPv4 Connection. If Static is selected, you will need to know the IP address of the IPv4 connection and enter it to the system manually in the field.

  • Page 167: Security

    HDDs from being altered. The options are Enabled and Disabled. Note: For detailed instructions on how to configure Secure Boot settings, please refer to the Secure Boot Configuration User's Guide posted on the web page under the link: http://www.supermicro.com/support/manuals/.
  • Page 168 Super X12DPD-A6M25 User's Manual Lockdown Mode Select Enabled to support Lockdown Mode which will prevent existing data or keys stored in the system from being altered or changed in an effort to preserve system integrity and security. The options are Enabled and Disabled.
  • Page 169 Chapter 4: UEFI BIOS Restore Factory Keys  Select Yes to restore manufacturer default keys used to ensure system security. The options are Yes and No. Reset to Setup Mode  This feature resets the system to Setup Mode. Export Secure Boot Variables ...
  • Page 170 Super X12DPD-A6M25 User's Manual Authorized Signatures  Use this feature to enter and configure a set of values to be used as Authorized Signatures for the system. These values also indicate the sizes, keys numbers, and the sources of the authorized signatures. Select Update to update your "Authorized Signatures". Select Append to append your "Authorized Signatures".

  • Page 171: Boot

    Chapter 4: UEFI BIOS 4.7 Boot Use this feature to configure Boot Settings: Boot Mode Select Use this feature to select the type of devices from which the system will boot. The options are Legacy, UEFI (Unified Extensible Firmware Interface), and Dual. Note: When the Boot Mode Select feature above is set to Dual, be sure to set all OPROM-related settings to Legacy.
  • Page 172 Super X12DPD-A6M25 User's Manual  Delete Boot Option This feature allows the user to select a boot device to delete from the boot priority list. Delete Boot Option This feature allows the user to remove an EFI boot option from the boot priority list.

  • Page 173: Save & Exit

    Chapter 4: UEFI BIOS 4.8 Save & Exit Select the Save & Exit menu from the BIOS setup screen to configure the settings below. Save Options Discard Changes and Exit Select this option to exit from the BIOS setup utility without making any permanent changes to the system configuration and reboot the computer.
  • Page 174 Super X12DPD-A6M25 User's Manual Default Options Restore Optimized Defaults To set this feature, select Restore Optimized Defaults from the Exit menu and press <Enter> to load manufacturer optimized default settings which are intended for maximum system performance but not for maximum stability.

  • Page 175: Appendix A Bios Post Codes

    When BIOS performs the Power On Self Test, it writes checkpoint codes to I/O port 0080h. If the computer cannot complete the boot process, a diagnostic card can be attached to the computer to read I/O port 0080h (Supermicro p/n AOC-LPC80-20). For information on AMI updates, please refer to http://www.ami.com/products/.

  • Page 176: Appendix B Software

    USB/SATA DVD drive, or a USB flash drive, or the BMC KVM console. 2. Retrieve the proper RST/RSTe driver. Go to the Supermicro web page for your motherboard and click on "Download the Latest Drivers and Utilities", select the proper driver, and copy it to a USB flash drive.
  • Page 177 Appendix B: Software 4. During Windows Setup, continue to the dialog where you select the drives on which to install Windows. If the disk you want to use is not listed, click on “Load driver” link at the bottom left corner. Figure B-2.

  • Page 178: Driver Installation

    The Supermicro website contains drivers and utilities for your system at https://www. supermicro.com/wdl/driver/. Some of these must be installed, such as the chipset driver. After accessing the website, go into the CDR_Images (in the parent directory of the above link) and locate the ISO file for your motherboard. Download this file to a USB flash drive or a DVD.

  • Page 179: Superdoctor ® 5

    Appendix B: Software B.3 SuperDoctor ® The Supermicro SuperDoctor 5 is a program that functions in a command-line or web-based ® interface for Windows and Linux operating systems. The program monitors such system health information as CPU temperature, system voltages, system power consumption, fan speed, and provides alerts via email or Simple Network Management Protocol (SNMP).

  • Page 180: Bmc

    When logging in to the BMC for the first time, please use the unique password provided by Supermicro to log in. You can change the unique password to a username and password of your choice for subsequent logins.

  • Page 181: Appendix C Standardized Warning Statements

    The following statements are industry standard warnings, provided to warn the user of situations where a potential bodily injury may occur. Should you have questions or experience difficulty, contact Supermicro's Technical Support department for assistance. Only certified technicians should attempt to install or configure components.
  • Page 182 Super X12DPD-A6M25 User's Manual Attention Danger d'explosion si la pile n'est pas remplacée correctement. Ne la remplacer que par une pile de type semblable ou équivalent, recommandée par le fabricant. Jeter les piles usagées conformément aux instructions du fabricant. ¡Advertencia! Existe peligro de explosión si la batería se reemplaza de manera incorrecta.
  • Page 183 Appendix C: Standardized Warning Statements Product Disposal Warning! Ultimate disposal of this product should be handled according to all national laws and regulations. 製品の廃棄 この製品を廃棄処分する場合、 国の関係する全ての法律 ・ 条例に従い処理する必要があります。 警告 本产品的废弃处理应根据所有国家的法律和规章进行。 警告 本產品的廢棄處理應根據所有國家的法律和規章進行。 Warnung Die Entsorgung dieses Produkts sollte gemäß allen Bestimmungen und Gesetzen des Landes erfolgen.

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