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Supermicro X12DPG-AR User Manual

Supermicro X12DPG-AR User Manual

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X12DPG-AR
USER'S MANUAL
Revision 1.0b

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  • Page 1 X12DPG-AR USER'S MANUAL Revision 1.0b...
  • Page 2 State of California, USA. The State of California, County of Santa Clara shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for all claims will not exceed the price paid for the hardware product.
  • Page 3 SATA3 connections, six PCIe 4.0 x16 slots, two PCIe 4.0 x8 slots, an AIOM slot, and two PCIe M.2 ports. It also offers the most advanced data protection capability that encompasses TPM (Trusted Platform Module) and RoT (Root of Trust) support. The X12DPG-AR is optimized for high-performance/high-end computing (HPC) platforms. Thus it is ideal for artificial intelligence and deep learning applications.
  • Page 4 Super X12DPG-AR User's Manual Contacting Supermicro Headquarters Address: Super Micro Computer, Inc. 980 Rock Ave. San Jose, CA 95131 U.S.A. Tel: +1 (408) 503-8000 Fax: +1 (408) 503-8008 Email: marketing@supermicro.com (General Information) Sales-USA@supermicro.com (Sales Inquiries) Government_Sales-USA@supermicro.com (Gov. Sales Inquiries) support@supermicro.com (Technical Support) RMA@supermicro.com (RMA Support)

  • Page 5: Table Of Contents

    Preface Table of Contents Chapter 1 Introduction 1.1 Checklist ..........................7 1.2 Processor and Chipset Overview ..................18 1.3 Special Features ........................19 1.4 System Health Monitoring ....................19 1.5 ACPI Features ........................20 1.6 Power Supply ........................20 1.7 Intel® Optane™ Persistent Memory (PMem) 200 Series Overview ........21 Chapter 2 Installation 2.1 Static-Sensitive Devices .....................22 2.2 Processor and Heatsink Installation ...................23...
  • Page 6 Super X12DPG-AR User's Manual Appendix A BIOS POST Codes A.1 BIOS POST Codes ......................175 Appendix B Software B.1 Microsoft Windows OS Installation ...................176 B.2 Driver Installation ......................178 B.3 SuperDoctor 5 .........................179 ® B.4 BMC ..........................180 B.5 Logging into the BMC (Baseboard Management Controller) ...........180...

  • Page 7: Chapter 1 Introduction

    Chapter 1 Introduction Congratulations on purchasing your computer motherboard from an industry leader. Supermicro motherboards are designed to provide you with the highest standards in quality and performance. 1.1 Checklist This motherboard was designed to be used in an SMCI-proprietary chassis only as a part of an integrated, complete system solution.
  • Page 8 Super X12DPG-AR User's Manual X12DPG-AR Motherboard Image Note: All graphics shown in this manual were based upon the latest PCB revision available at the time of publication of the manual. The motherboard you received may or may not look exactly the same as the graphics shown in this manual.
  • Page 9 LEDM1 JVGA1 AIOM CPU1 PCI-E 4.0 X8 JAIOM1 JRK1 JNCSI1 JTPM1 JBT1 JPWR_RISER1 CPU1 JSTBY1 JGPU2B BMC CODE BAR CODE DESIGNED IN USA JPW2 X12DPG-AR REV:1.01 Ba�ery CPU2 JFP1 FANF JPW3 FAN3 JHDD_PWR1 JHDD_PWR2 JPW4 BIOS LICENSE X12DPG-AR Motherboard Layout...
  • Page 10 Super X12DPG-AR User's Manual Quick Reference BMC_LAN1 JUIDB1 USB0/1 JUIDB1 JUSB1 COM1 USB0/1 (3.0) BMC_LAN1 LEDM1 LEDM1 JVGA1 JVGA1 JTPM1 M.2 Slot (JM2) JNCSI1 CMOS Clear JGPU1 AIOM AIOM CPU1 PCI-E 4.0 X8 JAIOM1 JRIO1 JRK1 JNCSI1 JTPM1 VROC (JRK1)
  • Page 11 Chapter 1: Introduction Notes: • Chapter 2 for detailed information on jumpers, I/O ports, and JFP1 front panel con- nections. • " " indicates the location of Pin 1. • Jumpers/LED indicators not indicated are used for testing only. • Use only the correct type of onboard CMOS battery as specified by the manufacturer.
  • Page 12 Solid Blue: Unit Identified LEDM1 BMC Heartbeat LED Blinking Green: BMC Normal (Active) Connector Description AIOM (JAIOM1) Supermicro® Advanced I/O Module (AIOM) slot Battery (BT1) Onboard CMOS battery FAN1/2/3/4/A/B/C/E/F CPU/System fan headers COM1 (JCOM1) Serial port header for front access I-SATA0~3 (JS1) Intel®...
  • Page 13 Network Interface Card Configuration User's Guide posted on our website under the link: http://www.supermicro.com/support/manuals/. Note 2: For detailed instructions on how to VROC RAID settings, please refer to the VROC RAID Configuration User's Guide posted on the web page under the link: http:// www.supermicro.com/support/manuals/.
  • Page 14 Super X12DPG-AR User's Manual Motherboard Features Motherboard Features • Supports two 3rd Gen Intel Xeon Scalable Processors (Socket P+) with up to 40 CPU cores per CPU and a thermal design power of up to 270W Memory • Supports up to 4TB 3DS LRDIMM/LRDIMM/3DS RDIMM/RDIMM DDR4 (288-pin) ECC memory with speeds of 3200/2933/2666 MHz in 16 memory slots and up to 4TB Intel Optane PMem 200 Series with speeds of up to 3200 MHz Note 1: Intel®...
  • Page 15 Chapter 1: Introduction Motherboard Features BIOS • 256Mb AMI BIOS SPI Flash BIOS ® • ACPI 6.0, Plug and Play (PnP), BIOS rescue hot-key, riser card auto detection support, and SMBIOS 3.0 or later Power Management • ACPI power management •...
  • Page 16 Note 1: The CPU maximum thermal design power (TDP) is subject to chassis and heatsink cooling restrictions. For proper thermal management, please check the chas- sis and heatsink specifications. Note 2: For BMC configuration instructions, please refer to the Embedded BMC Con- figuration User's Guide available at http://www.supermicro.com/support/manuals/.
  • Page 17 Chapter 1: Introduction X12DPG-AR CPU1-B1 CPU1-A1 CPU1-D1 CPU1-C1 CPU2-D1 CPU2-A1 CPU1 CPU2 DDR4 DDR4 Lane Reversal PECI:30 CPU1-F1 CPU1-E1 CPU1-H1 CPU1-G1 CPU2-G1 CPU2-H1 CPU2-E1 CPU2-F1 PECI:31 SOCKET ID:0 SOCKET ID:1 DMI3 PCI-E GEN4 X16 LANE REVERSAL PCI-E GEN4 X16 GPU5...

  • Page 18: Processor And Chipset Overview

    1.2 Processor and Chipset Overview Built upon the functionality and capability of the 3rd Gen Intel Xeon Scalable Processors (Socket P+) and the Intel PCH C621A chipset, the X12DPG-AR motherboard increases energy efficiency and system performance for a multitude of applications, such as high performance computing, artificial intelligence (AI), deep learning (DL), big data, and enterprise applications.

  • Page 19: Special Features

    Chapter 1: Introduction 1.3 Special Features Recovery from AC Power Loss The Basic I/O System (BIOS) provides a setting that determines how the system will respond when AC power is lost and then restored to the system. You can choose for the system to remain powered off (in which case you must press the power switch to turn it back on), or for it to automatically return to the power-on state.

  • Page 20: Acpi Features

    It is even more important for processors that have high CPU clock rates where noisy power transmission is present. The X12DPG-AR motherboard accommodates two CRPS PSUs. Although most power supplies generally meet the specifications required by the CPU, some are inadequate. In addition, four 12V 8-pin power connections are also necessary to ensure adequate power supply to the GPUs in the system.

  • Page 21: Intel® Optane™ Persistent Memory (Pmem) 200 Series Overview

    Chapter 1: Introduction 1.7 Intel® Optane™ Persistent Memory (PMem) 200 Series Overview The 3rd Gen Intel Xeon Scalable Processors support Intel Optane PMem 200 Series memory. Intel Optane PMem offers higher capacities than the traditional DDR4 modules. It also provides increased storage capabilities due to data persistence in a DDR4 form factor for higher performance computing platforms with flexible configuration options.

  • Page 22: Chapter 2 Installation

    Super X12DPG-AR User's Manual Chapter 2 Installation 2.1 Static-Sensitive Devices Electrostatic Discharge (ESD) can damage electronic com ponents. To avoid damaging your motherboard, it is important to handle it very carefully. The following measures are generally sufficient to protect your equipment from ESD.

  • Page 23: Processor And Heatsink Installation

    Thermal grease is pre-applied on a new heatsink. No additional thermal grease is needed. • Refer to the Supermicro website for updates on processor and memory support. • All graphics in this manual are for illustrations only. Your components may look different.
  • Page 24 Super X12DPG-AR User's Manual 1. The 3rd Gen Intel Xeon Scalable Processor Processor Top View (3D) CPU Key Pin 1 = Cutout = Pin 1 = CPU Key Processor Top View...
  • Page 25 Chapter 2: Installation 2. The Processor Carrier = Cutout = Pin 1 = CPU Key Carrier Bottom View...
  • Page 26 Super X12DPG-AR User's Manual 3. Heatsink Note: Exercise extreme care when handling the heatsink. Pay attention to the edges of heatsink fins which can be sharp! To avoid damaging the heatsink, please do not apply excessive force on the fins when handling the heatsink.
  • Page 27 Chapter 2: Installation Overview of the CPU Socket The CPU socket is protected by a plastic protective cover. Plastic Protective Cover CPU Socket...
  • Page 28 Super X12DPG-AR User's Manual Overview of the Processor Carrier Assembly The processor carrier assembly contains a 3rd Gen Intel Xeon Scalable processor and a processor carrier. Carefully follow the instructions given in the installation section to place a processor into the carrier to create a processor carrier.
  • Page 29 Chapter 2: Installation Overview of the Processor Heatsink Module The Processor Heatsink Module (PHM) contains a heatsink, a processor carrier, and a 3rd Gen Intel Xeon Scalable processor. 1. Heatsink (with Thermal Grease) 2. Processor Carrier 3. The 3rd Gen Intel Xeon Scalable Processor Bottom View 4.
  • Page 30 Super X12DPG-AR User's Manual Creating the Processor Carrier Assembly The processor carrier assembly contains a 3rd Gen Intel Xeon Scalable processor and a processor carrier. To create the processor carrier assembly, please follow the steps below: Note: Before installation, be sure to follow the instructions given on Page 1 and Page 2 of this chapter to properly prepare yourself for installation.
  • Page 31 Chapter 2: Installation 3. Locate the lever on the CPU socket and press the lever down as shown below. Lever 4. Using Pin 1 as a guide, carefully align the CPU keys (A and B) on the processor against the CPU keys on the carrier (a and b) as shown in the drawing below. 5.
  • Page 32 Super X12DPG-AR User's Manual Creating the Processor Heatsink Module (PHM) After creating the processor carrier assembly, please follow the instructions below to mount the processor carrier into the heatsink to form the processor heatsink module (PHM). Note: If this is a new heatsink, the thermal grease has been pre-applied on the un- derside.
  • Page 33 Chapter 2: Installation Preparing the CPU Socket for Installation This motherboard comes with a plastic protective cover installed on the CPU socket. Remove it from the socket to install the Processor Heatsink Module (PHM). Gently pull up one corner of the plastic protective cover to remove it. 1.
  • Page 34 Super X12DPG-AR User's Manual Preparing to Install the Processor Heatsink Module (PHM) into the CPU Socket After assembling the Processor Heatsink Module (PHM), you are ready to install it into the CPU socket. To ensure the proper installation, please follow the procedures below: 1.
  • Page 35 Chapter 2: Installation Installing the Processor Heatsink Module (PHM) 1. Align peek nut "A", which is next to the triangle (Pin 1) on the heatsink, against threaded fastener "a" on the CPU socket. Then align peek nuts "B", "C", and "D" on the heatsink against threaded fasteners "b", "c", and "d"...
  • Page 36 Super X12DPG-AR User's Manual Removing the Processor Heatsink Module from the CPU Socket Before removing the processor heatsink module (PHM) from the motherboard, unplug the AC power cord from all power supplies after shutting down the system. Then follow the steps below: 1.
  • Page 37 Chapter 2: Installation Removing the Processor Carrier Assembly from the Processor Heatsink Module (PHM) To remove the processor carrier assembly from the PHM, please follow the steps below: 1. Detach four plastic clips (marked a, b, c, and d) on the processor carrier assembly from the four corners of heatsink (marked A, B, C, and D) in the drawings below.
  • Page 38 Super X12DPG-AR User's Manual Removing the Processor from the Processor Carrier Assembly Once you have removed the processor carrier assembly from the PHM, you are ready to remove the processor from the processor carrier by following the steps below. 1. Unlock the lever from its locking position and push the lever upwards to disengage the processor from the processor carrier as shown in the right drawing below.

  • Page 39: Motherboard Installation

    JAIOM1 JRK1 JNCSI1 JTPM1 JBT1 JPWR_RISER1 CPU1 JSTBY1 JGPU2B BMC CODE BAR CODE DESIGNED IN USA JPW2 X12DPG-AR REV:1.01 Ba�ery CPU2 JFP1 FANF JPW3 FAN3 JHDD_PWR1 JHDD_PWR2 JPW4 BIOS LICENSE Location of Mounting Holes Note: 1) To avoid damaging the motherboard and its components, please do not use a force greater than 8 lbf-in on each mounting screw during motherboard installation.
  • Page 40 Super X12DPG-AR User's Manual Installing the Motherboard 1. Install the I/O shield into the back of the chassis, if applicable. 2. Locate the mounting holes on the motherboard. See the previous page for the location. 3. Locate the matching mounting holes on the chassis. Align the mounting holes on the motherboard against the mounting holes on the chassis.

  • Page 41: Memory Support And Installation

    Memory Support The X12DPG-AR supports up to 4TB 3DS LRDIMM/LRDIMM/3DS RDIMM/RDIMM DDR4 (288-pin) ECC memory with speeds of 3200/2933/2666 MHz in 16 memory slots and up to 4TB Intel Optane PMem 200 Series with speeds of up to 3200 MHz. (See the notes below.) Note 1: Intel®...
  • Page 42 2 CPUs & 14 DIMMs CPU1: P1-DIMMA1/P1-DIMME1/P1-DIMMC1/P1-DIMMG1/P1-DIMMB1/P1-DIMMF1/P1-DIMMD1/P1-DIMMH1 CPU2: P2-DIMMA1/P2-DIMME1/P2-DIMMC1/P2-DIMMG1/P2-DIMMB1/P2-DIMMF1 2 CPUs & 16 DIMMs (Note) CPU1: P1-DIMMA1/P1-DIMME1/P1-DIMMC1/P1-DIMMG1/P1-DIMMB1/P1-DIMMF1/P1-DIMMD1/P1-DIMMH1 CPU2: P2-DIMMA1/P2-DIMME1/P2-DIMMC1/P2-DIMMG1/P2-DIMMB1/P2-DIMMF1/P2-DIMMD1/P2-DIMMH1 Note: This memory configuration is recommended by Supermicro for optimal memory performance. Please use this configuration to maximize your memory performance.
  • Page 43 Chapter 2: Installation Intel Optane PMem 200 Series Memory Population Table Note: Intel® Optane™ Persistent Memory (PMem) 200 Series are supported by the 3rd Gen Intel Xeon Scalable (83xx/63xx/53xx/4314 Series) Processors. PMem 200 Series Population Table for X12DP 16-DIMM Motherboards (within 1 CPU socket) DDR4+PMem Mode AD Interleave...
  • Page 44 Super X12DPG-AR User's Manual DIMM Installation JUIDB1 JUSB1 USB0/1 (3.0) BMC_LAN1 1. Insert the desired number of DIMMs LEDM1 into the memory slots based on the JVGA1 recommended DIMM population table on AIOM CPU1 PCI-E 4.0 X8 JAIOM1 JRK1 JNCSI1 JTPM1 pg.
  • Page 45 Chapter 2: Installation 5. Push both ends of the module straight down into the slot until the module snaps into place. Push both ends straight down into the memory slot. 6. Press the release tabs to the lock positions to secure the DIMM module into the slot. DIMM Removal Press both release tabs on the ends of the DIMM module to unlock it.

  • Page 46: Rear I/O Ports

    Super X12DPG-AR User's Manual 2.5 Rear I/O Ports See Figure 2-1 below for the locations and descriptions of the various I/O ports on the rear of the motherboard. JUIDB1 JUSB1 USB0/1 (3.0) BMC_LAN1 LEDM1 JVGA1 AIOM CPU1 PCI-E 4.0 X8...
  • Page 47 BMC_LAN1 LEDM1 1. BMC_LAN JVGA1 AIOM CPU1 PCI-E 4.0 X8 JAIOM1 JRK1 JNCSI1 JTPM1 JBT1 JPWR_RISER1 CPU1 JSTBY1 JGPU2B BMC CODE BAR CODE DESIGNED IN USA JPW2 X12DPG-AR REV:1.01 Ba�ery CPU2 JFP1 FANF JPW3 FAN3 JHDD_PWR1 JHDD_PWR2 JPW4 BIOS LICENSE...
  • Page 48 Super X12DPG-AR User's Manual Universal Serial Bus (USB) Ports There are two USB 3.0 ports (USB0/1) located on the I/O back panel. The motherboard also has a Front-accessible USB 2.0 header located at J32 (USB2/3). J32 supports two USB connections.

  • Page 49: Front Control Panel

    JFP1 contains header pins for various buttons and indicators that are normally located on a control panel at the front of the chassis. These connectors are designed specifically for use with a Supermicro chassis. See the figure below for the descriptions of the front control panel buttons and LED indicators.
  • Page 50 Super X12DPG-AR User's Manual Front Control Panel LEDs Front Control Panel (JFP1) LED Indicators Event Power (LED1) HDD (LED2) LAN (LED3/4) UID (LED5) Information (LED5) Power Fail (LED6) Power On Solid On HDD Activity Blinking NIC Activity Blinking Overheat Solid On...
  • Page 51 FP PWR LED HDD LED CPU1 P3V3_STBY FP PWR LED JSTBY1 JGPU2B Ground SDA_SEN BMC CODE BAR CODE DESIGNED IN USA JPW2 SCL_SEN Ground X12DPG-AR REV:1.01 Ba�ery 3.3V CPU2 USB Power JFP1 FANF PWR Fail LED Ground JPW3 FAN3 JHDD_PWR1 JHDD_PWR2 JPW4...
  • Page 52 Super X12DPG-AR User's Manual Power Fail LED The Power Fail LED connection is located on pins 19 of JFP1. When this LED turns solid red, it indicates a power failure. Refer to the table below for pin definitions. UID LED The unit identifier LED connection is located on pins 3 of JFP1.
  • Page 53 Chapter 2: Installation NIC1/NIC2 (LAN1/LAN2) The NIC (Network Interface Controller) LED connection for LAN port 1 is located on pins 6 of JFP1, and LAN port 2 is on pins 5. UID Switch The UID Switch connection is located on pins 2 of JFP1. The UID switch in conjunction with JRU1 is used for a chassis that supports a front UID switch.
  • Page 54 Super X12DPG-AR User's Manual FP Power LED The Front Panel Power LED connection is located on pins 9 of JFP1. JFP1 1. FP PWR LED Power Button Reset/UID OH/FF LED UID LED NIC2 (Activity) LED NIC1 (Activity) LED FP PWR LED...

  • Page 55: Connectors

    2. JPW2 (Power Connector 2) LEDM1 JVGA1 AIOM CPU1 PCI-E 4.0 X8 JAIOM1 JRK1 JNCSI1 JTPM1 JBT1 JPWR_RISER1 CPU1 JSTBY1 JGPU2B BMC CODE BAR CODE DESIGNED IN USA JPW2 X12DPG-AR REV:1.01 Ba�ery CPU2 JFP1 FANF JPW3 FAN3 JHDD_PWR1 JHDD_PWR2 JPW4 BIOS LICENSE...
  • Page 56 Super X12DPG-AR User's Manual 8-Pin GPU Power Connectors Four 8-pin 12V power connectors are located at (JPW3-6) on the motherboard to provide power to GPU devices. Refer to the table below for pin definitions. 12V 8-pin Power Pin Definitions Pin#...
  • Page 57 1. JPWR_RISER1 AIOM CPU1 PCI-E 4.0 X8 JAIOM1 JRK1 JNCSI1 2. JHDD_PWR1 JTPM1 JBT1 JPWR_RISER1 3. JHDD_PWR2 CPU1 JSTBY1 JGPU2B BMC CODE BAR CODE DESIGNED IN USA JPW2 X12DPG-AR REV:1.01 Ba�ery CPU2 JFP1 FANF JPW3 FAN3 JHDD_PWR1 JHDD_PWR2 JPW4 BIOS LICENSE...
  • Page 58 Super X12DPG-AR User's Manual Headers Fan Headers There are one 6-pin fan header (FANC) and eight 4-pin fan headers (FAN1/2/3/4/A/B/E/F) on the motherboard. All these fan headers are backwards compatible with the traditional 4-pin fans. However, fan speed control is available by Thermal Management via the BMC interface.
  • Page 59 JVGA1 AIOM CPU1 PCI-E 4.0 X8 JAIOM1 JRK1 JNCSI1 JTPM1 JBT1 JPWR_RISER1 1. VGA Header (JVGA1) CPU1 JSTBY1 JGPU2B BMC CODE BAR CODE DESIGNED IN USA JPW2 X12DPG-AR REV:1.01 Ba�ery CPU2 JFP1 FANF JPW3 FAN3 JHDD_PWR1 JHDD_PWR2 JPW4 BIOS LICENSE...
  • Page 60 Super X12DPG-AR User's Manual BMC External I C Header A System Management Bus header for BMC (Baseboard Management Controller) is located at JIPMB1. Connect the appropriate cable here to use the IPMB I C connection on your system. Refer to the table below for pin definitions.
  • Page 61 JVGA1 1. NCSI header (JNCSI1) AIOM CPU1 PCI-E 4.0 X8 JAIOM1 JRK1 JNCSI1 JTPM1 JBT1 JPWR_RISER1 CPU1 JSTBY1 JGPU2B BMC CODE BAR CODE DESIGNED IN USA JPW2 X12DPG-AR REV:1.01 Ba�ery CPU2 JFP1 FANF JPW3 FAN3 JHDD_PWR1 JHDD_PWR2 JPW4 BIOS LICENSE...
  • Page 62 Super X12DPG-AR User's Manual Universal Serial Bus (USB) Ports The motherboard has a USB 2.0 header J32 (USB2/3). This header supports two USB connections. J32 can be used to provide front-side USB access with a cable (not included). Front Panel USB 3/4 (2.0)
  • Page 63 Port 80 connection. Use this header to enhance system performance and data security. Refer to the table below for pin definitions. Please go to the following link for more information on the TPM: http://www.supermicro.com/manuals/other/TPM.pdf. Trusted Platform Module Header Pin Definitions...
  • Page 64 Super X12DPG-AR User's Manual Standby Power Connectors A 3-pin 12V power connector is located at (JSTBY1). Refer to the motherboard layout below for the location. You must have a card with a Standby Power connector and a cable to use this feature.
  • Page 65 JVGA1 AIOM CPU1 PCI-E 4.0 X8 JAIOM1 JRK1 JNCSI1 JTPM1 JBT1 1. Chassis Intrusion (JL1) JPWR_RISER1 CPU1 JSTBY1 JGPU2B BMC CODE BAR CODE DESIGNED IN USA JPW2 X12DPG-AR REV:1.01 Ba�ery CPU2 JFP1 FANF JPW3 FAN3 JHDD_PWR1 JHDD_PWR2 JPW4 BIOS LICENSE...
  • Page 66 Super X12DPG-AR User's Manual VROC RAID Key Header A VROC RAID Key header is located at JRK1 on the motherboard. Install a VROC RAID Key on JRK1 for NVMe RAID support as shown in the illustration below. Please refer to the layout below for the location of JRK1.
  • Page 67 M.2 Slot The X12DPG-AR motherboard has PCIe M.2 support located at JM2. M.2 was formerly known as Next Generation Form Factor (NGFF) and serves to replace mini PCIe. M.2 allows for a variety of card sizes, increased functionality, and spatial efficiency. The M.2 socket from the AOC supports PCIe 3.0 x4x4 SSD cards in the 2280 and 22110 form factors.
  • Page 68 Super X12DPG-AR User's Manual NVMe Connectors Two NVMe connectors (JNVME1, JNVME2) provide onboard NVMe connections. Use these NVMe connectors to attach high-speed PCIe storage devices. Note: When installing an NVMe device on a motherboard, please be sure to connect the first NVMe port first (JNVME1) for your system to work properly.

  • Page 69: Jumper Settings

    Chapter 2: Installation 2.8 Jumper Settings How Jumpers Work To modify the operation of the motherboard, jumpers can be used to choose between optional settings. Jumpers create shorts between two pins to change the function of the connector. Pin 1 is identified with a square solder pad on the printed circuit board. See the diagram below for an example of jumping pins 1 and 2.

  • Page 70: Led Indicators

    Super X12DPG-AR User's Manual 2.9 LED Indicators BMC_LAN LEDs An BMC_LAN is located on the rear I/O panel. The LED on the right indicates activity, and the LED on the left indicates the speed of the connection. Refer to the table below for more information.
  • Page 71 1. Unit Identifier LED (LE6) LEDM1 JVGA1 AIOM CPU1 PCI-E 4.0 X8 JAIOM1 JRK1 JNCSI1 JTPM1 JBT1 JPWR_RISER1 CPU1 JSTBY1 JGPU2B BMC CODE BAR CODE DESIGNED IN USA JPW2 X12DPG-AR REV:1.01 Ba�ery CPU2 JFP1 FANF JPW3 FAN3 JHDD_PWR1 JHDD_PWR2 JPW4 BIOS LICENSE...
  • Page 72 Super X12DPG-AR User's Manual Onboard Power LED The Onboard Power LED is located at LE3 on the motherboard. When this LED is on, the system power is on. Be sure to turn off the system power and unplug the power cord before removing or installing components.
  • Page 73 1. BMC Heartbeat LED LEDM1 JVGA1 AIOM CPU1 PCI-E 4.0 X8 JAIOM1 JRK1 JNCSI1 JTPM1 JBT1 JPWR_RISER1 CPU1 JSTBY1 JGPU2B BMC CODE BAR CODE DESIGNED IN USA JPW2 X12DPG-AR REV:1.01 Ba�ery CPU2 JFP1 FANF JPW3 FAN3 JHDD_PWR1 JHDD_PWR2 JPW4 BIOS LICENSE...

  • Page 74: Chapter 3 Troubleshooting

    Super X12DPG-AR User's Manual Chapter 3 Troubleshooting 3.1 Troubleshooting Procedures Use the following procedures to troubleshoot your system. If you have followed all of the procedures below and still need assistance, refer to the ‘Technical Support Procedures’ and/ or ‘Returning Merchandise for Service’ section(s) in this chapter. Always disconnect the AC power cord before adding, changing or installing any non hot-swap hardware components.
  • Page 75 Chapter 3: Troubleshooting No Video 1. If the power is on, but you do not have video, remove all add-on cards and cables. 2. Remove all memory modules and turn on the system (if the alarm is on, check the specs of memory modules, reset the memory, or try a different one).
  • Page 76 Super X12DPG-AR User's Manual When the System Becomes Unstable A. If the system becomes unstable during or after OS installation, check the following: 1. CPU/BIOS support: Make sure that your CPU is supported and that you have the latest BIOS installed in your system.

  • Page 77: Technical Support Procedures

    Before contacting Technical Support, please take the following steps. Also, please note that as a motherboard manufacturer, Supermicro also sells motherboards through its channels, so it is best to first check with your distributor or reseller for troubleshooting services. They should know of any possible problems with the specific system configuration that was sold to you.

  • Page 78: Frequently Asked Questions

    BIOS revision to make sure that it is newer than your BIOS before downloading. Note: The SPI BIOS chip used on this motherboard cannot be removed. Send your motherboard back to our RMA Department at Supermicro for repair. For BIOS Recovery instructions, please refer to the AMI BIOS Recovery Instructions posted at http://www.

  • Page 79: Battery Removal And Installation

    Chapter 3: Troubleshooting 3.4 Battery Removal and Installation Battery Removal To remove the onboard battery, follow the steps below: 1. Power off your system and unplug your power cable. 2. Locate the onboard battery as shown below. 3. Using a tool such as a pen or a small screwdriver, push the battery lock outwards to unlock it.

  • Page 80: Returning Merchandise For Service

    Super X12DPG-AR User's Manual 3.5 Returning Merchandise for Service A receipt or copy of your invoice marked with the date of purchase is required before any warranty service will be rendered. You can obtain service by calling your vendor for a Returned Merchandise Authorization (RMA) number.

  • Page 81: Chapter 4 Uefi Bios

    Chapter 4: BIOS Chapter 4 UEFI BIOS 4.1 Introduction This chapter describes the AMIBIOS™ Setup utility for the motherboard. The BIOS is stored on a chip and can be easily upgraded using a flash program. Note: Due to periodic changes to the BIOS, some settings may have been added or deleted and might not yet be recorded in this manual.

  • Page 82: Main Setup

    Super X12DPG-AR User's Manual 4.2 Main Setup When you first enter the AMI BIOS setup utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab on the top of the screen.
  • Page 83 Chapter 4: BIOS CPLD Version This item displays the Complex Programmable Logic Device version. Memory Information Total Memory This item displays the total size of memory available in the system.

  • Page 84: Advanced Setup Configurations

    Super X12DPG-AR User's Manual 4.3 Advanced Setup Configurations Use the arrow keys to select the Advanced menu and press <Enter> to access the submenu items: Warning: Take caution when changing the Advanced settings. An incorrect value, a very high DRAM frequency, or an incorrect DRAM timing setting may make the system unstable. When this occurs, revert to default manufacturer settings.
  • Page 85 Chapter 4: BIOS Bootup NumLock State Use this feature to set the Power-on state for the <Numlock> key. The options are On and Off. Wait For 'F1' If Error Select Enabled to force the system to wait until the <F1> key is pressed if an error occurs. The options are Disabled and Enabled.
  • Page 86 Super X12DPG-AR User's Manual Power Configuration Watch Dog Function Select Enabled to allow the Watch Dog timer to reboot the system when it is inactive for more than 5 minutes. The options are Disabled and Enabled. If this feature is set to Enabled, the following feature will display: Watch Dog Action (Available when "Watch Dog Function"...
  • Page 87 Chapter 4: BIOS CPU Configuration  Warning: Setting the wrong values in the following sections may cause the system to malfunc- tion. The following CPU information will display: • Processor BSP Revision • Processor Socket • Processor ID • Processor Frequency •...
  • Page 88 Super X12DPG-AR User's Manual CPU1 Core Disable Bitmap/CPU2 Core Disable Bitmap  The following features will display: Available Bitmap: The available Bitmap will be displayed. Core Disable Bitmap (Hex) Enter 0 to enable all CPU cores. Enter FFFFFFFFFFF to disable all CPU cores. Please note that at least one core per CPU must be enabled.
  • Page 89 Select Enable to enable Intel Trusted Execution Technology (TXT) support to enhance system security and data integrity. The options are Disable and Enable. Note: For more information on TPM, please visit our website at http://www.supermicro. com/manuals/other. VMX (Not Available when "Enable Intel® TXT" is set to Enable)
  • Page 90 Super X12DPG-AR User's Manual Advanced Power Management Configuration Power Technology Select Energy Efficient to support power-saving mode. Select Custom to customize system power settings. Select Disabled to disable power-saving settings. The options are Disable, Energy Efficient, and Custom. Power Performance Tuning (Available when "Power Technology" is set to Custom) Select BIOS to allow the system BIOS to configure the Power-Performance Tuning Bias setting.
  • Page 91 Chapter 4: BIOS CPU P State Control (Available when "Power Technology" is set  to Custom) SpeedStep (P-States) EIST (Enhanced Intel SpeedStep Technology) allows the system to automatically adjust processor voltage and core frequency for power consumption and heat dissipation reduction. Please refer to Intel’s website for detailed information.
  • Page 92 Super X12DPG-AR User's Manual Hardware PM State Control  Hardware P-States This feature allows the user to select between OS and hardware-controlled P-states. Selecting Native Mode allows the OS to choose a P-state. Selecting Out of Band Mode allows the hardware to autonomously choose a P-state without OS guidance. Selecting Native Mode with No Legacy Support functions as Native Mode with no support for older hardware.
  • Page 93 Chapter 4: BIOS Package C State Control Package C State Use this feature to optimize and reduce CPU package power consumption in the idle mode. Please note that the changes you've made in this setting will affect all CPU cores or the circuits of the entire system.
  • Page 94 Super X12DPG-AR User's Manual Chipset Configuration  Warning: Setting the wrong values in the following items may cause the system to malfunction. North Bridge  This feature allows the user to configure Intel North Bridge parameters. Uncore Configuration  This section allows the user to configure the following Uncore settings: •...
  • Page 95 Chapter 4: BIOS Degrade Precedence Use this feature to select the degrading precedence option for Ultra Path Interconnect (UPI) connections. Select Topology Precedent to degrade UPI features if the system options are in conflict. Select Feature Precedent to degrade UPI topology if system options are in conflict.
  • Page 96 Super X12DPG-AR User's Manual IO Directory Cache (IODC) Select Enable for the IODC (I/O Directory Cache) to generate snoops instead of generating memory lockups for remote IIO (InvIToM) and/or WCiLF (Cores). Select Auto for the IODC to generate snoops (instead of memory lockups) for WCiLF (Cores). The options are Disable, Auto, Enable for Remote InvItoM Hybrid Push, InvItoM AllocFlow, Enable for Remote InvItoM Hybrid AllocNonAlloc, and Enable for Remote InvItoM and Remote WViLF.
  • Page 97 Chapter 4: BIOS LLC Dead Line Alloc Select Enable to opportunistically fill the deadlines in the LLC. The options are Disable, Enable, and Auto. Memory Configuration STEP DRAM Test Select Enable for Samsung Test BIOS and Enhanced Post Package Repair (PPR) support. The options are Disable and Enable.
  • Page 98 Super X12DPG-AR User's Manual Data Scrambling for PMem (Available when "Enabled ADR" is set to Enable) Select Enable to enable data scrambling for Intel Persistent Optane DIMM modules to enhance memory data security. The options are Disable and Enable. Legacy ADR Mode (Available when "Enabled ADR" is set to Enable) Select Enable to support Legacy ADR (Async DIMM Module Self-Refresh) mode to enhance memory performance.
  • Page 99 Chapter 4: BIOS Enable Pcode WA (Workaround) for SAI (Security Attribute of the Initiator) PG (Policy Group) Pcode, a register transfer language designed for reverse engineering, translates individual processor instructions into a sequence of Pcode operations in order to facilitate the construction of data-flow graphs and dissembling of processor instructions for machine application.
  • Page 100 Super X12DPG-AR User's Manual IIO Configuration  CPU1 Configuration/CPU2 Configuration  IOU0 (IIO PCIe Port 1) Use this feature to configure the PCIe Bifurcation setting for a PCIe port specified by the user. The options are Auto, x4x4x4x4, x4x4x8, x8x4x4, x8x8, and x16.
  • Page 101 Chapter 4: BIOS Intel® VT for Directed I/O (VT-d) Intel® VT for Directed I/O Select Yes to use the Intel Virtualization Technology support for Direct I/O VT-d by reporting the I/O device assignments to the VMM (Virtual Machine Monitor) through the DMAR ACPI tables.
  • Page 102 Super X12DPG-AR User's Manual P2P Completion Redirect (When "PCIe ACSCTL" is set to Enable) Select Enable to allow the system to determine when the component redirects peer-to-peer completions upstream. The options are Disable and Enable. Upstream Forwarding Enable (When "PCIe ACSCTL" is set to Enable) Select Enable to enable the component to forward upstream any requests and completions it received from another component in the lower hierarchy.
  • Page 103 Chapter 4: BIOS VMD Port 2A/VMD Port 2B/VMD Port 2C/VMD Port 2D Select Enable to enable Intel Volume Management Device Technology support for the root port specified. The options are Disable and Enable. Hot Plug Capable Select Enable to enable Hot Plug support for the root ports specified by the user, which will allow the user to change the devices on those root ports without shutting down the system.
  • Page 104 Super X12DPG-AR User's Manual P1_NVME0/P1_NVME1/P1_M.2_0/P1_M.2_1 Select Enable to enable Intel Volume Management Device Technology support for the root port specified. The options are Disable and Enable. Hot Plug Capable Select Enable to enable Hot Plug support for the root ports specified by the user, which will allow the user to change the devices on those root ports without shutting down the system.
  • Page 105 Chapter 4: BIOS VMD Port 2A/VMD Port 2B/VMD Port 2C/VMD Port 2D Select Enable to enable Intel Volume Management Device Technology support for the root port specified. The options are Disable and Enable. Hot Plug Capable Select Enable to enable Hot Plug support for the root ports specified by the user, which will allow the user to change the devices on those root ports without shutting down the system.
  • Page 106 Super X12DPG-AR User's Manual VMD Port 5A/VMD Port 5B/ Select Enable to enable Intel Volume Management Device Technology support for the root port specified. The options are Disable and Enable. Hot Plug Capable Select Enable to enable Hot Plug support for the root ports specified by the user, which will allow the user to change the devices on those root ports without shutting down the system.
  • Page 107 Chapter 4: BIOS South Bridge The following USB information will display: • USB Module Version • USB Devices Legacy USB Support Select Enabled to support onboard legacy USB devices. Select Auto to disable legacy support if there are no legacy USB devices present. Select Disable to have all USB devices available for EFI applications only.
  • Page 108 Super X12DPG-AR User's Manual Server ME Configuration  The following General ME Configuration will display: • General ME Configuration • Oper. Firmware Version • Backup Firmware Version • Recovery Firmware Version • ME Firmware Status #1 • ME Firmware Status #2 •...
  • Page 109 Chapter 4: BIOS SATA Configuration  When this submenu is selected, the AMI BIOS automatically detects the presence of the SATA devices that are supported by the Intel PCH chip and displays the following features: SATA Controller This feature enables or disables the onboard SATA controller supported by the Intel PCH chip.
  • Page 110 Super X12DPG-AR User's Manual SATA RAID Option ROM/UEFI Driver (Available when "Configure SATA as" is set to RAID) Select EFI to load the EFI driver for system boot. Select Legacy to load a legacy driver for system boot. The options are Disable, EFI, and Legacy.
  • Page 111 Chapter 4: BIOS sSATA Configuration  sSATA Controller This feature enables or disables the onboard sSATA controller supported by the Intel PCH. The options are Enable and Disable. Configure sSATA as Select AHCI to configure an sSATA drive specified by the user as an AHCI drive. Select RAID to configure an sSATA drive specified by the user as a RAID drive.
  • Page 112 Super X12DPG-AR User's Manual sSATA RAID Option ROM/UEFI Driver (Available when "Configure sSATA as" is set to RAID) Select EFI to load the EFI driver for system boot. Select Legacy to load a legacy driver for system boot. The options are Disable, EFI, and Legacy.
  • Page 113 Chapter 4: BIOS PCIe/PCI/PnP Configuration  The following PCI information will be displayed: • PCI Bus Driver Version Above 4G Decoding (Available if the system supports 64-bit PCI decoding) Select Enabled to decode a PCI device that supports 64-bit in the space above 4G Address. The options are Disabled and Enabled.
  • Page 114 Super X12DPG-AR User's Manual Maximum Read Request Select Auto for the system BIOS to automatically set the maximum size for a read request for a PCIe device to enhance system performance. The options are Auto, 128 Bytes, 256 Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes, and 4096 Bytes.
  • Page 115 Chapter 4: BIOS RSC-G2R-8G4 SLOT 1 PCI-E 4.0 X8 (IN x16) OPROM Select EFI to allow the user to boot the computer using an EFI (Extensible Firmware Interface) device installed on the PCIe slot specified by the user. Select Legacy to boot the computer using a legacy device installed on the PCIe slot specified by the user.
  • Page 116 Super X12DPG-AR User's Manual Super IO Configuration  Serial Port 1 Configuration Serial Port Select Enabled to enable Serial Port 1. The options are Disabled and Enabled. Device Settings (Available when "Serial Port 1" is set to Enabled) This feature displays the base I/O port address and the Interrupt Request address of Serial Port 1.
  • Page 117 Chapter 4: BIOS Change Settings (Available when "Serial Port 2" is set to Enabled) This feature specifies the base I/O port address and the Interrupt Request address of Serial Port 1. Select Auto for the BIOS to automatically assign the base I/O and IRQ address to Serial Port 2.
  • Page 118 Super X12DPG-AR User's Manual Serial Port Console Redirection  COM 1 Console Redirection Select Enabled to enable COM Port 1 for Console Redirection, which will allow a client machine to be connected to a host machine at a remote site for networking. The options are Disabled and Enabled.
  • Page 119 Chapter 4: BIOS Parity A parity bit can be sent along with regular data bits to detect data transmission errors. Select Even if the parity bit is set to 0, and the number of 1's in data bits is even. Select Odd if the parity bit is set to 0, and the number of 1's in data bits is odd.
  • Page 120 Super X12DPG-AR User's Manual Console Redirection (for COM2/SOL) Select Enabled to use the SOL port for Console Redirection. The options are Disabled and Enabled. *If the feature above is set to Enabled, the following items will become available for configuration: Console Redirection Settings (for COM2/SOL) ...
  • Page 121 Chapter 4: BIOS Flow Control Use this feature to set the flow control for Console Redirection to prevent data loss caused by buffer overflow. Send a "Stop" signal to stop sending data when the receiving buffer is full. Send a "Start" signal to start data-sending when the receiving buffer is empty. The options are None and Hardware RTS/CTS.
  • Page 122 Super X12DPG-AR User's Manual Serial Port for Out-of-Band Management/Windows Emergency Management Services (EMS) The feature allows the user to configure Console Redirection settings to support Out-of- Band Serial Port management. Console Redirection (for EMS) Select Enabled to use a COM port specified by the user for EMS Console Redirection. The options are Disabled and Enabled.
  • Page 123 Chapter 4: BIOS ACPI Settings  System ACPI Parameters Use this feature to configure Advanced Configuration and Power Interface (ACPI) power management settings and parameters for your system. NUMA Select Enabled to enable Non-Uniform Memory Access support to enhance system performance.
  • Page 124 Super X12DPG-AR User's Manual Trusted Computing (Available when a TPM device is installed  and detected by the BIOS) When a TPM (Trusted-Platform Module) device is detected in your machine, the following information will display: • TPM 2.0 Device Found: •...
  • Page 125 Chapter 4: BIOS SHA-1 PCR Bank Select Enabled to enable SHA-1 PCR Bank support to enhance system integrity and data security. The options are Enabled and Disabled. SHA256 PCR Bank Select Enabled to enable SHA256 PCR Bank support to enhance system integrity and data security.
  • Page 126 Super X12DPG-AR User's Manual hierarchy while still using the storage hierarchy for TPM applications, permitting the platform software to use the TPM. The options are Enabled and Disabled. PH (Platform Hierarchy) Randomization (for TPM Version 2.0 and above) Select Enabled for Platform Hierarchy Randomization support, which is used only during the platform developmental stage.
  • Page 127 Chapter 4: BIOS Network Configuration  Network Stack Select Enabled to enable PXE (Preboot Execution Environment) or UEFI (Unified Extensible Firmware Interface) for network stack support. The options are Disabled and Enabled. *If "Network Stack" is set to Enabled, the following items will display: IPv4 PXE Support Select Enabled to enable IPv4 PXE boot support.
  • Page 128 Super X12DPG-AR User's Manual Media detect count The user use this feature to select the wait time (in seconds) for the BIOS ROM to detect the presence of a LAN media either via the Internet connection or via a LAN port. The default is 1.
  • Page 129 Chapter 4: BIOS HTTP Boot Configuration  HTTP Boot Policy Use this feature to set the HTTP Boot policy. The options are Apply to all LANs, Apply to Each LAN, and Boot Priority #1 instantly. HTTP Boot Checks Hostname If this feature is set to Enabled, HTTPS Boot will check whether the hostname of TLS certificates matches the hostname provided by the user from the remote server to ensure system security.
  • Page 130 Super X12DPG-AR User's Manual Boot Description Use this feature to enter a boot description, which cannot be longer than 75 characters. Please be sure to enter a boot description; otherwise, the boot option for the URI cannot be created. Boot URI (Uniform Resource Identifier) Enter a Boot URI with 128 characters or shorter.
  • Page 131 Chapter 4: BIOS TLS Authentication Configuration  When this submenu is selected, the following items will display: Server CA Configuration This feature allows the user to configure the client certificate that is to be used by the server. Enroll Certification ...
  • Page 132 Super X12DPG-AR User's Manual Delete Certification  This feature is used to delete the certificate if a certificate has been enrolled in the system. Client Certification Configuration This feature allows the user to configure the client certificate to be used by the server.
  • Page 133 Chapter 4: BIOS SMC PMem Configuration When this submenu is selected, the following items will display: SMCI PMem Information Select this submenu and press <Enter>, the following items will display: • PMem UEFI Drive Version • All Initialized DIMMs • Total Initialized Intel PMem Count •...
  • Page 134 Super X12DPG-AR User's Manual • DIMM [1] FW (Firmware) Version • DIMM [1] Capacity • DIMM [1] APP Direct Capacity • DIMM [1] Unconfigured Capacity • DIMM [1] Reserved Capacity • DIMM [1] Inaccessible Capacity • DIMM [2] Handle •...
  • Page 135 Chapter 4: BIOS • DIMM [3] Serial Number • DIMM [3] FW (Firmware) Version • DIMM [3] Capacity • DIMM [3] APP Direct Capacity • DIMM [3] Unconfigured Capacity • DIMM [3] Reserved Capacity • DIMM [3] Inaccessible Capacity • DIMM [4] Handle •...
  • Page 136 Super X12DPG-AR User's Manual SMCI PMem Settings Select this submenu and press <Enter>, the following items will display: Create Goal Config (Configuration): Persistent: The default setting is [Do Nothing]. Memory Type Reserved [%] All PMem DIMMs have (the) same security state User Security Policy Use this feature to set the User Security Policy.
  • Page 137 Chapter 4: BIOS Intel® Optane™ Persistent Memory Configuration  When you select this submenu and press <Enter>, the following screen will display: Intel® Optane™ Persistent Memory Configuration  When you select this submenu and press <Enter>, the following screen will display: •...
  • Page 138 Super X12DPG-AR User's Manual DIMMs on Socket 0x0000: DIMM IO 0x0010  DIMM IO 0x0110  DIMM IO 0x0210  DIMM IO 0x0310  DIMMs on Socket 0x0001: DIMM IO 0x1010  DIMM IO 0x1110  DIMM IO 0x1210 ...
  • Page 139 Chapter 4: BIOS • Firmware Active API Version: This feature indicates the firmware API version of the PMem module. • Lock State: This feature indicates the lock state of the PMem module. • SVN Downgrade: This feature indicates the status of SVN Downgrade of the PMem module. •...
  • Page 140 Super X12DPG-AR User's Manual Show More Details Select Enabled to view more detailed information on the PMem module. The options are Disabled and Enabled. *If this option is set to Enabled, the following items will display: • Serial Number •...
  • Page 141 Chapter 4: BIOS • Form Factor • Manufacturer ID • Controller Revision ID • IS New • Memory Capacity • APP Direct Capacity • Unconfigured Capacity • Inaccessible Capacity • Reserved Capacity • Avg (Average) Power Limit [mW] • Memory Bandwidth Boost Feature •...
  • Page 142 Super X12DPG-AR User's Manual • ARS Status • Overwrite PMem Module Status • Last Shutdown Time • Average Power Reporting Time Constant [ms] • Viral Policy Enable • Viral State • Thermal Throttle Loss % • Latched Last Shutdown Status •...
  • Page 143 Chapter 4: BIOS • Average Power 12V • Average Power 1.2V • eADR Enable • Previous Power Cycle eADR Enabled • Latch System Shutdown State • Previous Power Cycle Latch System Shutdown State Monitor Health  This submenu displays the following health information on a memory module being monitored. •...
  • Page 144 Super X12DPG-AR User's Manual Update Firmware  Use this feature to select the firmware image to be loaded on the PMem module. After loading the firmware image, please reboot the system and select update for the firmware to take effect. The following items will display: Current Firmware Version This feature displays the current firmware version.
  • Page 145 Chapter 4: BIOS Back to Main Menu  Select this feature and press <Enter> to go back to the Intel® Optane™ Persistent Memory Configuration menu. Configure Data Policy  Use this feature to configure the data policy settings for all onboard PMem modules. Average Power Reporting Time Constant [ms] This feature specified the constant average power reporting time.
  • Page 146 Super X12DPG-AR User's Manual Back to Regions Menu  Back to Provisioning Menu  Back to Main Menu  Select this feature and press <Enter> to go back to the Intel® Optane™ Persistent Memory Configuration menu. Back to Main Menu ...
  • Page 147 Chapter 4: BIOS Create Goal Configuration  DIMM ID  • MemorySize • AppDirect1Size • AppDirect2Size Delete Goal Configuration  Back to Previous Menu  Select this feature and press <Enter> to go back to the previous menu. Back to Main Menu ...
  • Page 148 Super X12DPG-AR User's Manual • Units: Use this feature to change the namespace capacity (in the unit of B, MB, MiB, GB, GiB, TB, and TiB.) • Capacity • Label Version Delete After configuring the settings for the namespace above, click on <delete> to delete the changes you've made on the namespace.
  • Page 149 Chapter 4: BIOS Create Namespace  Back to Namespaces Back to Main Menu  Select this feature and press <Enter> to go back to the Intel® Optane™ Persistent Memory Configuration menu. Total Capacity  This feature allows the user to set the total PMem resource capacity allocated across all segments in the host server.
  • Page 150 Super X12DPG-AR User's Manual Total Memory Capacities • Volatile: This feature specifies Volatile information of the PMem module. • AppDirect: This feature specifies the App. direct capacity of the PMem module. • Cache: This feature specifies the capacity of the cache memory.
  • Page 151 Chapter 4: BIOS Security Diagnostics Select Enabled for the security diagnostics test to be performed on the PMem module. The options are Enabled and Disabled. Execute Tests Select this feature and press <Enter> to execute the selected diagnostic tests. The following items will be displayed: Back to Diagnostics Back to Main Menu...
  • Page 152 Super X12DPG-AR User's Manual Intel® I350 Gigabit Network Connection  Note: The Interface ID "3C:EC:EF:1D:16:50" is for illustration only. It is unique per system. When you select this menu and press <Enter>, the following items will display: NIC Configuration ...
  • Page 153 Chapter 4: BIOS • Factory MAC Address • Alternate MAC Address...
  • Page 154 Super X12DPG-AR User's Manual VLAN Configuration  Note: The Interface ID "MAC:3CECEF1D1650" is for illustration only. It is unique per system. When you select this menu and press <Enter>, the following items will display: Enter Configuration Menu  Create New VLAN This feature allows the user to create a new VLAN.
  • Page 155 Chapter 4: BIOS IPv6 Network Configuration  Note: The Interface ID "MAC:3CECEF1D1650" is for illustration only. It is unique per system. When you select this menu and press <Enter>, the following items will display: Enter Configuration Menu  • Interface Name •...
  • Page 156 Super X12DPG-AR User's Manual IPv4 Network Configuration  Note: The Interface ID "MAC:3CECEF1D1650" is for illustration only. It is unique per system. When you select this menu and press <Enter>, the following items will display: Configured Select Enabled to show whether the network address has been successfully configured or not.
  • Page 157 Chapter 4: BIOS Intel® I350 Gigabit Network Connection  Note: The Interface ID "3C:EC:EF:1D:16:51" is for illustration only. It is unique per system. When you select this menu and press <Enter>, the following items will display: NIC Configuration  Link Speed This feature displays the connection speed of a LAN port specified by the user.
  • Page 158 Super X12DPG-AR User's Manual VLAN Configuration  Note: The Interface ID "MAC:3CECEF1D1651" is for illustration only. It is unique per system. When you select this menu and press <Enter>, the following items will display: Enter Configuration Menu  Create New VLAN This feature allows the user to create a new VLAN.
  • Page 159 Chapter 4: BIOS IPv6 Network Configuration  Note: The Interface ID "MAC:3CECEF1D1651" is for illustration only. It is unique per system. When you select this menu and press <Enter>, the following items will display: Enter Configuration Menu  • Interface Name •...
  • Page 160 Super X12DPG-AR User's Manual IPv4 Network Configuration  Note: The Interface ID "MAC:3CECEF1D1651" is for illustration only. It is unique per system. When you select this menu and press <Enter>, the following items will display: Configured Select Enabled to show whether the network address has been successfully configured or not.

  • Page 161: Event Logs

    Chapter 4: BIOS 4.4 Event Logs Use this feature to configure Event Log settings. Note: After you've made any changes on a setting below, please reboot the system for the changes you've made to take effect. Change SMBIOS Event Log Settings Enabling/Disabling Options SMBIOS Event Log Select Enabled to enable SMBIOS (System Management BIOS) Event Logging during system...
  • Page 162 Super X12DPG-AR User's Manual SMBIOS Event Log Standard Settings Log System Boot Event Select Enabled to log system boot events. The options are Enabled and Disabled. MECI (Multiple Event Count Increment) Enter the increment value for the multiple event counter. Enter a number between 1 to 255.

  • Page 163: Bmc

    Chapter 4: BIOS 4.5 BMC This submenu displays the status of the Baseboard Management Controller (BMC), and allows the user to configure the following BMC settings. • BMC Firmware Revision: This feature indicates the BMC firmware used in your system. •...
  • Page 164 Super X12DPG-AR User's Manual BMC Network Configuration  Update BMC LAN Configuration Select Yes for the BIOS to implement all IP/MAC address changes upon next system boot. The options are No and Yes. ********************************* Configure IPv4 Support ********************************* • BMC LAN Selection: This feature allows the user to select the type of the BMC LAN. The manufacturer default setting is Failover.
  • Page 165 Chapter 4: BIOS • Configuration Address Source Use this feature to select the source of the IPv4 Connection. If Static is selected, you will need to know the IP address of IPv4 connection and enter it to the system manually in the field.

  • Page 166: Security

    Super X12DPG-AR User's Manual 4.6 Security This menu allows the user to configure the following security settings for the system. Administrator Password This feature indicates if an administrator password has been installed. It also allows the user to set the administrator password which is required to enter the BIOS setup utility. The length of the password should be from 3 characters to 20 characters long.
  • Page 167 Note: For detailed instructions on how to configure Secure Boot settings, please refer to the Secure Boot Configuration User's Guide posted on the web page under the link: http://www.supermicro.com/support/manuals/. When you select this submenu and press the <Enter> key, the following items will display:...
  • Page 168 Super X12DPG-AR User's Manual • Secure Mode Secure Boot Select Enabled to use Secure Boot settings. The options are Enabled and Disabled. Secure Boot Mode Use this feature to select the desired secure boot mode for the system. The options are Standard and Custom.
  • Page 169 Chapter 4: BIOS Export Secure Boot Variables  This feature exports the NVRAM contents of Secure Boot variables to a storage device. Enroll EFI Image  This feature specifies which EFI (Extensible Firmware Interface) image should be used for the system when it operates in the Secure Boot mode. Device Guard Ready Remove 'UEFI CA' from DB ...
  • Page 170 Super X12DPG-AR User's Manual Forbidden Signatures  Use this feature to enter and configure a set of values to be used as Forbidden Signatures for the system. These values also indicate sizes, keys numbers, and key sources of the forbidden signatures. Select Update to update your "Forbidden Signatures". Select Append to append your "Forbidden Signatures".

  • Page 171: Boot

    Chapter 4: BIOS 4.7 Boot Use this feature to configure Boot settings. Boot Mode Select Use this feature to select the type of devices from which the system will boot. The options are Legacy, UEFI (Unified Extensible Firmware Interface), and Dual. Note: When the Boot Mode Select feature above is set to Dual, be sure to set all OPROM-related settings to Legacy.
  • Page 172 Super X12DPG-AR User's Manual  Add New Boot Option This feature allows the user to add a boot device to the boot priority list.  Delete Boot Option This feature allows the user to select a boot device to delete from the boot priority list.

  • Page 173: Save & Exit

    Chapter 4: BIOS 4.8 Save & Exit Select the Save & Exit menu from the BIOS setup screen to configure the settings below. Save Options Discard Changes and Exit Select this option to exit from the BIOS setup utility without making any permanent changes to the system configuration and reboot the computer.
  • Page 174 Super X12DPG-AR User's Manual Default Options Restore Optimized Defaults To set this feature, select Restore Optimized Defaults from the Exit menu and press <Enter> to load manufacturer optimized default settings which are intended for maximum system performance but not for maximum stability.

  • Page 175: Appendix A Bios Post Codes

    When BIOS performs the Power On Self Test, it writes checkpoint codes to I/O port 0080h. If the computer cannot complete the boot process, a diagnostic card can be attached to the computer to read I/O port 0080h (Supermicro p/n AOC-LPC80-20). For information on AMI updates, please refer to http://www.ami.com/products/.

  • Page 176: Appendix B Software

    USB/SATA DVD drive, or a USB flash drive, or the BMC KVM console. 2. Retrieve the proper RST/RSTe driver. Go to the Supermicro web page for your motherboard and click on "Download the Latest Drivers and Utilities", select the proper driver, and copy it to a USB flash drive.
  • Page 177 Appendix B: Software 4. During Windows Setup, continue to the dialog where you select the drives on which to install Windows. If the disk you want to use is not listed, click on “Load driver” link at the bottom left corner. To load the driver, browse the USB flash drive for the proper driver files.

  • Page 178: Driver Installation

    The Supermicro website contains drivers and utilities for your system at https://www. supermicro.com/wdl/driver. Some of these must be installed, such as the chipset driver. After accessing the website, go into the CDR_Images (in the parent directory of the above link) and locate the ISO file for your motherboard. Download this file to a USB flash drive or a DVD.

  • Page 179: Superdoctor ® 5

    B.3 SuperDoctor ® The Supermicro SuperDoctor 5 is a program that functions in a command-line or web-based interface for Windows and Linux operating systems. The program monitors such system health information as CPU temperature, system voltages, system power consumption, fan speed, and provides alerts via email or Simple Network Management Protocol (SNMP).

  • Page 180: Bmc

    When logging in to the BMC for the first time, please use the unique password provided by Supermicro to log in. You can change the unique password to a user name and password of your choice for subsequent logins.

  • Page 181: Appendix C Standardized Warning Statements

    The following statements are industry standard warnings, provided to warn the user of situations which have the potential for bodily injury. Should you have questions or experience difficulty, contact Supermicro's Technical Support department for assistance. Only certified technicians should attempt to install or configure components.
  • Page 182 Super X12DPG-AR User's Manual Attention Danger d'explosion si la pile n'est pas remplacée correctement. Ne la remplacer que par une pile de type semblable ou équivalent, recommandée par le fabricant. Jeter les piles usagées conformément aux instructions du fabricant. ¡Advertencia! Existe peligro de explosión si la batería se reemplaza de manera incorrecta.
  • Page 183 Appendix C: Standardized Warning Statements Product Disposal Warning! Ultimate disposal of this product should be handled according to all national laws and regulations. 製品の廃棄 この製品を廃棄処分する場合、 国の関係する全ての法律 ・ 条例に従い処理する必要があります。 警告 本产品的废弃处理应根据所有国家的法律和规章进行。 警告 本產品的廢棄處理應根據所有國家的法律和規章進行。 Warnung Die Entsorgung dieses Produkts sollte gemäß allen Bestimmungen und Gesetzen des Landes erfolgen.

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