Schematics - ZiLOG Z8 Encore 4K Series User Manual

Schematics

The following diagrams provide schematics for the Z8 Encore! 4K Series Development Board.
5
R7
D2
PA6_nT1OUT
1 2
GREEN 100
R8
D3
PA7_T1OUT
1 2
YELL 100
D
R10
D4
PC3_COUT
1 2
10
RED
VCC_33V
VCC_33V
GND
GND
TABLE 1
R12 R13 R16
GPIO none 0 ohm none
Analog 0 ohm none 0 ohm
Supply
C
20 pin footprint
U6
PB1_ANA1
1
PB1/ANA1
PB2_ANA2
2
PB2/ANA2
PB3_ANA3
3
PB3/CLKIN/ANA3
VCC_33V
4
VDD
PA0_T0IN
5
PA0/T0IN/T0OUT/XIN/
PA1_T0OUT
6
PA1/T0OUT/XOUT
GND
7
GND
PA2
8
PA2/DE
PA3_CTS0
9
PA3/CTS0
PA4_RXD0
10
PA4/RXD0
Z8F04xA
Z8F0423
R14 R15
0 0
R18
B
1M
Y1
1 3
1 3
C19 C20
8 MHz
NOTE 2
TABLE 2
Clock Mode R14 R15 R18 C19
Note 2: The 4K does not support an external oscillator even though crystal Y1 is installed.
Internal Only none none none none
A Crystal 0 Ohm 220 Ohm none Yes
Ceramic Res 0 Ohm 0 Ohm none none
External CMOS none none none
(Use PA0_T0IN
pin on JP2)
5
Schematic, Z8 Encore! 4K Series Development Board, Page 1 of 2
UM018501-1004
4
Note 1:
PB6 and PB7 are dual function pins (GPIO or Analog
Supply)
R12, R13, R16, and R17 are zero-ohm jumpers used in
conjuntion with GPIO Control Registers to select
R9
SW2
VCC_33V GND function desired. The development board is shipped
with jumpers configured for Analog Supply.
TEST
U8 is an optional filter that can be used to improve
100K
R11 the quality of the Analog Supply
Table 1 shows the configurations
100
PA2
R12
0
R17 U8
U8
VCC_33V
0 ohm none
1 3
IO IO
none optional
EMI Filter
PB0_ANA0
20
PB0/ANA0
PC3_COUT
19
PC3/COUT/LED SENSE
PC2_ANA6
18
PC2/ANA6/LED
PC1_ANA5
17
PC1ANA5/CINN/LED
PC0_ANA4
16
PC0/ANA4/CINP/LED
DBG
C10
15
DBG
PD0
14
RESET/PD0
PA7_T1OUT
0.001uF
13
PA7/T1OUT
PA6_nT1OUT
12
PA6/T1IN/T1OUT
PA5_TXD0
11
PA5/TXD0
PA3_CTS0
PA4_RXD0
PA5_TXD0
R16 0 R17 0
GND
NOTE 1:
PB0_ANA0 PB1_ANA1
C11
0.001uF
Note 2: The XP supports internal, external crystal, external
C20 Y1
ceramic resonator, external R/C and external CMOS drive clock
modes. R14, R15, R18, C19, C20 and Y1 are used to support
none none
the clock mode selected.
Yes Yes
configured for external 8Mhz ceramic resonator or internal
none Yes clock operation.
Table 2 shows the recommended clock mode configurations.
none none none
4
3
recommended
NOTE 1:
GND
R13
PB6
RESET/TEST2
0
28 pin footprint
U5
PB2_ANA2
1
PB2/ANA2 PB1/ANA1
PB4_ANA7
2
PB4/ANA7 PB0/ANA0
PB5
3
PB5/Vref PC3/COUT/LED
PB3_ANA3
4
PB3/ANA3/CLKIN PC2/ANA6/LED
5
PB6(AVDD) PC1/ANA5/CINN/LED
VCC_33V
6
VDD PC0/ANA4/CINP/LED
PA0_T0IN
7
PA0/T0IN/T0OUTXIN
PA1_T0OUT
8
PA1/T0OUT/XOUT RESET/PD0
GND
9
GND PC7/LED
10
PB7(AGND) PC6/LED
PA2
11
PA2/DE PA7/T1OUT
PA3_CTS0
12
PA3/CTS0 PC5/LED
PA4_RXD0
13
PA4/RXD0 PC4/LED
PA5_TXD0
14
PA5/TXD0 PA6/T1IN/T1OUT
Z8F04xA_28 Z8F0423
PB7
PB2_ANA2 PB3_ANA3 PC0_ANA4 PC1_ANA5 PC2_ANA6
C12 C13 C14 C15 C16
0.001uF 0.001uF 0.001uF 0.001uF 0.001uF
PB0_ANA0
PB1_ANA1
PB2_ANA2
PB3_ANA3
PC0_ANA4
PC1_ANA5
PC2_ANA6
The development board is shipped
PB4_ANA7
3
PRELIMINARY
Z8F04328100KIT Development Kit
2
If Module is plugged onto the Dev Platform the local
RS232 interface is disabled by pin 50 of JP2
connector 2
PB4_ANA7
PC1_ANA5
PB3_ANA3
PB1_ANA1
VCC_33V
PC4
11
PC7
13
PC3_COUT
15
PA6_nT1OUT
17
GND
19
PA7_T1OUT
21
23
25
27
29
31
PA3_CTS0
33
PA4_RXD0
35
37
GND
39
41
SW1 43
R19 10K
PB6
45
PB7
47
49
JP5 51
-RESET
53
1
VCC_33V
55
2
57
VCC_33V
HEADER 2
59
PB1_ANA1
28
PB0_ANA0
27
PC3_COUT
26 connector 1
PC2_ANA6
25
PC1_ANA5
24 for
PC0_ANA4
23
DBG
22 reference
DBG DBG
PD0
21
PC7
20
only
PC6
19
PA7_T1OUT
18
PC5
17
PC4
16
PA6_nT1OUT
15
-TRSTN
-F91_WE
GND
A6
A10
GND
A8
A13
A15
A18
A19
PB4_ANA7 A2
A11
A4
A5
C17 C18
0.001uF 0.001uF
A21
GND
A22
-CS0
-CS2
D1
D3
J2
D5
D7
-MREQ
1 2
GND
3 4
-WR
5 6
-BUSACK
7 8
9 10
11 12
13 14
15 16
HEADER 8X2
Title
XP 4K MDS Processor Module. Schematic.
Size Document Number
B
96C0941-001
Date: Wednesday, February 25, 2004
2
User Manual
11
1
JP2
PC2_ANA6
1 2
PC0_ANA4
3 4
PB2_ANA2
5 6
PB0_ANA0
7 8
GND
9 10
PC5
12
PC6
14
PB5 D
16
PA0_T0IN
18
PA1_T0OUT
20
PA2
22
24
26
PD0
28
GND
30
32
34
PA5_TXD0
36
38
40
42
44
46
GND
48
50
-DIS_232
-DIS_IrDA
52
-DIS_IRDA
54
GND
56
58
60
C
HEADER 30x2/SM
JP1
1 2
3 4
5 6
7 8
VCC_33V
9 10
A0
11 12
A3
13 14
VCC_33V
15 16
A7
17 18
A9
19 20
B
A14
21 22
A16
23 24
25 26 GND
A1
27 28
A12
29 30
A20
31 32
A17
33 34
-DIS_FLASH
35 36
VCC_33V
37 38
A23
39 40
-CS1
41 42
D0
43 44
D2
45 46
D4
47 48
GND
49 50
D6
51 52
-IOREQ
53 54
-RD
55 56
-INSTRD
57 58
-BUSREQ
59 60
HEADER 30x2/SM A
Rev
B
Sheet 1 of 2
1
Schematics