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Soft Reset
Z-80 Reset
Power-Fail Warn
Principles of Operation
3-12
Soft reset suspends all hardware operations in progress and puts the LANIC into
the KERNEL state. waiting for further commands. In this way. most of the
LANIC internal state information is preserved. The microprocessor is not reset
and information pertaining to the RQ entries remains valid. The firmware is
forced to the KERNEL state and communication with the host software is
restricted to the CR and SR only.
The soft reset is typically issued when a LANIC failure has been detected by the
host (e.g., LANIC is unresponsive). The firmware is thus forced to communicate
with the host software. Since self-test has not been performed, diagnostics of
the firmware can take place by issuing the MEMORY_DUMP command.
Soft reset can be initiated by the LANIC or by host software. The LANIC
hardware initiates soft reset by detecting certain system bus errors. These errors
are: system bus timeout, memory parity error. bus parity error, or memory
bounds violation. System software can initiate a soft reset by writing register 14
(ABORT register) on the LANIC with bit 15=1.
The IOCL and INIT commands effect a. HARDRST. but the microprocessor
remains reset. This feature is useful for diagnostics which need to reset the
hardware registers without initiating the selftest sequence. The microprocessor
remains reset until a normal HARDRST in issued.
When the backplane power-fail warn signal (PFW) is active. the LANIC is
prevented from requesting or initiating a system bus master handshake. If the
PFW signal becomes active while the LANIC is requesting. but has not yet been
acknowledged bus master. then the LANIC backs off from requesting the bus
while PFW is active.
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