Smb/Cnv - Clevo W517GU Service Manual

SMB/CNV

5
D
[11]
3.3VA
[11] SMB_DATA
1K_04
1K_04
[18] CNVI_W GR_CLK_DP
[18] CNVI_W GR_CLK_DN
[18] CNVI_W GR_D0P
[18] CNVI_W GR_D0N
1.8VA
[18] CNVI_W GR_D1P
[18] CNVI_W GR_D1N
C [18] CNVI_W T_CLK_DP
D02 CNVI CLOSE TO PCH
[18] CNVI_W T_CLK_DN
R446 20K_04 SOC_GPIO193
[18] CNVI_W T_D0P
[18] CNVI_W T_D0N
[18] CNVI_W T_D1P
[18] CNVI_W T_D1N
[18] CLKIN_XTAL_LCP
[18] XTAL_CLKREQ
[18] CNVI_BRI_DT
[18] CNVI_BRI_RSP
[18] CNVI_RGI_DT
[18] CNVI_RGI_RSP
[18] CNVI_RF_RST#
D02 CLOSE TO CONN
PLACE CLOSE TO SOC
B SOC_CLKIN_XTAL_LCP
R385 C332
Hardware Straps (4)
10K_04
GPIO_62,79,80,85,86,87,89,192,194,196
Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation.
Internal PD 20K CMOS SOC_GPIO62
Internal PD 20K CMOS SOC_GPIO79
SOC_GPIO80
Internal PD 20K CMOS
Internal PD 20K CMOS SOC_GPIO85
SOC_GPIO86
Internal PD 20K CMOS
Internal PD 20K CMOS SOC_GPIO87
Internal PD 20K CMOS SOC_GPIO89
Internal PD 20K CMOS SOC_GPIO192
Internal PD 20K CMOS SOC_GPIO194
Internal PD 20K CMOS SOC_GPIO196
A
GPIO_81,193
Ensure that this strap is pulled HIGH when
RSM_RST_N de-asserts for normal platform operation.
Internal PU 20K CMOS SOC_GPIO81
Internal PU 20K CMOS SOC_GPIO193
5
4 3
U25F
U49
SIO_I2C0_SCL
U51
SIO_I2C0_SDA
U46 LPSS_I2C
SIO_I2C1_SCL
U48
SIO_I2C1_SDA
AA39
SIO_I2C2_SCL
AA41
SIO_I2C2_SDA
R44
SIO_I2C3_SCL
R43
SIO_I2C3_SDA
R49
SIO_I2C4_SCL
R51
SIO_I2C4_SDA
C50
SIO_I2C5_SCL
A50
SIO_I2C5_SDA
C48
SIO_I2C6_SCL
C47
SIO_I2C6_SDA
B47
SIO_I2C7_SCL
C46
SIO_I2C7_SDA
R368 *1K_04 SMB_ALERT# A26
3.3VA SMB_ALERT
B27
SMB_CLK SMB_CLK
C27 LPSS SMBus
SMB_DATA
R376
R378
H29
CNV_WGR_CLK_P
H31
CNV_WGR_CLK
M31
CNV_WGR_D0_P
P31
CNV_WGR_D0
D29
CNV_WGR_D1_P
F29
CNV_WGR_D1
F35
CNV_WT_CLK_P
D35
CNV_WT_CLK
J35
CNV_WT_D0_P
H35
CNV_WT_D0
L31
CNV_WT_D1_P
J31
CNV_WT_D1
FCM1005KF-121T03
R388 SOC_CLKIN_XTAL_LCP J29
CLKIN_XTAL_LCP
R102 0_04 SOC_GPIO196 F19
XTAL_CLKREQ
SOC_GPIO191 H17
R381 33_04
CNV_BRI_DT
R387 33_04 SOC_GPIO192 J17
CNV_BRI_RSP
R383 33_04 SOC_GPIO193 D19
CNV_RGI_DT
SOC_GPIO194
R380 33_04 D17
CNV_RGI_RSP
F17
CNV_RF_RESET
CNVI_W T_RCOMP
R129 150_1%_04 F33
CNV_WT_RCOMP
D02
Enable TXE ROM Bypass
1=enable bypass
0=disable bypass (default)
Internal PD 20K CMOS UART0_TXD
Force DNX FW Load
1=Force
0=Do not force (default)
Internal PD 20K CMOS UART2_TXD
LPC boot BIOS strap
1=boot from LPC
0=do not boot from LPC (default)
Internal PD 20K CMOS SOC_GPIO66 1.8VA
LPC 1.8V/3.3V mode select
1=buffers set to 1.8V mode R106 10K_04
0=buffers set to 3.3V mode (default)
SOC_GPIO83
Internal PD 20K CMOS
Allow SPI as a boot source D02
1=disable
0=enable (default)
Internal PU 20K CMOS SOC_GPIO84 R120 4.7K_1%_04
eSPI Flash Sharing Mode
1=slave attached flash sharing (SAFS);
0=master attached flash sharing (MAFS;default)
Internal PD 20K CMOS SOC_GPIO191
4 3
2
SIO_SPI_0_CLK
LPSS_SPI
SIO_SPI_0_TXD
SIO_SPI_0_RXD
SIO_SPI_0_FS0
SIO_SPI_0_FS1
SIO_SPI_2_CLK
SIO_SPI_2_TXD
SIO_SPI_2_RXD
SIO_SPI_2_FS0
SIO_SPI_2_FS1
SIO_SPI_2_FS2
SIO_UART0_TXD
SIO_UART0_RXD
SIO_UART0_RTS
SIO_UART0_CTS
SIO_UART2_TXD
SIO_UART2_RXD
SIO_UART2_RTS
SIO_UART2_CTS
LPSS_UART
CNVI
6 OF 13
1.8VA 1.8VA
AMI Debug Use
D02
D02
R168 R154
*2.2K_04 *2.2K_04
UART0_TXD
UART2_TXD 4 3 UART1_TXD_Q
R178 *0_04
*MTDK3S6R
Q15B
UART0_RXD 1 6 UART1_RXD_Q
UART2_RXD
R158 *0_04 *MTDK3S6R
Q15A
! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/
Title Title Title
[06] SMB/CNV [06] SMB/CNV [06] SMB/CNV
[7,8,9,19,22,23,24,26] 3.3VA
[3,4,5,7,8,9,11,17,18,19,22,23,24] 1.8VA
Size Size Size Document Number Document Number Document Number
6-71-W51G0-D02 6-71-W51G0-D02 6-71-W51G0-D02
A3 A3 A3 SCHEMATIC1 SCHEMATIC1 SCHEMATIC1
Date: Date: Date: Tuesday, January 30, 2018 Tuesday, January 30, 2018 Tuesday, January 30, 2018
2
Schematic Diagrams
1
M39 SOC_GPIO79
J37 SOC_GPIO83
L39
SOC_GPIO80
L37
J39 SOC_GPIO81
M37 SOC_GPIO84
M33 SOC_GPIO89
P35
D
P33 SOC_GPIO85
SOC_GPIO86
P37
L35 SOC_GPIO87
UART0_TXD
N54
P53 UART0_RXD
N53 SOC_GPIO62
M55
L54 UART2_TXD
M53 UART2_RXD
SOC_GPIO66
K53
L53
Sheet 6 of 31
C
SMB/CNV
B
A
Rev Rev Rev
3.0 3.0 3.0
Sheet Sheet Sheet 6 6 6 of of of 35 35 35
1
SMB/CNV B - 7