)
ad
)
)
D
16
FROM
CH
2
PREAMP
CH
2
GATE
19
FROM
TRI G GER
VI E W
AMP
TRIG
VI E W
GATE
DELAY
LINE
DRI V ER
15
FROM
CH
1
PREAMP
CH
1
GATE
ROM U3605
DELAY
LINE
P3505
FF
U3705
CH
1
SELECT
Q3619
01
o
CH
2
SELECT
A4
Do D1
02
01
ADD
SELECT
A5
03
TRIG
VIEW
SELECT
D2
02
Q3719
TO
VERTI C AL AMPL I F I E R
A6
04
CLK
XY
SELECT
Figure Opt ion 1 0-2 . Sim plified block diagram of gate- cont rol logic .
A7 A2
+5
V
Q3617
Aq
AO
CHOP CLOCK
CHOP
CLOCK GE N E R A T O R
464 and 466 Opt ion 1 0
U3805C
(
ALT
/
CHOP
)
(
ALT
SYNC
PULSE
)
1 753-1 02
5
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