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CIRCUIT DESCRIPTION
Quadruple Oversampling
This LSI incorporates digital filter circuitry for 2 channels,
providing quadruple oversampling outputs for both channels.
The SM5807 consists of two linear-phase FIR filters, each of
which performs double oversampling, connected in two suc-
cessive stages.
The basic configuration is shown in the diagram below. Name-
ly, the input signal sampled at 44.1 kHz is first converted by
the 61-order 1st DF, with double oversampling, into a signal
sampled at 88.2 kHz. The 13-oder 2nd DF converts the input
signal with an 88.2 kHz sampling rate, again by double over-
sampling, and outputs a signal with an 176.4 kHz sampling
rate, which is 4 times oversampled when compared to the 1st
DF input.
1st DF
61-order
double over-
sampling
2nd DF
13-order
double over-
sampling
176.4 kHz
Quadruple oversampling
System Clock
The system clock of the LSI is 192 fs = 8.4672 MHz or 196 fs
= 8.6436 MHz.
Either frequency can be selected by the status of the SCSL pin.
SCSL = H (or Open) ....192 fs (compatible with a 96 fs
system clock)
SCSL
= \ Levsrcssin
Se atuittes 196 fs (compatible with a 98 fs
system clock)
Clock Generator Circuit
Serial Input (data and bit clock)
As the serial input data is input at the positive-going edge of
the serial input bit clock BCK1, the data should be valid by the
positive-going edge of BCK1. After the 16-bit serial data in-
put, the serial data is latched by the internal register based on
the sync clock LRCI. The data should be input in 2's comple-
ment format, with the MSB first.
Start of Operations
All operations are started at the positive-going edge of the sync
clock LRCI.
Serial output (data and bit clock)
As DOUT outputs the L-CH and R-CH serial data alternately,
the output can be converted using only one DAC. In-phase con-
version using two DACs is also available by using some exter-
nal circuitry (2 gates). The data is output in 2's complement
format, with the MSB first.
The serial output bit clock is output from the BCKO terminal.
As the data varies in synchronism with the positive-going edge
of the bit clock, it can be input to the DAC at the negative-
going edge.
BCKO
= 8.4072 MHz
(when SCLS
=
H or Open, system clock =
192 fs)
BCKO
=
8.6436 MHz
(when SCSL
=
L, system clock =
196 fs)
Deglitch Signal
DGL:
L CH deglitch signal, 176.4 kHz (25% duty)
DGR: R CH deglitch signal, 176.4 kHz (25% duty)
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