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DPC-77
34
CIRCUIT DESCRIPTION
(5) Sub code output
Sub codes P~W
loaded in the 8-bit shift register are output
out of SBSO pin in accordance with the clock input through
EXCK pin. When SCOR pin is ''H'', SO+S1
signal is output.
Sub code Q is as follows, depending on the SQEX pin status.
a.
When the SQEX pin is ''L'', sub code Q is output from the
SUBO
pin in synchronism
with the WFCK
signal in the
same way as for the CX23035. The WFCK is also output
from the SQCK pin.
. When the SQEX pin is ''H'', sub code Q is output from the
SUBO pin in synchronism with the external clock (as from
the
microprocessor).
Two
80-bit
shift
registers,
for
(a) Timing of SBSO, SUBQ, SCOR, CRCF
vcol
CRCF
(b) Timing of SBSO, EXCK
reading and writing, are incorporated as shown in Fig. 7,
and while the microprocessor reads, the new sub code Q
is written to another register. The microprocessor is inter-
rupted from the outside at the rising edge of the SCOR pin,
and after checking the CRCF flag (output to the CRCF pin,
or the SUBQ pin when the CRCOQ flag is '1''}, the CRCE is
checked. If CRCF="'H"', a shift lock is output and the new
sub code Q is read. After the LSB side is replaced with the
MSB side by a unit of 4-bit, the data is stored in register.
As the microprocessor serially inputs from the LSB first,
replacing the 4-bit of data is unnecessary.
*1:
Sub code P is output when SCOR is O.
SO +S1 is output when SCOR is 1.
*2:
SBSO is 0 when 8 or more pulses are input to EXCK.
*3:
4T~6T
if the period of VCO is expressed as T.
"4:
Make EXCK low for 10 ys from the rising edge of WFCK.
One time period of
T=8.6436 MHz.
Fig. 5 Timing chart of sub code outputs
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