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DPC-77
CIRCUIT DESCRIPTION
(6) CLV-P:
Register E=1111'B
PLL servo mode.
When the NCLV of register 9 is ''O'', the phase
of the WFCK/4
signal and the phase of the
RFCK/4 signal are compared and output to the
MDP pin. When
NCLV=''1"',
1/4 of the base
counter frame frequencies at the Write side and
the Read side are phase-compared and output
to the MDP
pin. It goes ''H'' when
WFCK
is
slow, ''L'' when it is fast, and is ''Z'' when syn-
chronized.
Assuming the 8.4672/2
MHz period is T, and
the time when WFCK is ''H'' is thw, the MDS
MDP pin
pin outputs a signal which goes ''H"' during the
time from the trailing edge of WFCK to the time
represented
by
(thw-279T)x32,
and
then
goes ''L"' until the next trailing edge of WFCK.
MDS ="'H"
when thw2279T,
MDS
=''L"' when thwS$ 2797.
The MDS pin varies between 32T and 544T, in
32T steps, when 280TSthwS$296T.
For ex-
ample, when synchronized (rotating at the stan-
dard speed), that is when thw=288T,
a 7.35
kHz signal, with a duty cycle of 50% is output.
FSW="Z"',
MON="'H".
RFCK/4
(or RFCK/8)
|
|
|
|
|
|
|
jee
ie
cae
(or WFCK/8)
|
|
|
aig
MDP seed
VE os eS
a2
Z: High impedance
MDS pin (The period of 4.2336 MHz is expressed as ''T''.)
(1) When rotating at specified velocity
|
t
|
14
|
}+— 288T —+|
sis oem aes! SORTS (aaa ee a
|
{
!
/-— 288T ——+|
(2) When rotation becomes fast
}+-— 280T—|
WFCK
|
|
|
|
|
|
!
Se Gi hk 32T
Ne
ee
ee
(3) When rotation becomes slow
ho
as
WFCK
|
|
1
{
Si
Fig. 12
Timing chart in CLV-P mode
43
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