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CIRCUIT DESCRIPTION
Terminal explanations
Terminal | Terminal
name
FSW
Time constant switching output of output filter of spindle motor.
MON
ON/OFF control output of spindle motor.
MDP
Drive output of spindle motor. Rough speed control in CLV-S mode and phase control in CLV-P mode.
Function
MDS
Drive output of spindle motor. Speed control in CLV-P mode.
EFM
EFM signal input from RF amplifier.
ASY
[ Output for controlling the slice level of EFM signal.
LOCK
Samples the GFS signal with WFCK/16, and outputs ''H'' when the level is high.
When
it is ''L'' for eight times, in arrow, outputs ''L''.
VCOO
VCO output. f =8.6436 MHz when locked to EFM signal.
VCO!
VCO input.
TEST
(0 V)
"F
Phase comparison output of EFM signal and VCO/2.
GND (0 V)
Serial data transmission clock input from CPU. Data is latched at rising edge of a clock.
Latch input from CPU. Data (serial data from CPU) from the 8 bit shift register is latched in each register.
Serial data input from CPU.
System reset input. Reset at ''L''.
Input of tracking pulse.
Output of internal status in correspondence to the address.
"
Muting input. In the case when ATTM of internal register A is ''L
Normal status when MUTG
is *'L"' or soundless state when it is ''H''.
Output of result of CRC check of sub code Q.
Clock input for sub code serial output.
Sub code serial output.
Sub code Q output.
Sub code sync SO+S1
output.
Sub code Q read-off clock.
SQCK select input.
DIGITAL OUT output.
Display output of frame sync lock status.
Data pin of external RAM.
DATA8
(MSB)
Data pin of external RAM. DATA7
Data pin of external RAM.
DATA6
Data pin of external RAM.
DATA5
;
Power supply (+ 5 V)
Data pin of external RAM.
DATA4
Data pin of external RAM.
DATA3
Data pin of external RAM. DATA2
Data pin of external RAM.
DATA1
(LSB)
Address output of external RAM. ADDRO1
(LSB)
Address output of external RAM. ADDRO2
Address output of external RAM. ADDRO3
Address output of external RAM. ADDRO4
Address output of external RAM. ADDROD5
Address output of external RAM. ADDRO6
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